CN103018574A - Capacitance measurement circuit - Google Patents
Capacitance measurement circuit Download PDFInfo
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- CN103018574A CN103018574A CN2012104834696A CN201210483469A CN103018574A CN 103018574 A CN103018574 A CN 103018574A CN 2012104834696 A CN2012104834696 A CN 2012104834696A CN 201210483469 A CN201210483469 A CN 201210483469A CN 103018574 A CN103018574 A CN 103018574A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/16—Spectrum analysis; Fourier analysis
- G01R23/165—Spectrum analysis; Fourier analysis using filters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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Abstract
A capacitance measurement circuit is provided. In the capacitance measurement circuit of the invention, a pad that contacts an external capacitance is configured inside a feedback loop. As the capacitance value increases in turn, effects of a noise passing through the pad are reduced. Therefore, the capacitance measurement circuit is able to measure a correct capacitance value. Due to periodic testing of the contacted capacitance, the capacitance measurement circuit may eliminate the effects of the noise. And, the capacitance measurement circuit with a digital filter can have stable capacitance value.
Description
The application is to be that February 23, application number in 2010 are dividing an application of 201010118229.7 application for a patent for invention " capacitance measurement circuit " applying date.
Technical field
The present invention relates to capacitance measurement circuit, relate in particular to and to fall low noise capacitance measurement circuit.
Background technology
Capacitance measurement circuit (capacitance measurement circuit) refers to mainly be used in the electric capacity of measuring various circuit or element for the circuit of measuring electric capacity.But, recently along with various mancarried devices provide such as Trackpad, touch-screen and near the sensor user interface, can detect user's contact and the scope of application of close capacitance measurement circuit and enlarge gradually.
Fig. 1 is the synoptic diagram that an example of existing detection feeler is shown, and it is open in No. the 0683249th, Korean granted patent.The feeler of Fig. 1 comprises measuring-signal generating unit 10, reference signal generating unit 20, a plurality of transducing signal generating unit (30-1～30-n), a plurality of variable delay section (35-1～35-n), a plurality of activation signal generating unit (40-1～40-n) and control part 50.
Measuring-signal generating unit 10 is output as measuring-signal in clock signal, and measuring-signal in is outputed to reference signal generating unit 20 and each transducing signal generating unit (30-1～30-n).
Reference signal generating unit 20 is made of the first resistance R 1-1 and capacitor C, and whether uncorrelated it is with the contact that contacts object, measuring-signal in is postponed predetermined time always after output reference signal ref.The first resistance R 1-1 and capacitor C be used for to set for the variable delay signal (length of delay of the reference signal ref of Vsen2-1～Vsen2-n).
A plurality of transducing signal generating units (30-1～30-n) comprise respectively: lay respectively at the ((R2-1～R2-n) of the second resistance between the 35-1～35-n) of measuring-signal generating unit 10 and a plurality of variable delay section; (R2-1～R2-n) and a plurality of variable delay section are (between the 35-1～35-n) and be used for making the pad P AD that contacts object contact with electric capacity to lay respectively at the second resistance.(R2-1～R2-n) is used for making measuring-signal generating unit 10 to become identical with delay constituent adjustment between each pad P AD to each second resistance.A plurality of transducing signal generating units (30-1～30-n) have respectively for the pad P AD that contacts object, and output detection signal (sen2-1～sen2-n), with when the contact object touches pad P AD, postpone measuring-signal in relative datum signal ref more, when the contact object does not touch pad P AD, measuring-signal in relative datum signal ref is postponed still less, produce time delay thereby make between measuring-signal in and the reference signal ref.
The applicable all objects with predetermined static capacity of contact object, and as a representation example human body that can put aside a large amount of electric charges is arranged.
(35-1～35-n) responds respectively the control signal that receives from control part 50 (D1～Dn) afterwards in a plurality of variable delay section, the change detection signal (time delay of sen2-1～sen2-n), and according to exporting variable delay signal (Vsen2-1～Vsen2-n) time delay of change.Variable delay section (35-1～35-n) can be consisted of by a plurality of delay cells and impact damper, and a plurality of delay cell can be made of a multiplexer (multiplexer) and two phase inverters (inverter) respectively.
Multiplexer comprises two input ends and an output terminal and is used for from the selection input end of an input end of two input ends selections.Described selection input end is by the control signal that receives from control part 50 (the control signal control of the correspondence the D1～Dn).Two phase inverters play the effect with the output delay scheduled time of multiplexer.
A plurality of activation signal generating units (40-1～40-n) synchronous with reference signal ref respectively, and to variable delay signal (Vsen2-1～Vsen2-n) sample and latch after export activation signal (S1～Sn).(40-1～40-n) is respectively by (35-1～35-n) receives variable delay signal, and (Vsen2-1～Vsen2-n) is also received the reference signal ref of reference signal generating unit 20 and exported activation signal (d type flip flop (D Flip-Flop) of S1～Sn) consists of by sequential input end CLK from the variable delay section of correspondence for a plurality of activation signal generating units.
If the activation signal because pad P AD contact has the contact object (S1～when Sn) continuing to change, it is in running order that control part 50 detects feeler, and from (40-1～40-n) receives activation signal, and (S1～Sn) produces contact output (Tout-1～Tout-n) afterwards with the corresponding activation signal generating unit of the pad P AD that contacts; , pad P AD causes activation signal (S1～when Sn) not changing in the given time if not contacting object, control part 50 detects feeler and is in holding state, and begins to carry out the adjustment to the control signal that outputs to respectively a plurality of variable delay section (35-1～35-n)) in order to adjust time delay.
Fig. 2 is the synoptic diagram that another example of existing detection feeler is shown, and it is open in No. the 082656th, Korean granted patent.Pulse signal generating unit 60 is according to the pulsewidth of the code value setting pulse signal pul of the control routine code that transmits from control part 90, and the pulse signal pul of output with pulsewidth of having set.
Pulse signal generating unit 60 have pulse signal generator 61, variable delay chain (delay chains) VDC, phase inverter INV and with door AND.Clock signal clk occur in pulse signal generator 61, and with its be sent to respectively variable delay chain VDC and with door AND.Variable delay chain VDC responds the time delay of changing clock signal clk from the code value of the control routine of control part 90 transmission.Phase inverter INV reverses the clock signal dclk from variable delay chain VDC output.With door AND to the clock signal clk that transmits from pulse signal generator 61 and the clock signal that transmits through variable delay chain VDC and phase inverter INV (/dclk) carry out exporting after the logical and combination pulse signal pul that has corresponding to the pulsewidth of time delay of variable delay chain VDC.
By the pulse signal transfer part 70 that resistance R 3 and pad P AD consist of, when pad P AD did not contact object, pulse signal pul arrived pulse signal detection section 80 with original state transfer.But contact is when having the contact object with predetermined static capacity, and pulse signal pul can not be passed to pulse signal detection section 80 according to the electric capacity of the contact object that touches pad P AD.
At this moment, the applicable all objects with predetermined static capacity of contact object, and as a representation example human body that can put aside a large amount of electric charges is arranged.
The pulse signal pul that is transmitted by pulse signal transfer part 70 detects in pulse signal detection section 80, and testing result is circulated a notice of to control part 90.Pulse signal detection 80 can be made of T trigger TFF.
The T trigger is when return pulse signal pul, by the rising edge of pulse signal pul or negative edge synchronization and trigger output signal, and can trigger output signal when not having return pulse signal.
Control part 90 generates the contact whether output signal out that is used for circular contact object according to the testing result of pulse signal detection section 80, and this output signal out outputed to external device (ED), but also periodically carry out corrective action, under contactless state, the pulsewidth of pulse signal pul is proofreaied and correct as being suitable for current operating environment.During the output signal output that is triggered when the T trigger, control part 90 generates circular contact object does not have the output signal out signal of contact afterwards this output signal out to be outputed to the outside, otherwise, after the output signal out that then generation circular contact object has contacted this output signal out is outputed to the outside.
The detection feeler of above-mentioned Fig. 1 and Fig. 2 only detects and contacts or noncontact and exporting, size that can not output capacitance.And its characteristic of mancarried device is that surrounding enviroment often change, and therefore needs a kind of mancarried device that can prevent of research and development because of the various noises that cause along with environmental change capacitor measurement circuit misoperation, that can reduce noise effect to occur.
Summary of the invention
The present invention proposes in order to address the above problem, and its purpose is to provide a kind of capacitance measurement circuit that reduces noise effect.
To achieve these goals, capacitance measurement circuit of the present invention comprises: the measuring-signal generating unit, to be used for occuring measuring-signal; The fixed delay chain is to be used for making described measuring-signal postpone to export corresponding to the time of benchmark length of delay; Variable delay chain is to be used for making described measuring-signal postpone to export corresponding to the time of code value; The first delay section is to be used for the making output signal of described fixed delay chain postpone the set time and the output reference signal; The second delay section with the liner that contacts with external capacitive, to be used for electric capacity that response contacts by described liner with the output signal variation of described variable delay chain and delay and output detection signal; The data generating unit, to be used for responding the delay-time difference of described reference signal and described transducing signal described capacitance is increased or reduce after output, and respond described capacitance and export after changing described code value.
And described data generating unit comprises: phase-detection section, with the output detection signal for the delay-time difference that responds described reference signal and described transducing signal; Postpone pump, to be used for responding described detection signal capacitance is increased successively by predetermined rule or reduce after output, and respond described capacitance and will output to described variable delay chain after the described code value change.
And described phase-detection section is trigger, and it has with the rising edge of described reference signal or negative edge and latchs synchronously the logical circuit of exporting described detection signal after the described transducing signal.
And described delay pump comprises: counter makes capacitance increase successively or reduce afterwards output by predetermined rule to be used for responding described detection signal; Subtracter is to be used for exporting described code value after described benchmark length of delay deducts described capacitance.
And described counter responds described detection signal and capacitance is increased or reduce afterwards output successively by predetermined unit.
And, when described counter is high level or low level when described detection signal continuous wave output, make capacitance increase successively or reduce afterwards output according to the change unit change.
And described delay pump also comprises the digital filter with output after described code value or the filtration of described capacitance.
And digital filter is low-pass filter or bandpass filter, be used for receiving and the described code value of stabilization or capacitance, and eliminates noise.
And described counter and described digital filter are realized with software.
And described counter responds described reference signal and receives described detection signal.
And described counter responds described measuring-signal and receives described detection signal.
And described the first delay section is the first resistance that is connected between described fixed delay chain and the described phase-detection section.
And described the second delay section also comprises the second resistance that is connected between described variable delay chain and the described phase-detection section.
To achieve these goals, capacitance measurement circuit of the present invention comprises: the pulse signal generating unit, and the pulsewidth that changes clock signal to be used for the response capacitance produces pulse signal afterwards; Pulse signal transfer part with the liner that contacts with external capacitive is carried out transmission or is not transmitted described pulse signal by the electric capacity of described liner contact to be used for response; Pulse signal detection section is to be used for periodically detecting by the described pulse signal of described pulse signal transfer part reception output detection signal; Counter is to increase count value successively by predetermined rule for responding described detection signal or to reduce; Digital filter is to export described capacitance after described count value is filtered.
And described pulse signal generating unit comprises: pulse signal generator, to be used for occuring clock signal; Variable delay chain is to export afterwards for according to described capacitance described clock signal being changed and postponing; Phase inverter is to be used for that the output signal of described delay chain is reversed afterwards output; With door, to be used for that the output signal of described clock signal and described phase inverter is carried out logical multiply, with the described pulse signal of generation corresponding to the pulsewidth of the time delay of described clock signal.
And described pulse signal transfer part also comprises and is connected in described pulse signal generating unit between described pulse signal detection section and suppresses the resistance of the transmission of described pulse signal with the electric capacity that contacts by described liner.
And described pulse signal detection section comprises: the T trigger, detect described pulse signal to be used for the response clock signal, and produce the described pulse signal of response and the output signal that is triggered; The cycle arbiter, whether periodic triggers is come output detection signal to be used for output signal by differentiating described T trigger.
And described T trigger comprises: set-reset flip-floop outputs to the described pulse signal that terminal or the some terminals of replacement terminal are set and exports described detection signal to be used for response; D type flip flop is exported after latching described detection signal to be used for responding described clock signal; Multiplexer is selected to be used for responding the output signal of described d type flip flop describedly to transmit described pulse signal after terminal or the some terminals of replacement terminal are set.
And described counter responds described detection signal and makes capacitance increase successively or reduce afterwards output with predetermined unit.
And, when described counter is high level or low level when described detection signal continuous wave output, make capacitance increase successively or reduce afterwards output according to the change unit change.
And described digital filter is low-pass filter or bandpass filter, be used for receiving and the described count value of stabilization, and exports described capacitance after eliminating noise.
And described counter and described digital filter are realized with software.
Therefore, capacitance measurement circuit of the present invention is arranged on backfeed loop (feedback loop) inside from the liner of external contact electric capacity, and, be subject to therefore, can measuring correct capacitance along with the impact that increases successively the noise that capacitance transmits by liner is less.
Description of drawings
Fig. 1 is the synoptic diagram that an example of existing detection feeler is shown;
Fig. 2 is the synoptic diagram that another example of existing detection feeler is shown;
Fig. 3 is the synoptic diagram that illustrates according to an example of capacitance measurement circuit of the present invention;
Fig. 4 illustrates that calculate time delay and the synoptic diagram of the capacitance measurement circuit of Fig. 3 of the Application Example of data generating unit;
Fig. 5 to Fig. 7 is the synoptic diagram for the action of the capacitance measurement circuit of key diagram 4;
Fig. 8 is the synoptic diagram that illustrates according to another example of capacitance measurement circuit of the present invention;
Fig. 9 is the synoptic diagram of Application Example that the T trigger of Fig. 8 is shown.
The main symbol description of accompanying drawing: 110 is that measuring-signal generating unit, 120 is that variable delay section, 130 is fixed delay section, 141 is phase-detection section, 142 for postponing pump, 211 is pulse signal generator, 210 is the clock signal generating unit, 220 is the pulse signal transfer part, and 210 is the pulse signal generating unit, and 230 is pulse signal detection section, 231 is the T trigger, 232 is the cycle arbiter, and 241 is counter, and 242 is digital filter, 240 for postponing pump, 331 is multiplexer, and 332 is set-reset flip-floop, and 333 is d type flip flop.
Embodiment
Below, describe capacitance measurement circuit of the present invention in detail with reference to accompanying drawing.
Fig. 3 is the synoptic diagram that illustrates according to an example of capacitance measurement circuit of the present invention.The detection feeler of capacitance measurement circuit shown in Figure 3 and Fig. 1 is similar, that is, comprise and calculating and data generating unit 140 measuring-signal generating unit 110, variable delay section 120, fixed delay section 130 and time delay.The measuring-signal generating unit 110 applicable clock signals that will have predetermined period are output as the timing generator circuit of measuring-signal in.
Fixed delay section 130 is in parallel with variable delay section 120, this fixed delay section 130 comprise and measuring-signal generating unit 110 and data generating unit 140 between the fixed delay chain FDC and the resistance R 2 that are connected in series.Fixed delay chain FDC makes the measurement range maximization of electric capacity for building-out capacitor side-play amount (offset), receive the benchmark length of delay Nref for the zero point of adjusting the code value Code that outputs to variable delay chain VDC.Fixed delay chain FDC responds benchmark length of delay Nref and postpones to export measuring-signal in, resistance R 2 is appended delay according to resistance value to the measuring-signal that postpones to export at fixed delay chain FDC, calculates and data generating unit 140 reference signal ref is outputed to time delay.
(35-1～35-n) the same can be made of a plurality of delay cells, and a plurality of delay cell can be made of a multiplexer and two phase inverters respectively in the variable delay section of fixed delay chain FDC and variable delay chain VDC and Fig. 1.Select to be used for the delay cell of delay measurement signal in after fixed delay chain FDC responds benchmark length of delay Nref, select to be used for the delay cell of delay measurement signal in after variable delay chain VDC responds code value Code.
Calculating and data generating unit 140 comprised phase-detection section 141 and postponed pump (delaypump) 142 time delay.The speed of the transducing signal sen phase place of relative datum signal ref is differentiated by phase-detection section 141, and output detection signal det.Postpone to calculate capacitance CV after pump (delay pump) the response detection signal det, and the capacitance CV that calculates is responded and improves (up) or reduce after (down) code value Code its output.
In the capacitance measurement circuit of Fig. 3, variable delay section 120 and fixed delay section 130 directly receive measuring-signal in by variable delay chain VDC and fixed delay chain FDC from measuring-signal generating unit 110 respectively.And then, calculate the time delay that the pad P AD that contacts with external capacitive is arranged at the variable delay chain VDC of the capacitance CV that reception feeds back and output capacitance value CV and data generating unit 140 between, therefore, pad P AD is arranged at backfeed loop (feedback loop) inside.
Noise might occur in capacitance measurement circuit inside, but most of situation is for to import into from the outside by pad P AD.That is, in order to reduce noise, it is the most effective to eliminate the noise that transmits by pad P AD.But therefore the detection feeler of Fig. 1, is difficult to reduce the noise that transmits by pad P AD because pad P AD is connected in the backfeed loop outside.In contrast, in the capacitance measurement circuit of Fig. 3, be connected in backfeed loop inside from the pad P AD of external contact electric capacity.If liner is connected in backfeed loop inside, then according to the characteristic of backfeed loop (attenuation) noise of can decaying.
Fig. 4 illustrates that calculate time delay and the synoptic diagram of the capacitance measurement circuit of Fig. 3 of the Application Example of data generating unit.In Fig. 4, because measuring-signal generating unit 110 is identical with Fig. 3 with variable delay section 120 and fixed delay section 130, therefore, do not explain in addition.
For calculating time delay and data generating unit 140 of Fig. 4, the 141 usefulness d type flip flop D-FF of phase-detection section realize having counter cnt and subtracter SUB and postpone pump 142.D type flip flop D-FF is also exported by the some transducing signal sen that latchs afterwards synchronously in the rising edge of reference signal ref or the negative edge.When the delay of transducing signal sen during less than reference signal ref, the detection signal det of d type flip flop D-FF output low level, when the delay of transducing signal sen during greater than reference signal ref, the detection signal det of d type flip flop D-FF output high level.Postpone pump 142 and play negative feedback (negative feedback) effect that when detection signal det is low level, improves code value Code, when detection signal det is high level, reduces code value Code, so that the phase place of the transducing signal sen of variable delay section 120 is identical with the phase place of the output signal ref of fixed delay section 130.Between fixed delay section 130 and variable delay section 120, might postpone side-play amount owing to pad P AD, surpass the setting range of variable delay chain if described side-play amount is large, then can surpass the working range of the capacitance measurement circuit of Fig. 4.At this moment, the benchmark length of delay Nref of fixed delay section 130 compensates the electric capacity side-play amount, so that the code value Code of variable delay chain is in variation and delay scope.Among Fig. 4, used d type flip flop D-FF as an example of phase-detection section 141, but also can use other logical circuits.
Counter cnt improves or reduces the up/down counter (up/down counter) of exporting after the capacitance CV for detection signal det is responded.Counter cnt improves take 1 bit (bit) as unit or reduces after the capacitance CV its output according to the level of detection signal det.But when after counter cnt improves take 1 bit as unit or reduces capacitance CV it being exported, if the size of the electric capacity by pad P AD contact is larger, the time of then measuring electric capacity is longer.In order to remedy this problem, counter cnt does not improve or reduces capacitance CV take 1 bit as unit, when detection signal det continuous wave output is high level or low level, with the order of 1 bit, 2 bits, 4 bits, 8 bits, namely improve or reduce capacitance CV afterwards with its output with 2 power side.Perhaps, also can improve or reduce capacitance CN afterwards with its output according to predetermined rule.And, more than show the situation that is received detection signal det by counter cnt response reference signal ret, but also can response measurement signal in and receive detection signal det.
Subtracter SUB is by deducting capacitance CV and output code value Code from benchmark length of delay Nref.Therefore, capacitance CV represents the total capacitance value of pad P AD contact, but, when the capacitance of pad P AD contact increases, by phase-detection section 141 and the code value Code that postpones backfeed loop that pump 142 consists of and deduct the recruitment that is equivalent to the electric capacity that contact by pad P AD, with the retardation of shortening variable delay chain.And, when the capacitance of pad P AD contact reduces, increase the code value of the amount that is equivalent to reduce, to increase the retardation of variable delay chain.As a result, it is identical with the phase place of reference signal ref to be controlled to be the transducing signal sen that is input to phase-detection section 141, and then, the electric capacity of capacitance CV and pad P AD contact big or small corresponding.
At this, the benchmark length of delay Nref that is input to subtracter SUB is identical with the signal of control fixed delay chain FDC, still, also may be controlled to difference.And, in the explanation of Fig. 3 and Fig. 4, having fixed delay chain FDC, still, also can omit.
Fig. 5 to Fig. 7 is the synoptic diagram for the action of the capacitance measurement circuit of key diagram 4.Figure be 5 when pad P AD hand capacity is shown transducing signal sen and the synoptic diagram of the variation of detection signal set.
Reference signal ref postpones fixing time delay according to fixed delay section 130 with measuring-signal in and exports, and therefore has the identical cycle of measuring-signal in.Because during the capacitance measurement circuit virgin work, capacitance CV is 0, therefore initial stage code value Code is identical with benchmark length of delay Nref, and, identical with the time of fixed delay chain FDC delay measurement signal in by the time of variable delay chain VDC delay measurement signal in.Therefore, at the capacitance measurement circuit work initial stage, transducing signal sen compares reference signal ref according to the electric capacity of pad P AD self and more postpones to output to afterwards d type flip flop D-FF.
Because transducing signal sen more postpones than reference signal ref, therefore at the negative edge of reference signal ref, transducing signal sen is output as high level, and detection signal det is output as high level.Because detection signal det is high level, so counter cnt improves capacitance CV and exports 1, and exports owing to subtracter SUB deducts capacitance CV in benchmark length of delay Nref, and therefore, code value Code is lowered and is output as benchmark length of delay-1.
Variable delay chain VDC responds code value Code and output after shortening time delay of measuring-signal in, and along with the time delay that shortens transducing signal sen, also is shortened with the delay-time difference of reference signal ref.Delay-time difference between transducing signal sen and the reference signal ref is shortened gradually, thus when time delay of transducing signal sen or more in short-term t1 identical with the time delay of reference signal ref, d type flip flop D-FF changes to low level with detection signal det.
Afterwards, t2 when contacting with external capacitive by pad P AD, transducing signal sen appends delay according to the electric capacity of contact, and the detection signal det of d type flip flop D-FF output high level.When detection signal det was output as high level, as mentioned above, until the time delay of transducing signal sen is identical with the time delay of reference signal ref or shorter, capacitance CV increased t3 gradually.And, the afterwards increase of capacitance CV with reduce and will repeatedly carry out.
Fig. 6 illustrates the variation of the capacitance CV of the capacitance measurement circuit that has take 1 bit as unit the counter cnt that improves/reduce capacitance CV, and Fig. 7 illustrates has the variation of capacitance CV of capacitance measurement circuit that improves/reduce the counter cnt of capacitance CV according to predetermined rule.
Therefore at Fig. 6, counter cnt improves take 1 bit as unit/reduces, and when the electric capacity that contacts by pad P AD is larger, it is longer that capacitance CV is expressed as the required time of electric capacity of contact.But in the same manner, counter cnt improves take 1 bit as unit/reduction work, and therefore, even temporary transient produce larger noise, the capacitance CV that changes according to noise also is 1 bit, thereby the suffered impact of capacitance CV is less.
Fig. 7 illustrates to be improved/reduce the rule of capacitance CV by counter cnt, and detection signal det is continuous when being output as high level or low level 3 times, increases the example of the appointment of the bit number that improves/reduce.That is, when detection signal det continuous wave output is high level, the bit number that per three increases improve.For example, when detection signal det continuous wave output is high level or low level, the capacitance of first three time change 1 bit, the afterwards capacitance of three change 2 bits.And when reversing the low level into detection signal det, the bit number by the raising before reducing/reduction reduces capacitance CV.Therefore, even the larger electric capacity of contact also can represent capacitance CV within a short period of time.The capacitance of Fig. 7 is compared the amplitude that the capacitance CV of Fig. 6 changes when noise occurs larger, but because the boundary of amplitude of variation is little, so noise is given less with the impact of capacitance CV.Especially, because pad P AD is arranged at backfeed loop inside, the direct reception of variable delay chain VDC does not contain noisy measuring-signal in, and the code value Code that considers the noise effect of transmitting by pad P AD responded postpones output, therefore according to the characteristic attenuation noise of backfeed loop.
More than, illustrated that data generating unit 140 has d type flip flop D-FF and up/down counter cnt, so that capacitance CV is improved gradually/reduces, but also can export the capacitance CV that touches pad P AD with respect to the delay-time difference of the transducing signal sen of reference signal ref by direct calculating.
And, postpone pump 142 and also can have the digital filter that capacitance CV is filtered and exports in order to eliminate noise.At above-described embodiment, capacitance CV is subject to exporting in the situation of restriction of amplitude of variation, and therefore, code value Code amplitude of variation also will be restricted.But, include noise if code value Code with to a certain degree above changes in amplitude, then can be judged as.Therefore, also can comprise wave digital lowpass filter or digital band-pass filter, with as receiving from subtracter SUB and filtering code value Code and output to the digital filter of variable delay chain VDC.And, even in the situation of code value Code not being filtered, directly capacitance CV is filtered and exports, also can obtain identical effect.When also can be used for adjusting the noisiness of capacitance measurement circuit, digital filter adjusts the characteristic of backfeed loop.And because the delay-time difference of reference signal ref and transducing signal sen is shortened fully, when backfeed loop was stablized, capacitance CV vibrated (repeatedly increase and reduce) take+1/-1 as unit, but this can utilize digital filter to be fixed.That is, give hysteresis (Hysteresis) characteristic to digital filter, to prevent the microvibration at the lower capacitance CV of steady state (SS) (steady state).
And the digital filter of described counter cnt realizes with hardware that not only also available software realizes.
Fig. 8 is the synoptic diagram that illustrates according to another example of capacitance measurement circuit of the present invention.At this, pulse signal generating unit 210 and pulse signal transfer part 220 are similar with the structure of Fig. 2, and therefore the description thereof will be omitted.
And at Fig. 2, pulse signal detection section 80 has only used the T trigger.But as mentioned above, most noise is more by the situation that pad P AD transmits, and the T trigger of Fig. 2 directly is connected with pad P AD, therefore, when the pulse signal genration noise, T trigger TFF might be by more than triggering once in the pulse signal by pad P AD.At Fig. 8, in order to make the periodicity of cycle arbiter 232 correct decision pulses, the T trigger is only once triggered to a pulse input.The T trigger of Fig. 8 only once triggers a pulse input in order to address the above problem, and it is such as the trigger circuit of Fig. 9.
The pulse signal detection section 230 of Fig. 8, the return pulse signal pul by T trigger 231 response clock signal clk, so the output signal of T trigger 231 can not triggered by noise.And the pulse signal detection section 230 of Fig. 8 also comprises for the output signal of the differentiating T trigger 231 cycle arbiter 232 of periodic triggers whether.Periodically whether cycle arbiter 232 response clock signal clk and the output signal of differentiating T trigger 231 migration, if the output signal of T trigger 231 periodically shifts, then the detection signal det of output low level if do not carry out the periodicity migration, then exports the detection signal det of high level.
The detection feeler of Fig. 2 only detects contact or noncontact, but the capacitance measurement circuit of Fig. 8 need to come output capacitance value CV by the size of measuring the electric capacity that contacts by pad P AD, therefore, postponing pump 240 has and the similar counter 241 of Fig. 4 and digital filter 242.Counter 241 is the up/down counter, and it responds clock signal and receives detection signal det, and according to take 1 bit as unit or predetermined rule export after improving/reduce count value Cout.As mentioned above, for the characteristic of the noisiness of together adjusting capacitance measurement circuit and backfeed loop and use digital filter 242, it has hysteresis (Hysteresis) characteristic, and output capacitance value CV after count value Cout is filtered changes continuously to prevent capacitance CV.
More than, illustrated by counter 241 response clock signal clk and receive detection signal det, but counter 241 can not receive clock signal clk when being the asynchronous type counter.And cycle arbiter 232 also for the output signal of differentiating T trigger 231 periodic triggers whether, also can use the another kind of signal that is not clock signal clk.
And, at Fig. 8, variable delay chain VDC response capacitance CV and change and postpones clock signal clk afterwards with its output.
Fig. 9 is the trigger circuit of Application Example that the T trigger of Fig. 8 is shown, and this goes out Power Generation Road and comprises a multiplexer (Mux) and set-reset flip-floop (SRF) and d type flip flop (DF).
The output signal of multiplexer 331 response d type flip flops 333 is return pulse signal pul afterwards, and outputs to setting (set) terminal S or replacement (reset) the terminal R of set-reset flip-floop 332.When multiplexer 331 is output as low level as detection signal det, pulse signal pul is outputed to terminal S is set, when detection signal det is high level, pulse signal pul is outputed to replacement terminal R.
When set-reset flip-floop 332 during not from multiplexer 331 return pulse signal, the level of detection signal det before keeping, and when the signal of terminal S reception high level is set, the detection signal det of high level is outputed to delay pump 340, and when replacement terminal R receives the signal of high level, the detection signal det of output low level.
D type flip flop 333 responds from the clock signal clk of pulse signal generator 311 outputs and latchs detection signal det, and it is outputed to multiplexer 331.D type flip flop 333 latchs detection signal det by response clock signal clk and decides the output signal of multiplexer 331 should output on earth which terminal among terminal S or the replacement terminal R of arranging of set-reset flip-floop 332.
As mentioned above, be illustrated with reference to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that in the scope that does not break away from claims record and carry out various changes.
Claims (9)
1. capacitance measurement circuit is characterized in that comprising:
The pulse signal generating unit, the pulsewidth that changes clock signal to be used for the response capacitance produces pulse signal afterwards;
Pulse signal transfer part with the liner that contacts with external capacitive is carried out transmission or is not transmitted described pulse signal by the electric capacity of described liner contact to be used for response;
Pulse signal detection section is to be used for periodically detecting by the described pulse signal of described pulse signal transfer part reception output detection signal;
Counter is to increase count value successively by predetermined rule for responding described detection signal or to reduce;
Digital filter is to export described capacitance after described count value is filtered.
2. capacitance measurement circuit according to claim 1 is characterized in that described pulse signal generating unit comprises:
Pulse signal generator is to be used for occuring clock signal;
Variable delay chain is to export afterwards for according to described capacitance described clock signal being changed and postponing;
Phase inverter is to be used for that the output signal of described delay chain is reversed afterwards output;
With door, to be used for that the output signal of described clock signal and described phase inverter is carried out logical multiply, with the described pulse signal of generation corresponding to the pulsewidth of the time delay of described clock signal.
3. capacitance measurement circuit according to claim 1 is characterized in that described pulse signal transfer part also comprises to be connected in described pulse signal generating unit between described pulse signal detection section and to suppress the resistance of the transmission of described pulse signal with the electric capacity that contacts by described liner.
4. capacitance measurement circuit according to claim 1 is characterized in that described pulse signal detection section comprises:
The T trigger detects described pulse signal to be used for the response clock signal, and produces the output signal that responds described pulse signal and be triggered;
The cycle arbiter, whether periodic triggers is come output detection signal to be used for output signal by differentiating described T trigger.
5. capacitance measurement circuit according to claim 4 is characterized in that described T trigger comprises:
Set-reset flip-floop outputs to the described pulse signal that terminal or the some terminals of replacement terminal are set and exports described detection signal to be used for response;
D type flip flop is exported after latching described detection signal to be used for responding described clock signal;
Multiplexer is selected to be used for responding the output signal of described d type flip flop describedly to transmit described pulse signal after terminal or the some terminals of replacement terminal are set.
6. capacitance measurement circuit according to claim 1 is characterized in that described counter responds described detection signal and makes capacitance increase successively or reduce afterwards output with predetermined unit.
7. capacitance measurement circuit according to claim 1 is characterized in that described counter when described detection signal continuous wave output is high level or low level, makes capacitance increase successively or reduce afterwards output according to the change unit change.
8. capacitance measurement circuit according to claim 1 is characterized in that described digital filter is low-pass filter or bandpass filter, be used for receiving and the described count value of stabilization, and exports described capacitance after eliminating noise.
9. capacitance measurement circuit according to claim 1 is characterized in that described counter and described digital filter realize with software.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2009-0014944 | 2009-02-23 | ||
| KR1020090014944A KR101063537B1 (en) | 2009-02-23 | 2009-02-23 | Capacitance Measurement Circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101182297A Division CN101813726B (en) | 2009-02-23 | 2010-02-23 | Capacitance measurement circuit |
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| Publication Number | Publication Date |
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| CN103018574A true CN103018574A (en) | 2013-04-03 |
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
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| CN2012104834696A Pending CN103018574A (en) | 2009-02-23 | 2010-02-23 | Capacitance measurement circuit |
| CN2010101182297A Expired - Fee Related CN101813726B (en) | 2009-02-23 | 2010-02-23 | Capacitance measurement circuit |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101182297A Expired - Fee Related CN101813726B (en) | 2009-02-23 | 2010-02-23 | Capacitance measurement circuit |
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|---|---|
| JP (1) | JP5165708B2 (en) |
| KR (1) | KR101063537B1 (en) |
| CN (2) | CN103018574A (en) |
| TW (1) | TWI412756B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101172798B1 (en) * | 2010-11-04 | 2012-08-10 | 주식회사 애트랩 | Capacitance measurement circuit and method for measuring capacitance thereof |
| US9323385B2 (en) * | 2011-04-05 | 2016-04-26 | Parade Technologies, Ltd. | Noise detection for a capacitance sensing panel |
| CN103424616B (en) * | 2013-08-22 | 2015-10-07 | 宁波三星智能电气有限公司 | Artificial capacitor filter pulse acquisition method |
| US10042483B2 (en) * | 2014-04-18 | 2018-08-07 | Atmel Corporation | Touch system with code hopping algorithms and code division multiplexing |
| US10204737B2 (en) | 2014-06-11 | 2019-02-12 | Avx Corporation | Low noise capacitors |
| US10408870B2 (en) * | 2016-06-28 | 2019-09-10 | Himax Technologies Limited | Capacitor sensor apparatus and sensing method thereof |
| CN106932650A (en) * | 2017-03-03 | 2017-07-07 | 广东合微集成电路技术有限公司 | A kind of sensor capacitance value detection method |
| CN110764394A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Time-to-digital conversion circuit applied to SPAD detector |
| US11281314B2 (en) * | 2019-12-02 | 2022-03-22 | Semiconductor Components Industries, Llc | Methods and apparatus for variable capacitance detection |
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- 2010-02-23 TW TW099105196A patent/TWI412756B/en not_active IP Right Cessation
- 2010-02-23 CN CN2010101182297A patent/CN101813726B/en not_active Expired - Fee Related
- 2010-02-23 JP JP2010037291A patent/JP5165708B2/en not_active Expired - Fee Related
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| US5585733A (en) * | 1992-09-10 | 1996-12-17 | David Sarnoff Research Center | Capacitive sensor and method of measuring changes in capacitance |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101813726B (en) | 2013-03-20 |
| JP5165708B2 (en) | 2013-03-21 |
| TW201031932A (en) | 2010-09-01 |
| JP2010197390A (en) | 2010-09-09 |
| KR101063537B1 (en) | 2011-09-07 |
| CN101813726A (en) | 2010-08-25 |
| KR20090026791A (en) | 2009-03-13 |
| TWI412756B (en) | 2013-10-21 |
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Application publication date: 20130403 |