CN103016818B - Piezoelectric valve drive amplifier circuit - Google Patents
Piezoelectric valve drive amplifier circuit Download PDFInfo
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- CN103016818B CN103016818B CN201210574518.7A CN201210574518A CN103016818B CN 103016818 B CN103016818 B CN 103016818B CN 201210574518 A CN201210574518 A CN 201210574518A CN 103016818 B CN103016818 B CN 103016818B
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Abstract
The embodiment of the invention provides a piezoelectric valve drive amplifier circuit, which comprises two first logic circuits and two second logic circuits. By arranging a logic NOT gate in each first logic circuit, after an input signal passes through the two second logic circuits, output signals are the same with the input signal; and after the input signal passes through the two first logic circuits, the output signals are opposite to the input signal, so as to achieve the goal of controlling the output signals through the piezoelectric valve drive amplifier circuit when a single-chip microcomputer is reset in the prior art.
Description
Technical field
The application relates to valve positioner technical field, particularly relates to a kind of piezo electric valve drive amplification circuit.
Background technique
Pneumatic control valve is one of widely used industrial process control instruments of enterprise such as oil, chemical industry, electric power, pharmacy, metallurgy.Pneumatic control valve forms after normally being debugged by pneumatic actuator and modulating valve connection, enter the pneumatic signal size of pneumatic actuator by control, the aperture of regulating and controlling valve, thereby the rate-of flow of production control device reaches predetermined value, wherein, controlling the size of pneumatic signal that enters pneumatic actuator mainly completes by electropneumatic valve positioner.Therefore, electropneumatic valve positioner plays conclusive effect in the control performance of whole modulating valve and on-the-spot function.
In prior art, electropneumatic valve positioner can be divided into electromagnetic type electropneumatic valve positioner and piezoelectricity type electropneumatic valve positioner.Because piezoelectricity type valve positioner adopts the high piezoceramic material of internal resistance, micro power consumption, more favourable in the time of composition intrinsic safe explosion-proof structure, therefore extensively favored.
In prior art, be mainly by the piezo electric valve drive amplification circuit in Single-chip Controlling piezoelectricity type electropneumatic valve positioner, thereby realize the aperture of the output control valve of voltage.But, (send out strong interference) under special circumstances, may cause the situation of monolithic processor resetting.When occurring after the situation of monolithic processor resetting, although can recover by WATCHDOG, but general piezoelectricity type electropneumatic valve positioner is after single-chip microcomputer resets, the Piezoelectric Driving amplification circuit of piezoelectricity type electropneumatic valve positioner will lose the control to output signal, thereby cause the uncontrolled situation of valve location, when this thing happens on some crucial station, also may there is potential safety hazard.
Summary of the invention
In view of this, the embodiment of the present application provides a kind of piezo electric valve drive amplification circuit, to solve in prior art in the time that single-chip microcomputer occurs to reset, and the problem that cannot control output signal.
To achieve these goals, the technological scheme that the embodiment of the present application provides is as follows:
A kind of piezo electric valve drive amplification circuit, comprising: two the first logical circuits and two the second logical circuits, wherein,
Described the first logical circuit and described the second logical circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance, the second resistance, inductance and reference diode, wherein:
The drain electrode of described the first metal-oxide-semiconductor is connected with the first reference voltage end; The source electrode of described the first metal-oxide-semiconductor is connected with one end of described inductance, and the other end of described inductance is connected with signal output part; The grid of described the first metal-oxide-semiconductor is connected with described the first reference voltage end by described the first resistance;
The drain electrode of described the second metal-oxide-semiconductor is connected with the grid of described the first metal-oxide-semiconductor; The source electrode of described the second metal-oxide-semiconductor is connected with grounding end; The grid of described the second metal-oxide-semiconductor is connected with signal input part;
The negative electrode of described reference diode is connected with the grid of described the first metal-oxide-semiconductor, and the anode of described reference diode is connected with the source electrode of described the first metal-oxide-semiconductor;
One end of described the second resistance is connected with the grid of described the second metal-oxide-semiconductor, and the other end is connected with described grounding end;
In each described the first logical circuit, be provided with a logic inverter; In described first logical circuit, described logic inverter is connected in described the first logical circuit between the grid of the second metal-oxide-semiconductor and the signal input part of described the first logical circuit, and the output terminal of described logic inverter is connected with the grid of the second metal-oxide-semiconductor in described the first logical circuit, and the input end of described logic inverter is connected with the signal input part of described the first logical circuit.
Preferably, each described the second logical circuit is provided with diode in all;
Described diode is connected in described the second logical circuit between the grid of the second metal-oxide-semiconductor and the signal input part of described the second logical circuit, and the negative electrode of described diode is connected with the grid of described the second metal-oxide-semiconductor, the anode of described diode is connected with the signal input part of described the second logical circuit.
Preferably, in first logical circuit, the other end of the second resistance is connected as common port with the other end of the second resistance in second logical circuit, and described circuit also comprises switching circuit, and described switching circuit comprises the 3rd metal-oxide-semiconductor, the 3rd resistance, the 4th resistance and the 5th resistance, wherein
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described common port;
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described the first reference voltage end by described the 3rd resistance;
The source electrode of described the 3rd metal-oxide-semiconductor is connected with described grounding end;
The grid of described the 3rd metal-oxide-semiconductor is connected with the second reference voltage end by described the 4th resistance;
The grid of described the 3rd metal-oxide-semiconductor is connected with reference signal input end by described the 5th resistance.
From above technological scheme, the piezo electric valve drive amplification circuit that the embodiment of the present application provides, comprise two the first logical circuits and two the second logical circuits, by a logic inverter is set respectively in each the first logical circuit, make when input signal is respectively by after two the second logical circuits, output signal is identical with input signal.But when input signal is respectively by after two the first logical circuits, output signal is contrary with input signal, thereby realize in prior art in the time of single-chip microcomputer generation reset, can control output signal.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present application or technological scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiments that record in the application, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of piezo electric valve drive amplification circuit diagram that Fig. 1 provides for the embodiment of the present application one;
A kind of piezo electric valve drive amplification circuit diagram that Fig. 2 provides for the embodiment of the present application two.
Embodiment
In order to make those skilled in the art person understand better the technological scheme in the application, below in conjunction with the accompanying drawing in the embodiment of the present application, technological scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment who obtains under creative work prerequisite, all should belong to the scope of the application's protection.
Embodiment one
A kind of piezo electric valve drive amplification circuit diagram that Fig. 1 provides for the embodiment of the present application one.
As shown in Figure 1, this Piezoelectric Driving amplification circuit comprises: two the first logical circuits 1 and two the second logical circuits 2, wherein, in two described the first logical circuits 1 and two described the second logical circuits 2, be provided with the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first resistance R 1, the second resistance R 2, inductance L and reference diode ZD, in each described the first logical circuit 1, be also respectively arranged with a logic inverter X.
Introduce the annexation of each device in two the second logical circuits below.
The drain electrode of the first metal-oxide-semiconductor M1 is connected with the first reference voltage end, and in the embodiment of the present application, the voltage of the first reference voltage end can be 24V.The first source electrode of metal-oxide-semiconductor M1 and one end of inductance L are connected, and the other end of inductance L is connected with signal output part, and signal output part is mainly used in the output of logical circuit signal.The grid of the first metal-oxide-semiconductor M1 is connected with the first reference voltage end by the first resistance R 1.
The drain electrode of the second metal-oxide-semiconductor M2 is connected with the grid of the first metal-oxide-semiconductor M1, and the source electrode of the second metal-oxide-semiconductor M2 is connected with grounding end, and the grid of the second metal-oxide-semiconductor M2 is connected with signal input part, and signal input part is mainly used in the input of signal.
The negative electrode of reference diode ZD is connected with the grid of the first metal-oxide-semiconductor M1, and the anode of reference diode ZD is connected with the source electrode of the first metal-oxide-semiconductor M1.
One end of the second resistance R 2 is connected with the grid of the second metal-oxide-semiconductor M2, and the other end is connected with grounding end.
In two the first logical circuits, except comprising each device in two the second logical circuits of above-mentioned introduction, also comprise respectively a logic inverter X.The annexation of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first resistance R 1, the second resistance R 2, inductance L and reference diode ZD in two the first logical circuits, the annexation that refers to all parts in above-mentioned two the second logical circuits, repeats no more here.
In each the first logical circuit, be provided with a logic inverter X, this logic inverter X is connected between the grid and signal input part of the second metal-oxide-semiconductor M2, and the input end of this logic inverter X is connected with signal input part, the output terminal of logic inverter X is connected with the grid of the second metal-oxide-semiconductor.
In the embodiment of the present application, the arrangement mode of two the first logical circuits and two the second logical circuits can arrange arbitrarily.Two the first logical circuits that Fig. 1 is given and the arrangement mode of two the second logical circuits are a kind of optimal way, and inventor can arrange arbitrarily according to the demand of oneself.
As shown in Figure 1, the piezo electric valve drive amplification circuit providing when the embodiment of the present application, in the time that single-chip microcomputer occurs to reset, the input signal of the signal input part of piezo electric valve drive amplification circuit is respectively IN1=0, IN2=0, IN3=0 and IN4=0, this input signal is respectively after two the first logical circuits and the second logical circuit, the output signal of signal output part is IN1=1, IN2=0, IN3=1 and IN4=0, thereby realize in prior art in the time that single-chip microcomputer occurs to reset, can control output signal by Piezoelectric Driving amplification circuit, make valve position remain on current position.
From above technological scheme, the piezo electric valve drive amplification circuit that the embodiment of the present application provides, comprise two the first logical circuits and two the second logical circuits, by a logic inverter is set respectively in each the first logical circuit, make when input signal is respectively by after two the second logical circuits, output signal is identical with input signal.But when input signal is respectively by after two the first logical circuits, output signal is contrary with input signal, thereby realize in prior art in the time of single-chip microcomputer generation reset, can control output signal.
Embodiment two
A kind of piezo electric valve drive amplification circuit diagram that Fig. 2 provides for the embodiment of the present application two.
As shown in Figure 2, the piezo electric valve drive amplification circuit that the application provides comprises two the first logical circuits 1, two the second logical circuits 2 and switching circuits 3, wherein, two the first logical circuits 1 and two the second logical circuits 2 are identical with the structure of two the first logical circuits 1 in embodiment one and two the second logical circuits 2, do not repeat them here.
Switching circuit comprises the 3rd metal-oxide-semiconductor M3, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5.
In the embodiment of the present application, the other end of the second resistance R 2 in first logical circuit is connected as common port with the other end of the second resistance R 2 in second logical circuit, and the drain electrode of the 3rd metal-oxide-semiconductor M3 is connected with this common port.
The drain electrode of the 3rd metal-oxide-semiconductor M3 is also connected with the first reference voltage end by the 3rd resistance R 3; The source electrode of the 3rd metal-oxide-semiconductor M3 is connected with grounding end; The grid of the 3rd metal-oxide-semiconductor M3 is connected with the second reference voltage end by the 4th resistance R 4.In the embodiment of the present application, the voltage of the second reference voltage end can be 3V; The grid of the 3rd metal-oxide-semiconductor is also connected with reference signal input end by the 5th resistance R 5.
Can control the "on" position of two the first logical circuits 1 and two the second logical circuits 2 by switching circuit 3, in the time that the voltage of the reference signal input end input of switching circuit 3 is high level, two the first logical circuits 1 and two the second logical circuits 2 are no electric circuit state; In the time that the voltage of the reference signal input end input of switching circuit 3 is low level, two the first logical circuits 1 and two the second logical circuits 2 are "on" position.
As shown in Figure 2, the embodiment of the present application provides two the first logical circuits 1 and two the second logical circuits 2 can also comprise diode D.
Wherein, between the grid of the second metal-oxide-semiconductor M2 of each the second logical circuit 2 and the signal input part of the second logical circuit, be all in series with a diode D, the negative electrode of this diode D is connected with the grid of the second metal-oxide-semiconductor, and the anode of this diode D is connected with signal input part.
A diode D also all can be set between the drain electrode of the first metal-oxide-semiconductor M1 of two the first logical circuits 1 and two the second logical circuits 2 and the first reference voltage, the negative electrode of this diode D is connected with the drain electrode of the first metal-oxide-semiconductor M1, and the anode of this diode D is connected with the first reference voltage end.
As can be seen here, the piezo electric valve drive amplification circuit that the embodiment of the present application provides also comprises switching circuit, can directly control two the first logical circuits in piezo electric valve drive amplification circuit and the "on" position of two the second logical circuits by switching circuit, thereby control two the first logical circuits and whether two the second logical circuits can work, make the embodiment of the present application provide piezo electric valve drive amplification circuit to be more prone to control.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually referring to, what each embodiment stressed is and other embodiments' difference.
Below be only the application's preferred implementation, make those skilled in the art can understand or realize the application.To be apparent to one skilled in the art to these embodiments' multiple amendment, General Principle as defined herein can, in the case of not departing from the application's spirit or scope, realize in other embodiments.Therefore, the application will can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty
Claims (3)
1. a piezo electric valve drive amplification circuit, is characterized in that, comprising: two the first logical circuits and two the second logical circuits, wherein,
Described the first logical circuit and described the second logical circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance, the second resistance, inductance and reference diode, wherein:
The drain electrode of described the first metal-oxide-semiconductor is connected with the first reference voltage end; The source electrode of described the first metal-oxide-semiconductor is connected with one end of described inductance, and the other end of described inductance is connected with signal output part; The grid of described the first metal-oxide-semiconductor is connected with described the first reference voltage end by described the first resistance;
The drain electrode of described the second metal-oxide-semiconductor is connected with the grid of described the first metal-oxide-semiconductor; The source electrode of described the second metal-oxide-semiconductor is connected with grounding end; The grid of described the second metal-oxide-semiconductor is connected with signal input part;
The negative electrode of described reference diode is connected with the grid of described the first metal-oxide-semiconductor, and the anode of described reference diode is connected with the source electrode of described the first metal-oxide-semiconductor;
One end of described the second resistance is connected with the grid of described the second metal-oxide-semiconductor, and the other end is connected with described grounding end;
In each described the first logical circuit, be provided with a logic inverter; In described first logical circuit, described logic inverter is connected in described the first logical circuit between the grid of the second metal-oxide-semiconductor and the signal input part of described the first logical circuit, and the output terminal of described logic inverter is connected with the grid of the second metal-oxide-semiconductor in described the first logical circuit, and the input end of described logic inverter is connected with the signal input part of described the first logical circuit.
2. circuit according to claim 1, is characterized in that, in each described the second logical circuit, is provided with diode;
Described diode is connected in described the second logical circuit between the grid of the second metal-oxide-semiconductor and the signal input part of described the second logical circuit, and the negative electrode of described diode is connected with the grid of described the second metal-oxide-semiconductor, the anode of described diode is connected with the signal input part of described the second logical circuit.
3. circuit according to claim 2, it is characterized in that, in first logical circuit, the other end of the second resistance is connected as common port with the other end of the second resistance in second logical circuit, described circuit also comprises switching circuit, described switching circuit comprises the 3rd metal-oxide-semiconductor, the 3rd resistance, the 4th resistance and the 5th resistance, wherein
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described common port;
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described the first reference voltage end by described the 3rd resistance;
The source electrode of described the 3rd metal-oxide-semiconductor is connected with described grounding end;
The grid of described the 3rd metal-oxide-semiconductor is connected with the second reference voltage end by described the 4th resistance;
The grid of described the 3rd metal-oxide-semiconductor is connected with reference signal input end by described the 5th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574518.7A CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574518.7A CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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| CN103016818A CN103016818A (en) | 2013-04-03 |
| CN103016818B true CN103016818B (en) | 2014-10-15 |
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| CN201210574518.7A Active CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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| CN111140688B (en) * | 2019-08-09 | 2021-12-28 | 浙江中控技术股份有限公司 | Piezoelectric valve control circuit and control method |
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| US7741827B2 (en) * | 2007-05-01 | 2010-06-22 | Semiconductor Components Industries, Llc | Parameter control circuit including charging and discharging current mirrors and method therefor |
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| CN1881763A (en) * | 2005-06-17 | 2006-12-20 | 威盛电子股份有限公司 | Pulse frequency mode dc-dc converter circuit |
| CN201521699U (en) * | 2009-06-18 | 2010-07-07 | 深圳万讯自控股份有限公司 | Valve locator with lightening protection function |
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