CN113526287B - Electronic safety control module of elevator device - Google Patents
Electronic safety control module of elevator device Download PDFInfo
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- CN113526287B CN113526287B CN202110894557.4A CN202110894557A CN113526287B CN 113526287 B CN113526287 B CN 113526287B CN 202110894557 A CN202110894557 A CN 202110894557A CN 113526287 B CN113526287 B CN 113526287B
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- 238000005299 abrasion Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B66—HOISTING; LIFTING; HAULING
- B66B—ELEVATORS; ESCALATORS OR MOVING WALKWAYS
- B66B5/00—Applications of checking, fault-correcting, or safety devices in elevators
- B66B5/0043—Devices enhancing safety during maintenance
- B66B5/005—Safety of maintenance personnel
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- Electronic Switches (AREA)
- Elevator Control (AREA)
Abstract
The application provides an electronic safety control module of an elevator device, which is characterized in that: a signal input circuit having a channel signal input for accessing a channel signal of an elevator apparatus; a control output circuit having at least one set of controllably opened or closed switch contacts; and the logic processing circuit is connected between the signal input circuit and the control output circuit and is used for outputting an effective level to the control output circuit when the channel signals are activated simultaneously so as to enable the switch to be contacted. The application realizes switching of the safety circuit through the self-interlocking logic, avoids the influence of mechanical stress and the abrasion of mechanical movable contacts in the traditional relay scheme, has more stable operation and longer service life, reduces the production cost and the size of the safety module, and has little limitation on the operation environment.
Description
Technical Field
The invention belongs to the technical field of elevators, and particularly relates to an electronic safety control module of an elevator device.
Background
Safety modules (also known as "safety relay units") are widely used in machinery and elevator applications to switch safety circuits to protect personnel from the hazards of operating machinery (e.g., rotating or moving tools) during elevator service and to allow the elevator car to move with the doors open. The most advanced safety module solution at present uses forced guidance relay contacts to compare two-channel input signals to ensure safe operation of the monitored system, but the disadvantages of this solution are also obvious: first, two-channel inputs require at least three forced guidance relays, which are typically very expensive to market due to manufacturer construction and documentation work; secondly, the relays are electromechanical elements, and attention is paid to preventing the electromechanical elements from being influenced by mechanical stress such as impact or vibration; third, relays have worn mechanical moving contacts, and the service life is greatly limited.
Disclosure of Invention
The invention provides an electronic safety control module of an elevator device, which realizes safety self-locking control without mechanical contact and is realized by adopting the following technical means:
an electronic safety control module of an elevator device, comprising:
A signal input circuit having a channel signal input for accessing a channel signal of an elevator apparatus;
A control output circuit having at least one set of controllably opened or closed switch contacts;
and the logic processing circuit is connected between the signal input circuit and the control output circuit and is used for outputting an effective level to the control output circuit when the channel signals are activated simultaneously so as to enable the switch to be contacted.
In one or more embodiments of the present invention, the logic processing circuit includes a plurality of logic branches, and a combining circuit connected to the output end of each logic branch, where the output end of the combining circuit is connected to the output end of the logic processing circuit.
In one or more embodiments of the present invention, the logic branch includes an exclusive-or logic circuit and an RS flip-flop connected.
In one or more embodiments of the present invention, a first delay module is provided between the exclusive OR logic circuit and the RS flip-flop.
In one or more embodiments of the present invention, the exclusive OR circuit includes
One input end of the first NAND gate is connected with a first channel signal, and the other input end of the first NAND gate is connected with a second channel signal;
one input end of the second NAND gate is connected with the first channel signal, and the other input end of the second NAND gate is connected with the output end of the first NAND gate;
One input end of the third NAND gate is connected with the second channel signal, and the other input end of the third NAND gate is connected with the output end of the first NAND gate;
And the two input ends of the fourth NAND gate are respectively connected with the output ends of the second NAND gate and the third NAND gate.
In one or more embodiments of the present invention, the RS trigger includes
The two input ends of the fifth NAND gate are commonly connected to the output end of the fourth NAND gate;
a sixth NAND gate, one input end of which is connected to the output end of the fifth NAND gate;
and one input end of the seventh NAND gate is connected with the output end of the sixth NAND gate, the other input end of the seventh NAND gate is connected with the +V end, and the output end of the seventh NAND gate is connected with one input end of the sixth NAND gate.
In one or more embodiments of the present invention, a second delay module is disposed between the input terminal and the +v terminal of the seventh nand gate.
In one or more embodiments of the present invention, an output terminal of the RS flip-flop is connected to an eighth nand gate, which is used for inverting the output value of the RS flip-flop.
In one or more embodiments of the present invention, the output end of the logic processing circuit is connected to a status output circuit, which is used for connecting to a host computer to output a status signal of the electronic security control module thereto.
In one or more embodiments of the present invention, the signal input circuit has a feedback terminal connected to an output terminal of the logic processing circuit, and generates an internal signal output to the logic processing circuit in response to a feedback signal received by the feedback terminal, thereby implementing interlocking of the control output circuit.
The beneficial effects of the invention are as follows: the switching safety circuit is realized through the self-interlocking logic, and due to the adopted logic device without mechanical contact, the mechanical stress influence and mechanical moving contact abrasion existing in the traditional relay combination scheme are avoided, the operation is more stable, the service life is longer, the production cost and the size of the safety module are reduced, the limit on the operation environment is small, and the self-interlocking logic switching safety circuit is a better alternative scheme of the traditional mechanical safety module and has higher economical efficiency, technical performance and practicability.
Drawings
Fig. 1 is a schematic circuit diagram of an embodiment of the present application.
Fig. 2 is an equivalent circuit schematic diagram of a logic processing circuit according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a signal input circuit according to an embodiment of the application.
Fig. 4 is a signal waveform diagram of an embodiment of the present application.
Detailed Description
The scheme of the application is further described with reference to the accompanying drawings:
Referring to fig. 1 to 3, the electronic safety control module of the elevator apparatus of the present embodiment includes a signal input circuit 1, a control output circuit 2, a logic processing circuit 3, a status output circuit 4, and a power supply circuit 5, the signal input circuit 1 having Channel signal input terminals channel_a and channel_b for accessing the Channel signal of the elevator apparatus; the control output circuit 2 has a set of switch contacts C which are controllably turned on or off; the logic processing circuit 3 is connected between the signal input circuit 1 and the control output circuit 2 and is used for outputting an effective level to the control output circuit 2 when all channel signals are activated simultaneously so as to enable the switch contact C to be connected; the state output circuit 4 is connected to the output end of the logic processing circuit 3, and is used for connecting an upper computer to output a state signal FB of the electronic safety control module to the upper computer, wherein the state signal FB is synchronous with the output level of the logic processing circuit 3.
Specifically, the logic processing circuit 3 includes logic branches CH1 and CH2, and a combining circuit 6 connected to the output ends of the logic branches CH1 and CH2, where the input ends of the logic branches CH1 and CH2 are connected to the signal input circuit 1 to obtain the first channel signal a and the second channel signal B, respectively, and the output end of the combining circuit 6 is connected to the output end of the logic processing circuit 3. The logic branch CH1 and the logic branch CH2 have the same circuit structure and respectively comprise an exclusive-or logic circuit and an RS trigger which are connected, and a first delay module 31 is arranged between the exclusive-or logic circuit and the RS trigger. The signal input circuit 1 has a feedback terminal connected to the output terminal of the logic processing circuit 3, which is responsive to a feedback signal G received by the feedback terminal to generate an internal signal output to the logic processing circuit 3, thereby effecting interlocking of the control output circuit 2.
The exclusive OR logic circuit comprises a first NAND gate 3-1, a second NAND gate 3-2, a third NAND gate 3-3 and a fourth NAND gate 3-4, wherein one input end of the first NAND gate 3-1 is connected with a first channel signal A, and the other input end of the first NAND gate is connected with a second channel signal B; one input end of the second NAND gate 3-2 is connected with a first channel signal A, and the other input end of the second NAND gate is connected with the output end of the first NAND gate 3-1; one input end of the third NAND gate 3-3 is connected with a second channel signal B, and the other input end of the third NAND gate is connected with the output end of the first NAND gate 3-1; two input ends of the fourth NAND gate 3-4 are respectively connected with the output ends of the second NAND gate 3-2 and the third NAND gate 3-3.
The RS trigger comprises a fifth NAND gate 3-5, a sixth NAND gate 3-6 and a seventh NAND gate 3-7, wherein two input ends of the fifth NAND gate 3-5 are commonly connected to the output end of the fourth NAND gate 3-4; one input end of the sixth NAND gate 3-6 is connected to the output end of the fifth NAND gate 3-5; one input end of the seventh NAND gate 3-7 is connected with the output end of the sixth NAND gate 3-6, the other input end of the seventh NAND gate is connected with the +V end, and the output end of the seventh NAND gate is connected with one input end of the sixth NAND gate 3-6; the output end of the sixth NAND gate 3-6 is connected with the input end of an eighth NAND gate 3-8, and the eighth NAND gate 3-8 is used for inverting the output value of the RS trigger; a second delay module 32 is arranged between the input end and the +v end of the seventh nand gate 3-7.
The exclusive OR logic circuit is uniformly formed by NAND gate devices and is used for overcoming the time sequence problem or solving the problem in the follow-up authentication process caused by using different types of logic device forming circuits. While the fifth nand gate 3-5, the sixth nand gate 3-6 and the seventh nand gate 3-7 are one form of forming an RS flip-flop, whether the positive output or the negative output of the RS flip-flop is used depends only on the logic definition of the combining circuit 6, and the negative output is adopted in the present embodiment regardless of the operation principle of the RS flip-flop. The first delay module 31 is configured to set a duration of the allowable timing tolerance between the first channel signal a and the second channel signal B by affecting the response of the feedback signal G, and the second delay module 32 is configured to keep the output signal of the eighth nand gate 3-8 in a safe state until the internal power supply is stable.
The signal input circuit 1 comprises optocoupler units U1 and U2, triodes Q1 and Q2; the input side of the optocoupler unit U1 is connected with a Channel signal input end channel_A, the output side of the optocoupler unit U1 is connected with the base electrode of the triode Q1 through a resistor R31, the input side of the optocoupler unit U2 is connected with a Channel signal input end channel_B, the output side of the optocoupler unit U2 is connected with the base electrode of the triode Q2 through a resistor R30, the base electrodes of the triodes Q1 and Q2 are connected through resistors R24 and R25, the emitters of the triodes Q1 and Q2 are commonly connected to a feedback end for obtaining a feedback signal G, and the collectors of the triodes Q1 and Q2 output a first Channel signal A and a second Channel signal B respectively; the connection point of the resistors R24 and R25 is connected to the feedback end; the first channel signal a and the second channel signal B are set by influencing the response of the feedback signal G.
The control output circuit 2 adopts an optocoupler isolation device, the input side of the optocoupler isolation device is connected to the output end of the logic processing circuit 3, and the output side of the optocoupler isolation device is connected to the switch contact C. The implementation manner of the control output circuit 2 is not limited to adopting an optocoupler isolation device, and can also be realized by adopting modes of an electromagnetic relay, a MOS tube circuit and the like, and the on-off of the switch contact C is realized according to the output signal of the logic processing circuit 3, which is not described in detail herein.
Working principle:
Referring to fig. 4, the switch contact C is turned on only when the first channel signal a and the second channel signal B are simultaneously activated (simultaneously transitions from low to high), where the simultaneous activation may have a certain timing tolerance range; while switch contact C remains open when either of the first channel signal a and the second channel signal B is deactivated or reactivated (from low back to high). That is, when the outputs of both logic branches CH1 and CH2 are simultaneously activated by the signal input circuit 1 within a certain timing tolerance, the output of the combining circuit 6 will also be activated. Otherwise, the combining circuit 6 will interlock the logic branches CH1 and CH2 by outputting the feedback signal G (i.e. a low level signal) to the signal input circuit 1, which in turn interlocks the control output circuit 2 to open the switch contact C. Since the output of the logic processing circuit 3 will be inactive when the first channel signal a and the second channel signal B are not equal, the output of the logic processing circuit 3 can be used as an element of the detection judgment input being unequal. Once the logic processing circuit 3 enters the inactive state, it can be reset to the active state only if the initial conditions are met (the first channel signal a and the second channel signal B are in the inactive state and switch to the active state within the specified timing requirements, e.g. a power reset), eliminating the interlocking of the logic branches CH1 and CH 2.
The above-mentioned preferred embodiments should be regarded as illustrative examples of embodiments of the present application, and all such technical deductions, substitutions, improvements made on the basis of the same, similar or similar embodiments of the present application should be regarded as the protection scope of the present patent.
Claims (6)
1. An electronic safety control module of an elevator apparatus, comprising: a signal input circuit having a channel signal input for accessing a channel signal of an elevator apparatus; a control output circuit having at least one set of controllably opened or closed switch contacts; the logic processing circuit is connected between the signal input circuit and the control output circuit and is used for outputting an effective level to the control output circuit when all channel signals are activated simultaneously so as to enable the switch to be contacted;
the logic processing circuit comprises a plurality of logic branches and a merging circuit which is respectively connected with the output ends of the logic branches, and the output ends of the merging circuit are connected to the output ends of the logic processing circuit;
the logic branch circuit comprises an exclusive OR logic circuit and an RS trigger which are connected;
a first delay module is arranged between the exclusive OR logic circuit and the RS trigger;
The exclusive OR logic circuit comprises a first NAND gate, wherein one input end of the first NAND gate is connected with a first channel signal, and the other input end of the first NAND gate is connected with a second channel signal; one input end of the second NAND gate is connected with the first channel signal, and the other input end of the second NAND gate is connected with the output end of the first NAND gate; one input end of the third NAND gate is connected with the second channel signal, and the other input end of the third NAND gate is connected with the output end of the first NAND gate; and the two input ends of the fourth NAND gate are respectively connected with the output ends of the second NAND gate and the third NAND gate.
2. The electronic safety control module of an elevator apparatus of claim 1, wherein: the RS trigger comprises a fifth NAND gate, and two input ends of the fifth NAND gate are commonly connected to the output end of the fourth NAND gate; a sixth NAND gate, one input end of which is connected to the output end of the fifth NAND gate; and one input end of the seventh NAND gate is connected with the output end of the sixth NAND gate, the other input end of the seventh NAND gate is connected with the +V end, and the output end of the seventh NAND gate is connected with one input end of the sixth NAND gate.
3. The electronic safety control module of an elevator apparatus according to claim 2, characterized in that: and a second delay module is arranged between the input end and the +V end of the seventh NAND gate.
4. The electronic safety control module of an elevator apparatus of claim 1, wherein: and the output end of the RS trigger is connected with an eighth NAND gate which is used for inverting the output value of the RS trigger.
5. The electronic safety control module of an elevator apparatus according to any one of claims 1-4, characterized in that: the output end of the logic processing circuit is connected with a state output circuit which is used for being connected with an upper computer to output a state signal of the electronic safety control module to the upper computer.
6. The electronic safety control module of an elevator apparatus according to any one of claims 1-4, characterized in that: the signal input circuit has a feedback terminal connected to the output terminal of the logic processing circuit, and is responsive to a feedback signal received by the feedback terminal to generate an internal signal output to the logic processing circuit, thereby implementing an interlock to the control output circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110894557.4A CN113526287B (en) | 2021-08-05 | 2021-08-05 | Electronic safety control module of elevator device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110894557.4A CN113526287B (en) | 2021-08-05 | 2021-08-05 | Electronic safety control module of elevator device |
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| CN113526287B true CN113526287B (en) | 2024-07-23 |
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| CN215710891U (en) * | 2021-08-05 | 2022-02-01 | 广东卓梅尼技术股份有限公司 | Electronic safety control module of elevator device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2464697Y (en) * | 2000-04-11 | 2001-12-12 | 王达兴 | Elevator safety check controller |
| DE10119051B4 (en) * | 2001-04-18 | 2006-12-28 | Infineon Technologies Ag | Circuit arrangement for enabling a clock signal in response to an enable signal |
| JP3802377B2 (en) * | 2001-07-27 | 2006-07-26 | Ｎｅｃエレクトロニクス株式会社 | Flip-flop and scan path circuit |
| US6924682B1 (en) * | 2003-10-10 | 2005-08-02 | Advanced Micro Devices, Inc. | Latch circuit with metastability trap and method therefor |
| KR20070012457A (en) * | 2006-11-06 | 2007-01-25 | 미쓰비시덴키 가부시키가이샤 | Elevator apparatus |
| CN104355195B (en) * | 2014-10-27 | 2017-06-16 | 广东卓梅尼技术股份有限公司 | Safe torque turn-off function circuit and elevator safety control system |
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| CN215710891U (en) * | 2021-08-05 | 2022-02-01 | 广东卓梅尼技术股份有限公司 | Electronic safety control module of elevator device |
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