CN103016818A - Piezoelectric valve drive amplifier circuit - Google Patents
Piezoelectric valve drive amplifier circuit Download PDFInfo
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- CN103016818A CN103016818A CN2012105745187A CN201210574518A CN103016818A CN 103016818 A CN103016818 A CN 103016818A CN 2012105745187 A CN2012105745187 A CN 2012105745187A CN 201210574518 A CN201210574518 A CN 201210574518A CN 103016818 A CN103016818 A CN 103016818A
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Abstract
The embodiment of the invention provides a piezoelectric valve drive amplifier circuit, which comprises two first logic circuits and two second logic circuits. By arranging a logic NOT gate in each first logic circuit, after an input signal passes through the two second logic circuits, output signals are the same with the input signal; and after the input signal passes through the two first logic circuits, the output signals are opposite to the input signal, so as to achieve the goal of controlling the output signals through the piezoelectric valve drive amplifier circuit when a single-chip microcomputer is reset in the prior art.
Description
Technical field
The application relates to the valve positioner technical field, particularly relates to a kind of piezo electric valve drive amplification circuit.
Background technique
Pneumatic control valve is one of widely used industrial process control instruments of enterprise such as oil, chemical industry, electric power, pharmacy, metallurgy.Pneumatic control valve forms after normally being debugged by pneumatic actuator and modulating valve connection, enter the pneumatic signal size of pneumatic actuator by control, the aperture of regulating and controlling valve, thereby the rate-of flow of production control device reaches predetermined value, wherein, the size of controlling the pneumatic signal that enters pneumatic actuator is mainly finished by electropneumatic valve positioner.Therefore, electropneumatic valve positioner plays conclusive effect in the control performance of whole modulating valve and on-the-spot function.
Electropneumatic valve positioner can be divided into electromagnetic type electropneumatic valve positioner and piezoelectricity type electropneumatic valve positioner in the prior art.Because the piezoelectricity type valve positioner adopts the high piezoceramic material of internal resistance, micro power consumption, more favourable when forming the intrinsic safe explosion-proof structure, therefore extensively favored.
In the prior art, mainly be by the piezo electric valve drive amplification circuit in the Single-chip Controlling piezoelectricity type electropneumatic valve positioner, thereby realize the aperture of the output control valve of voltage.But, (send out strong the interference) under special circumstances, may cause the situation of monolithic processor resetting.After the situation that monolithic processor resetting occurs, although can recover by WATCHDOG, but general piezoelectricity type electropneumatic valve positioner is after single-chip microcomputer resets, the Piezoelectric Driving amplification circuit of piezoelectricity type electropneumatic valve positioner will lose the control to output signal, thereby cause the uncontrolled situation of valve location, when this thing happens on some crucial station, also potential safety hazard may appear.
Summary of the invention
In view of this, the embodiment of the present application provides a kind of piezo electric valve drive amplification circuit, solving in the prior art when single-chip microcomputer resets, and the problem that can't control output signal.
To achieve these goals, the technological scheme that provides of the embodiment of the present application is as follows:
A kind of piezo electric valve drive amplification circuit comprises: two the first logical circuits and two the second logical circuits, wherein,
Described the first logical circuit and described the second logical circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance, the second resistance, inductance and reference diode, wherein:
The drain electrode of described the first metal-oxide-semiconductor is connected with the first reference voltage end; The source electrode of described the first metal-oxide-semiconductor is connected with an end of described inductance, and the other end of described inductance is connected with signal output part; The grid of described the first metal-oxide-semiconductor is connected with described the first reference voltage end by described the first resistance;
The drain electrode of described the second metal-oxide-semiconductor is connected with the grid of described the first metal-oxide-semiconductor; The source electrode of described the second metal-oxide-semiconductor is connected with grounding end; The grid of described the second metal-oxide-semiconductor is connected with signal input part;
The negative electrode of described reference diode is connected with the grid of described the first metal-oxide-semiconductor, and the anode of described reference diode is connected with the source electrode of described the first metal-oxide-semiconductor;
One end of described the second resistance is connected with the grid of described the second metal-oxide-semiconductor, and the other end is connected with described grounding end;
Be provided with a logic inverter in each described first logical circuit; In described first logical circuit, described logic inverter is connected between the signal input part of the grid of the second metal-oxide-semiconductor in described the first logical circuit and described the first logical circuit, and the output terminal of described logic inverter is connected with the grid of the second metal-oxide-semiconductor in described the first logical circuit, and the input end of described logic inverter is connected with the signal input part of described the first logical circuit.
Preferably, each described second logical circuit is provided with diode in all;
Described diode is connected between the signal input part of the grid of the second metal-oxide-semiconductor in described the second logical circuit and described the second logical circuit, and the negative electrode of described diode is connected with the grid of described the second metal-oxide-semiconductor, and the anode of described diode is connected with the signal input part of described the second logical circuit.
Preferably, in first logical circuit in the other end of the second resistance and second logical circuit the other end of the second resistance be connected as common port, described circuit also comprises switching circuit, described switching circuit comprises the 3rd metal-oxide-semiconductor, the 3rd resistance, the 4th resistance and the 5th resistance, wherein
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described common port;
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described the first reference voltage end by described the 3rd resistance;
The source electrode of described the 3rd metal-oxide-semiconductor is connected with described grounding end;
The grid of described the 3rd metal-oxide-semiconductor is connected with the second reference voltage end by described the 4th resistance;
The grid of described the 3rd metal-oxide-semiconductor is connected with the reference signal input end by described the 5th resistance.
By above technological scheme as seen, the piezo electric valve drive amplification circuit that the embodiment of the present application provides, comprise two the first logical circuits and two the second logical circuits, by a logic inverter is set in each first logical circuit respectively, so that after input signal was respectively by two the second logical circuits, output signal was identical with input signal.But, when input signal respectively by after two the first logical circuits, output signal is opposite with input signal, thus in the realization prior art when single-chip microcomputer resets, can control output signal.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present application or technological scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, the accompanying drawing that the following describes only is some embodiments that put down in writing among the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of piezo electric valve drive amplification circuit diagram that Fig. 1 provides for the embodiment of the present application one;
A kind of piezo electric valve drive amplification circuit diagram that Fig. 2 provides for the embodiment of the present application two.
Embodiment
In order to make those skilled in the art person understand better technological scheme among the application, below in conjunction with the accompanying drawing in the embodiment of the present application, technological scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiments.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment who obtains under the creative work prerequisite, all should belong to the scope of the application's protection.
Embodiment one
A kind of piezo electric valve drive amplification circuit diagram that Fig. 1 provides for the embodiment of the present application one.
As shown in Figure 1, this Piezoelectric Driving amplification circuit comprises: two the first logical circuits 1 and two the second logical circuits 2, wherein, be provided with the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first resistance R 1, the second resistance R 2, inductance L and reference diode ZD in two described the first logical circuits 1 and two described the second logical circuits 2, also be respectively arranged with a logic inverter X in each described first logical circuit 1.
The below introduces the annexation of each device in two the second logical circuits.
The drain electrode of the first metal-oxide-semiconductor M1 is connected with the first reference voltage end, and in the embodiment of the present application, the voltage of the first reference voltage end can be 24V.The source electrode of the first metal-oxide-semiconductor M1 is connected with an end of inductance L, and the other end of inductance L is connected with signal output part, and signal output part is mainly used in the output of logical circuit signal.The grid of the first metal-oxide-semiconductor M1 is connected with the first reference voltage end by the first resistance R 1.
The drain electrode of the second metal-oxide-semiconductor M2 is connected with the grid of the first metal-oxide-semiconductor M1, and the source electrode of the second metal-oxide-semiconductor M2 is connected with grounding end, and the grid of the second metal-oxide-semiconductor M2 is connected with signal input part, and signal input part is mainly used in the input of signal.
The negative electrode of reference diode ZD is connected with the grid of the first metal-oxide-semiconductor M1, and the anode of reference diode ZD is connected with the source electrode of the first metal-oxide-semiconductor M1.
One end of the second resistance R 2 is connected with the grid of the second metal-oxide-semiconductor M2, and the other end is connected with grounding end.
Each device in two the first logical circuits in two the second logical circuits that comprise above-mentioned introduction, also comprise respectively a logic inverter X.The annexation of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first resistance R 1, the second resistance R 2, inductance L and reference diode ZD in two the first logical circuits, see also the annexation of all parts in above-mentioned two the second logical circuits, repeat no more here.
Be provided with a logic inverter X in each first logical circuit, this logic inverter X is connected between the grid and signal input part of the second metal-oxide-semiconductor M2, and the input end of this logic inverter X is connected with signal input part, and the output terminal of logic inverter X is connected with the grid of the second metal-oxide-semiconductor.
In the embodiment of the present application, the arrangement mode of two the first logical circuits and two the second logical circuits can arrange arbitrarily.Two the first logical circuits that Fig. 1 is given and the arrangement mode of two the second logical circuits are a kind of optimal way, and the inventor can arrange arbitrarily according to the demand of oneself.
As shown in Figure 1, the piezo electric valve drive amplification circuit that provides when the embodiment of the present application, when single-chip microcomputer resets, the input signal of the signal input part of piezo electric valve drive amplification circuit is respectively IN1=0, IN2=0, IN3=0 and IN4=0, this input signal is respectively through after two the first logical circuits and the second logical circuit, the output signal of signal output part is IN1=1, IN2=0, IN3=1 and IN4=0, thereby in the realization prior art when single-chip microcomputer resets, can control output signal by the Piezoelectric Driving amplification circuit, so that valve position remains on current position.
By above technological scheme as seen, the piezo electric valve drive amplification circuit that the embodiment of the present application provides, comprise two the first logical circuits and two the second logical circuits, by a logic inverter is set in each first logical circuit respectively, so that after input signal was respectively by two the second logical circuits, output signal was identical with input signal.But, when input signal respectively by after two the first logical circuits, output signal is opposite with input signal, thus in the realization prior art when single-chip microcomputer resets, can control output signal.
Embodiment two
A kind of piezo electric valve drive amplification circuit diagram that Fig. 2 provides for the embodiment of the present application two.
As shown in Figure 2, the piezo electric valve drive amplification circuit that the application provides comprises two the first logical circuits 1, two the second logical circuits 2 and switching circuits 3, wherein, two the first logical circuits 1 among two the first logical circuits 1 and two the second logical circuits 2 and the embodiment one are identical with the structure of two the second logical circuits 2, do not repeat them here.
Switching circuit comprises the 3rd metal-oxide-semiconductor M3, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5.
In the embodiment of the present application, the other end of the second resistance R 2 in the other end of the second resistance R 2 in first logical circuit and second logical circuit is connected as common port, and the drain electrode of the 3rd metal-oxide-semiconductor M3 is connected with this common port.
The drain electrode of the 3rd metal-oxide-semiconductor M3 also is connected with the first reference voltage end by the 3rd resistance R 3; The source electrode of the 3rd metal-oxide-semiconductor M3 is connected with grounding end; The grid of the 3rd metal-oxide-semiconductor M3 is connected with the second reference voltage end by the 4th resistance R 4.In the embodiment of the present application, the voltage of the second reference voltage end can be 3V; The grid of the 3rd metal-oxide-semiconductor also is connected with the reference signal input end by the 5th resistance R 5.
Can control the "on" position of two the first logical circuits 1 and two the second logical circuits 2 by switching circuit 3, when the voltage of the reference signal input end of switching circuit 3 input was high level, two the first logical circuits 1 and two the second logical circuits 2 were the no electric circuit state; When the voltage of the reference signal input end of switching circuit 3 input was low level, two the first logical circuits 1 and two the second logical circuits 2 were "on" position.
As shown in Figure 2, two the first logical circuits 1 and two the second logical circuits 2 of providing of the embodiment of the present application can also comprise diode D.
Wherein, all be in series with a diode D between the grid of the second metal-oxide-semiconductor M2 of each the second logical circuit 2 and the signal input part of the second logical circuit, the negative electrode of this diode D is connected with the grid of the second metal-oxide-semiconductor, and the anode of this diode D is connected with signal input part.
A diode D also all can be set between the drain electrode of the first metal-oxide-semiconductor M1 of two the first logical circuits 1 and two the second logical circuits 2 and the first reference voltage, the negative electrode of this diode D is connected with the drain electrode of the first metal-oxide-semiconductor M1, and the anode of this diode D is connected with the first reference voltage end.
This shows, the piezo electric valve drive amplification circuit that the embodiment of the present application provides also comprises switching circuit, can directly control two the first logical circuits in the piezo electric valve drive amplification circuit and the "on" position of two the second logical circuits by switching circuit, thereby control two the first logical circuits and whether two the second logical circuits can work, so that the embodiment of the present application provides piezo electric valve drive amplification circuit to be more prone to control.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and identical similar part is mutually referring to getting final product between each embodiment, and each embodiment stresses is difference with other embodiments.
Only be the application's preferred implementation below, make those skilled in the art can understand or realize the application.Multiple modification to these embodiments will be apparent to one skilled in the art, and General Principle as defined herein can in the situation of the spirit or scope that do not break away from the application, realize in other embodiments.Therefore, the application will can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty
Claims (3)
1. a piezo electric valve drive amplification circuit is characterized in that, comprising: two the first logical circuits and two the second logical circuits, wherein,
Described the first logical circuit and described the second logical circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance, the second resistance, inductance and reference diode, wherein:
The drain electrode of described the first metal-oxide-semiconductor is connected with the first reference voltage end; The source electrode of described the first metal-oxide-semiconductor is connected with an end of described inductance, and the other end of described inductance is connected with signal output part; The grid of described the first metal-oxide-semiconductor is connected with described the first reference voltage end by described the first resistance;
The drain electrode of described the second metal-oxide-semiconductor is connected with the grid of described the first metal-oxide-semiconductor; The source electrode of described the second metal-oxide-semiconductor is connected with grounding end; The grid of described the second metal-oxide-semiconductor is connected with signal input part;
The negative electrode of described reference diode is connected with the grid of described the first metal-oxide-semiconductor, and the anode of described reference diode is connected with the source electrode of described the first metal-oxide-semiconductor;
One end of described the second resistance is connected with the grid of described the second metal-oxide-semiconductor, and the other end is connected with described grounding end;
Be provided with a logic inverter in each described first logical circuit; In described first logical circuit, described logic inverter is connected between the signal input part of the grid of the second metal-oxide-semiconductor in described the first logical circuit and described the first logical circuit, and the output terminal of described logic inverter is connected with the grid of the second metal-oxide-semiconductor in described the first logical circuit, and the input end of described logic inverter is connected with the signal input part of described the first logical circuit.
2. circuit according to claim 1 is characterized in that, is provided with diode in each described second logical circuit;
Described diode is connected between the signal input part of the grid of the second metal-oxide-semiconductor in described the second logical circuit and described the second logical circuit, and the negative electrode of described diode is connected with the grid of described the second metal-oxide-semiconductor, and the anode of described diode is connected with the signal input part of described the second logical circuit.
3. circuit according to claim 2, it is characterized in that, in first logical circuit in the other end of the second resistance and second logical circuit the other end of the second resistance be connected as common port, described circuit also comprises switching circuit, described switching circuit comprises the 3rd metal-oxide-semiconductor, the 3rd resistance, the 4th resistance and the 5th resistance, wherein
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described common port;
The drain electrode of described the 3rd metal-oxide-semiconductor is connected with described the first reference voltage end by described the 3rd resistance;
The source electrode of described the 3rd metal-oxide-semiconductor is connected with described grounding end;
The grid of described the 3rd metal-oxide-semiconductor is connected with the second reference voltage end by described the 4th resistance;
The grid of described the 3rd metal-oxide-semiconductor is connected with the reference signal input end by described the 5th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574518.7A CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574518.7A CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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| CN103016818A true CN103016818A (en) | 2013-04-03 |
| CN103016818B CN103016818B (en) | 2014-10-15 |
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| CN201210574518.7A Active CN103016818B (en) | 2012-12-26 | 2012-12-26 | Piezoelectric valve drive amplifier circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111140688A (en) * | 2019-08-09 | 2020-05-12 | 浙江中控技术股份有限公司 | Piezoelectric valve control circuit and control method |
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2012
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| CN1881763A (en) * | 2005-06-17 | 2006-12-20 | 威盛电子股份有限公司 | Pulse frequency mode dc-dc converter circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111140688A (en) * | 2019-08-09 | 2020-05-12 | 浙江中控技术股份有限公司 | Piezoelectric valve control circuit and control method |
| CN111140688B (en) * | 2019-08-09 | 2021-12-28 | 浙江中控技术股份有限公司 | Piezoelectric valve control circuit and control method |
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| CN103016818B (en) | 2014-10-15 |
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