CN103001736A - CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and implementing method thereof - Google Patents
CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and implementing method thereof Download PDFInfo
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Abstract
The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of RS coded system and its implementation based on CMMB.
Background technology
At present, RS encoder of the prior art is to use combinational logic to realize, and requires to use high-end FPGA.Because when using pure combinational logic circuit, the RS coding needs a large amount of combinational logic designs, and FPGA is higher to the requirement of sequential, and a large amount of combinational logic circuits can cause sequence problem, particularly in the complex environment.High-end FPGA can be alleviated the sequence problem that a large amount of combinational logics bring, but also can therefore be restricted when processing clock.Because if employing sequence circuit, the code rate that the RS that obtains from theory analysis encodes is 3 times of data rate, that is to say, if data rate is 60M-100M, code rate will be near 300M so, and this is difficult to FPGA, can only reduce processing clock, both affected efficient, still multi-clock is processed simultaneously.
Summary of the invention
The purpose of this invention is to provide a kind of can be under unified clock be processed, the RS coded system based on CMMB that adopts sequential logic to realize.
Another object of the present invention provide a kind of can be under unified clock be processed, the RS coding implementation method based on CMMB that adopts sequential logic to realize.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:
A kind of RS coded system based on CMMB comprises following part:
Sdram controller is used for receiving information code current, and the check code that enters is stored;
Byte interleaver device is used for information code and the check code that enters carried out byte-interleaved;
Internal storage is used for information code and the check code that enters carried out buffer memory;
The RS encoder is for processing that information code is encoded;
Described sdram controller is connected with byte interleaver device, internal storage and RS encoder successively.
As the further improvement of described a kind of RS coded system based on CMMB, described RS encoder comprises:
Reader is used for information code of per three Clockreadings;
Maker is used for generating a check code by three clock units;
Described internal storage is connected with reader, maker successively.
As the further improvement of described a kind of RS coded system based on CMMB, described maker also comprises:
Arithmetic unit is used for that the value of information code word and last register of coding circuit is carried out mould two and adds computing; The result that mould two adds computing multiplies each other with the coefficient that RS encodes respectively; The result of the result who multiplies each other and upper level register carries out mould two and adds computing;
Shift unit is used for all registers of coding circuit are shifted, and to the last the value of a register shifts out register, has just generated check code;
Described maker is connected with arithmetic unit, shift unit successively.
Another technical scheme of the present invention is:
A kind of RS coding implementation method based on CMMB may further comprise the steps:
A, sdram controller receive information code current;
B, information code enter byte interleaver device and carry out byte-interleaved;
C, the information code after will interweaving are stored in the internal storage;
D, reading information code also encode to it;
E, the check code that obtains is stored in the internal storage;
F, read check code and enter byte interleaver device and carry out byte-interleaved;
G, the check code after interweaving enter sdram controller and store.
As the further improvement of described a kind of RS coding implementation method based on CMMB, described step D comprises:
D1, information code of per three Clockreadings;
D2, generate a check code by three clock units.
As the further improvement of described a kind of RS coding implementation method based on CMMB, described step D2 comprises:
S1, information code word enter coding circuit;
The value of S2, information code word and last register of coding circuit is carried out mould two and is added computing;
The result that S3, mould two add computing multiplies each other with the coefficient that RS encodes respectively;
The result of S4, the result who multiplies each other and upper level register carries out mould two and adds computing;
All registers are shifted in S5, the coding circuit, and to the last the value of a register shifts out register, have just generated check code.
The invention has the beneficial effects as follows:
A kind of RS coded system based on CMMB of the present invention receives information code current by sdram controller, byte interleaver device, internal storage and RS encoder, and the check code that enters stored, information code and the check code that enters carried out byte-interleaved, information code and the check code that enters carried out buffer memory, to the information code processing of encoding, effectively save the FPGA internal resource and reduce its operand, so that in the sequence problem that has solved FPGA, can also use the FPGA of low side to design, make native system under complex environment, also can work.
Another beneficial effect of the present invention is:
A kind of RS coding implementation method based on CMMB of the present invention, receive information code current by sdram controller, information code enters byte interleaver device and carries out byte-interleaved, information code after will interweaving is stored in the internal storage of FPGA, the reading information code is also encoded to it, the check code that obtains is stored in the internal storage, reading check code enters byte interleaver device and carries out byte-interleaved, check code after interweaving enters sdram controller and stores, solved the sequence problem of FPGA, the sequential that has guaranteed FPGA under complex environment is correct, and uses the FPGA of low side to design, and effectively saves the FPGA internal resource and reduces its operand.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described further:
Fig. 1 is the functional-block diagram of a kind of RS coded system based on CMMB of the present invention.
Fig. 2 is the functional-block diagram of the embodiment one of a kind of RS coded system based on CMMB of the present invention.
Fig. 3 is the functional-block diagram of the embodiment two of a kind of RS coded system based on CMMB of the present invention.
Fig. 4 is the flow chart of steps of a kind of RS coding implementation method based on CMMB of the present invention.
Fig. 5 is the flow chart of steps of a kind of RS coding implementation method step D embodiment one based on CMMB of the present invention.
Fig. 6 is the flow chart of steps of a kind of RS coding implementation method step D embodiment two based on CMMB of the present invention.
Fig. 7 is the RS coding circuit schematic diagram of a kind of RS coded system based on CMMB of the present invention.
Embodiment
Fig. 1 is the functional-block diagram of a kind of RS coded system based on CMMB of the present invention, comprising: sdram controller is used for receiving information code current; And the check code that enters stored; Byte interleaver device is used for information code and the check code that enters carried out byte-interleaved; Internal storage is used for information code and the check code that enters carried out buffer memory; The RS encoder is for processing that information code is encoded.Described sdram controller is connected with byte interleaver device, internal storage and RS encoder successively.
Fig. 2 is the functional-block diagram of the embodiment one of a kind of RS coded system based on CMMB of the present invention, and wherein said RS encoder comprises: reader is used for information code of per three Clockreadings; Maker is used for generating a check code by three clock units.Described internal storage is connected with reader, maker successively.
Fig. 3 is the functional-block diagram of the embodiment two of a kind of RS coded system based on CMMB of the present invention, and wherein said maker also comprises: arithmetic unit is used for that the value of information code word and last register of coding circuit is carried out mould two and adds computing; The result that mould two adds computing multiplies each other with the coefficient that RS encodes respectively; The result of the result who multiplies each other and upper level register carries out mould two and adds computing; Shift unit is used for all registers of coding circuit are shifted, and to the last the value of a register shifts out register, has just generated check code.Described maker is connected with arithmetic unit, shift unit successively.
Fig. 4 is the flow chart of steps of a kind of RS coding implementation method based on CMMB of the present invention, and in conjunction with Fig. 1, the present invention may further comprise the steps as the RS coding implementation method of a kind of CMMB:
A, sdram controller receive information code current;
B, the information code after interweaving enter byte interleaver device and carry out byte-interleaved;
C, information code is stored in the internal storage of FPGA;
D, reading information code also encode to it;
E, the check code that obtains is stored in the internal storage;
F, read check code and enter byte interleaver device and carry out byte-interleaved;
G, the check code after interweaving enter sdram controller and store.
Fig. 5 is the flow chart of steps of a kind of RS coding implementation method step D embodiment one based on CMMB of the present invention, and described step D comprises:
D1, information code of per three Clockreadings;
D2, generate a check code by three clock units.
Fig. 6 is the flow chart of steps of a kind of RS coding implementation method step D embodiment two based on CMMB of the present invention, and as the further improvement to embodiment one, described step D2 comprises:
S1, information code word enter coding circuit;
The value of S2, information code word and last register of coding circuit is carried out mould two and is added computing;
The result that S3, mould two add computing multiplies each other with the coefficient that RS encodes respectively;
The result of S4, the result who multiplies each other and upper level register carries out mould two and adds computing;
All registers are shifted in S5, the coding circuit, and to the last the value of a register shifts out register, have just generated check code.
Fig. 7 is the RS coding circuit schematic diagram of a kind of RS coded system based on CMMB of the present invention.As can be seen from Figure 7, the multiplier number in the coding circuit and coefficient will be decided according to the coding mode of RS, and RS coding mode one has four kinds in the CMMB system, and the number of the multiplication coefficient that different coding mode devices is corresponding and value are all different.Compatibility of the present invention the RS coding of four kinds of patterns, can change according to the pattern of correspondence its circuit-mode.And the multiplier in the coding circuit and common multiplier are different, and in the calculating process of RS coding, the computing that adds, subtracts, takes advantage of and remove is carried out in galois field, so need to the multiplier in the circuit be designed.
Further, to Galois field multiplying unit, two numbers that multiply each other in the RS coding are respectively information code word and multiplier coefficients, wherein multiplier coefficients is fixed, given according to different coding mode standard documents, these coefficients are directly multiplied each other with the information code word, and the result's who so multiplies each other unknown quantity only has the information code word, and just the mould two of corresponding of the information code word of eight bits adds computing.Although this method has increased the amount of program, be easily understood, use the logical resource of FPGA still less, further saved resource, reduced simultaneously the operand of FPGA.Example below is provided, and wherein multin is enter code word, and g0 is coefficient, g0=106, and the as a result rslt_g0 of information code word is as shown below.
//multin*g0 g0 = 106
rslt_g0[0]<=multin[2]^multin[3]^multin[5]^multin[6]^multin[7];
rslt_g0[1]<=multin[0]^multin[3]^multin[4]^multin[6]^multin[7];
rslt_g0[2]<=multin[1]^multin[2]^multin[3]^multin[4]^multin[6];
rslt_g0[3] <= multin[0]^multin[4]^multin[6];
rslt_g0[4] <= multin[1]^multin[2]^multin[3]^multin[6];
rslt_g0[5]<=multin[0]^multin[2]^multin[3]^multin[4]^multin[7];
rslt_g0[6]<=multin[0]^multin[1]^multin[3]^multin[4]^multin[5];
rslt_g0[7]<=multin[1]^multin[2]^multin[4]^multin[5]^multin[6];
It can be seen from the above:
The present invention a kind of RS coded system and its implementation based on CMMB, receive information code current by sdram controller, information code enters byte interleaver device and carries out byte-interleaved, information code after will interweaving is stored in the internal storage of FPGA, the reading information code is also encoded to it, the check code that obtains is stored in the internal storage, reading check code enters byte interleaver device and carries out byte-interleaved, check code after interweaving enters sdram controller and stores, solved the sequence problem of FPGA, the sequential that has guaranteed FPGA under complex environment is correct, and uses the FPGA of low side to design, and effectively saves the FPGA internal resource and reduces its operand.
More than be that better enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art make all equivalent variations or replacement also can doing under the prerequisite of spirit of the present invention, the distortion that these are equal to or replace all is included in the application's claim limited range.
Claims (6)
1. the RS coded system based on CMMB is characterized in that, comprises following part:
Sdram controller is used for receiving information code current, and the check code that enters is stored;
Byte interleaver device is used for information code and the check code that enters carried out byte-interleaved;
Internal storage is used for information code and the check code that enters carried out buffer memory;
The RS encoder is for processing that information code is encoded;
Described sdram controller is connected with byte interleaver device, internal storage and RS encoder successively.
2. a kind of RS coded system based on CMMB according to claim 1 is characterized in that described RS encoder comprises:
Reader is used for information code of per three Clockreadings;
Maker is used for generating a check code by three clock units;
Described internal storage is connected with reader, maker successively.
3. a kind of RS coded system based on CMMB according to claim 2 is characterized in that described maker comprises:
Arithmetic unit is used for that the value of information code word and last register of coding circuit is carried out mould two and adds computing, and the result that mould two adds computing multiplies each other with the coefficient that RS encodes respectively, and the result of the result who multiplies each other and upper level register carries out mould two and adds computing;
Shift unit is used for all registers of coding circuit are shifted, and to the last the value of a register shifts out register, has just generated check code;
Described maker is connected with arithmetic unit, shift unit successively.
4. the RS coding implementation method based on CMMB is characterized in that, may further comprise the steps:
A, sdram controller receive information code current;
B, information code enter byte interleaver device and carry out byte-interleaved;
C, the information code after will interweaving are stored in the internal storage;
D, reading information code also encode to it;
E, the check code that obtains is stored in the internal storage;
F, read check code and enter byte interleaver device and carry out byte-interleaved;
G, the check code after interweaving enter sdram controller and store.
5. a kind of RS coding implementation method based on CMMB according to claim 4 is characterized in that described step D comprises:
D1, information code of per three Clockreadings;
D2, generate a check code by three clock units.
6. a kind of RS coding implementation method based on CMMB according to claim 5 is characterized in that described step D2 comprises:
S1, information code word enter coding circuit;
The value of S2, information code word and last register of coding circuit is carried out mould two and is added computing;
The result that S3, mould two add computing multiplies each other with the coefficient that RS encodes respectively;
The result of S4, the result who multiplies each other and upper level register carries out mould two and adds computing;
All registers are shifted in S5, the coding circuit, and to the last the value of a register shifts out register, have just generated check code.
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| CN110380738A (en) * | 2019-07-19 | 2019-10-25 | 广东省新一代通信与网络创新研究院 | The configurable RS encoder IP core circuit structure of parametric software and its coding method |
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| CN101478315A (en) * | 2009-01-09 | 2009-07-08 | 航天恒星科技有限公司 | Byte interleaver device and interleaving method based on CMMB standard |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110380738A (en) * | 2019-07-19 | 2019-10-25 | 广东省新一代通信与网络创新研究院 | The configurable RS encoder IP core circuit structure of parametric software and its coding method |
| CN110380738B (en) * | 2019-07-19 | 2023-01-31 | 广东省新一代通信与网络创新研究院 | RS encoder IP core circuit structure with configurable parameter software and encoding method thereof |
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