CN103000548B - Method for detecting integrated circuit manufacturing process defects by using field programmable gate array (FPGA) chip - Google Patents
Method for detecting integrated circuit manufacturing process defects by using field programmable gate array (FPGA) chip Download PDFInfo
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- CN103000548B CN103000548B CN201210516210.7A CN201210516210A CN103000548B CN 103000548 B CN103000548 B CN 103000548B CN 201210516210 A CN201210516210 A CN 201210516210A CN 103000548 B CN103000548 B CN 103000548B
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Abstract
The invention relates to a method for detecting integrated circuit manufacturing process defects by using a field programmable gate array (FPGA) chip. The method includes the following steps of subjecting a configuration memory of the FPGA chip to back-read testing to obtain testing data of the configuration memory; detecting testing data to obtain coordinate information of a faulted configuration memory; accounting fault distribution maps of three levels of a submodule level, a chip level and a wafer level according to the fault coordinate information; respectively overlaying the fault distribution maps of the three levels to obtain fault point distribution densities; and subjecting distribution density uniformity to detecting to obtain accurate high occurrence areas and possible reasons of process defects. According to the method for detecting the integrated circuit manufacturing process defects by using the FPGA chip, by means of a unique design structure of the FPGA chip and a testing method, fault distribution density maps of a plurality of levels can be rapidly acquired, defect areas can be rapidly positioned, possible process factors can be fast pointed, and detection speeds of the process defects are increased.
Description
Technical field
The present invention relates to a kind of method of integrated circuit fabrication process defects detection, particularly a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection.
Background technology
Integrated circuit production line process abnormality is accurate and complicated, new technology needs to carry out a large amount of throwing sheet tests and checking research before formal volume production is enabled, by carrying out accurate defect location and mechanism detection to test disk, find systematic manufacturing process defect cause, set up suitable layout design rules system simultaneously, guarantee rate of finished products when formally producing.At present, widely used method utilizes sram chip to carry out defective workmanship to detect, and this is because sram cell is regularly arranged, has unique address information, conveniently carries out fault location, easily carries out the detection of defect mechanism.The very rule but the structure of sram chip and unit are arranged, can only react the defect situation with its similar structures, and user's design that production line is actual when coming into operation is Protean, and SRAM is difficult to cover more defect type.In addition, all right specialized designs DFT/DFM (design for Measurability/manufacturability design) chip, although this type chip can cover more defect situation, the chip design level that demand is very high, also can bring more complicated defect inspection process.Detect although method in the past also can realize defective workmanship, its detection speed is lower, and the defect type of covering is less than actual conditions, or needs Custom Design test chip, of a high price.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provides a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection, greatly accelerates location and the detection speed of defective workmanship, covers a greater variety of defect type.
Technical solution of the present invention is: a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection, comprises the steps:
(1) utilize the configuration bit stream of Four types vector to carry out retaking of a year or grade test to the config memory of fpga chip, obtain the test data of config memory;
(2) detect test data, obtain the coordinate information of the config memory broken down;
(3) according to fault coordinate information, the fault distribution map of submodule rank, chip level and disk rank three kinds of ranks is counted;
(4) the fault distribution map under three kinds of ranks is stacked respectively, obtain fault point distribution density;
(5) distribution density uniformity is detected, obtain defective workmanship region occurred frequently thus complete detection.
The configuration bit stream vector of Four types is respectively test full 0, tests complete 1, interval test 01 and interval test 10 in described step (1).
In described step (2), the coordinate information of config memory is the physical address information of config memory, comprises block address, main address, secondary address, frame address and bit address.
Submodule rank in described step (3) is programmable configuration module CLB, comprises the error number of each config memory in CLB module.
Chip level in described step (3) is complete fpga chip, comprises the error number of all CLB modules in fpga chip.
Disk rank in described step (3) is complete disk, comprises the error number of all fpga chips in disk.
Fault graph in described step (4) stacks and refers to and add up to number of faults, obtains total number of faults.
Implementation procedure in described step (5) is: fault distributing homogeneity refers to the number of faults mean value in unit are, number of faults mean value on unit of account area, when the number of faults in certain unit are exceedes 20% of mean value, be namely judged to be defective workmanship district occurred frequently.
The present invention's beneficial effect is compared with prior art:
(1) framework of field programmable gate array (FPGA) chip adopts the integral layout form based on array, although the programmable configuration determined bit position structure of FPGA is the same, but in modules, be all scattered distribution, the domain environment of each unit may be completely different, each configuration bit can control different logical resources, therefore can cover more defect situation.
(2) the present invention utilizes the project organization of fpga chip uniqueness, by carrying out retaking of a year or grade test to all programmable memory cell, can can carry out fast accurately location and test to all fault points to detect, obtain defect distribution density map, improve defective workmanship reason detection speed.
(3) the present invention utilizes actual FPGA product to carry out defects detection, throws built-in testing application-specific integrated circuit (ASIC), greatly provide cost savings without the need to specialized designs.
Accompanying drawing explanation
Fig. 1 is the basic structure schematic diagram of FPGA;
Fig. 2 is the structure composition schematic diagram of config memory;
Fig. 3 is the fault distribution schematic diagram of CLB rank.
Embodiment
The basic structure of FPGA as shown in Figure 1, its agent structure is by programmed logical module (CLB) 1, interconnect resource line segment 2 and programmable switch matrix (SM) 3 form, interconnect resource line segment 2 and programmable switch matrix 3 are around programmed logical module 1, form netted stacked structure, these modules are all combined by the config memory being in backstage and realize various function.And a fpga chip is according to scale, have hundreds thousand of config memory to hundreds of myriabit, all config memorys are all programmable, have well-determined physical address, can carry out write access and read access.
As shown in Figure 2, locked mutually by two inverters and realize data storage function, each unit has unique address to the structure of config memory, can realize addressing writing and reading by turn.And each unit may be linked into the user logic of FPGA from Q end or QB end extraction control signal, different cut-in methods is had, input of the Digital Logic such as the control end being such as connected to nmos pass transistor, the source and drain end being connected to nmos pass transistor, the input being connected to inverter or NAND gate etc. according to chip design situation.Connected modes different in a large number makes fpga chip more be similar to actual chip design situation, also can reflect more defect situation than standard sram chip.
The present invention mainly by carrying out retaking of a year or grade test to the config memory of FPGA, locates and counts fault distribution map, fast obtains defective locations information, and then provides data for next step defect cause detects.The present invention is described in more detail below, is primarily characterized in that and is divided into following 5 steps:
(1) retaking of a year or grade test is carried out to the config memory of fpga chip, obtain the test data of config memory.A complete config memory retaking of a year or grade test vector should comprise 4 kinds of configuration bit streams, i.e. all writes 0, all write 1, all intervals write 01 and all intervals writes 10, after four kinds of configuration bit streams are written to all config memorys of FPGA, recycling Jtag retaking of a year or grade function or Selectmap retaking of a year or grade function by the test value retaking of a year or grade of all config memorys out, are tested by namely completing retaking of a year or grade with the contrast carried out by turn of the retaking of a year or grade test vector of original write;
(2) detect test data, obtain the coordinate information of the config memory broken down.The back read data that test is preserved includes all fault messages, and the retaking of a year or grade test of whole 0 can be determined to fix 0 type fault; The retaking of a year or grade test of whole 1 can be determined to fix 1 type fault; The retaking of a year or grade test of whole 01 and whole 10 can be determined to close on write/read fault.Because the quantity of config memory configuration bit is according to the scale of FPGA, have hundreds thousand of even hundreds of myriabit, computer software therefore can be utilized to carry out the fault coordinate information statistics of fault position.Usually in SRAM type FPGA, all configuration bits have well-determined physical address, generally comprise block address, main address, secondary address, frame address and bit address etc., according to the fault message counted in step (2), be converted into the coordinate information by address statistics further, these coordinate informations can indicate the exact position of fault point on FPGA domain.
(3) according to fault coordinate information, the fault distribution map of submodule rank, chip level and disk rank three kinds of ranks is counted.The fault distribution map of submodule rank refers to, within the scope of single CLB, whether each config memory exists the information of fault, and there is failure identification is 1, and there is not failure identification is 0; The fault distribution map of chip level refers within the scope of one single chip, and the information of the number of faults of each CLB module identifies by physical fault quantity; Other fault distribution map of wafer level refers within the scope of single disk, and the information of the number of faults of each fpga chip, identifies by physical fault quantity.
(4) the fault distribution map under three kinds of ranks is stacked respectively, obtain fault point distribution density.When fault graph is stacked, errors number is added up, the fault sum of each config memory can be demonstrated like this on the fault density distribution map of submodule rank; The fault density distribution map of chip level can demonstrate the fault sum of each CLB submodule; Other fault distribution map of wafer level can demonstrate the fault sum of each fpga chip.
(5) distribution density uniformity is detected, obtain accurate defective workmanship region occurred frequently.According to the fault distribution density that step (4) obtains, the difference of different units defective workmanship probability of happening can be learnt, when the number of faults of certain unit exceedes 20% of mean value, defective workmanship district occurred frequently can be thought.In general the fault close quarters of submodule rank, represents in layout design rules and has inappropriate place, can determine specifically what rule is unreasonable by further detection and localization.And the fault distribution map of chip-scale, can be used for judging that the ratio of defects between dissimilar submodule is distinguished, usually represent systematic defective workmanship reason.And the fault distribution map of wafer level can reflect the defect that the reason of integrated circuit production line equipment self causes, and the disappearance in disk manufacturing process.
By fpga chip test and the Data Detection of above-mentioned 5 steps, the fault distribution density of three kinds of levels can be obtained fast, accurate positioning process defect region occurred frequently.And the fault distribution density of different stage points to different possible factors, indicate specific direction for further defective workmanship mechanism detects, greatly accelerate the detection speed of integrated circuit technology defect factors.
The non-detailed description of the present invention is known to the skilled person technology.
Claims (8)
1. utilize fpga chip to carry out a method for integrated circuit fabrication process defects detection, it is characterized in that comprising the steps:
(1) utilize the configuration bit stream of Four types vector to carry out retaking of a year or grade test to the config memory of fpga chip, obtain the test data of config memory;
(2) detect test data, obtain the coordinate information of the config memory broken down;
(3) according to fault coordinate information, the fault distribution map of submodule rank, chip level and disk rank three kinds of ranks is counted;
(4) the fault distribution map under three kinds of ranks is stacked respectively, obtain fault point distribution density;
(5) distribution density uniformity is detected, obtain defective workmanship region occurred frequently thus complete detection.
2. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, is characterized in that: the configuration bit stream vector of Four types is respectively test full 0, tests complete 1, interval test 01 and interval test 10 in described step (1).
3. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, it is characterized in that: in described step (2), the coordinate information of config memory is the physical address information of config memory, comprises block address, main address, secondary address, frame address and bit address.
4. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, it is characterized in that: the submodule rank in described step (3) is programmable configuration module CLB, comprises the error number of each config memory in CLB module.
5. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, it is characterized in that: the chip level in described step (3) is complete fpga chip, comprise the error number of all CLB modules in fpga chip.
6. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, is characterized in that: the disk rank in described step (3) is complete disk, comprises the error number of all fpga chips in disk.
7. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, it is characterized in that: " the fault distribution map under three kinds of ranks is stacked respectively " in described step (4) and refer to and the number of faults of the fault distribution map under often kind of rank is added up respectively, obtain number of faults total on each level faults distribution map.
8. a kind of method utilizing fpga chip to carry out integrated circuit fabrication process defects detection according to claim 1, it is characterized in that: the implementation procedure in described step (5) is: the number of faults mean value on unit of account area, when the number of faults in certain unit are exceedes 20% of mean value, be namely judged to be defective workmanship district occurred frequently.
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| US10191112B2 (en) * | 2016-11-18 | 2019-01-29 | Globalfoundries Inc. | Early development of a database of fail signatures for systematic defects in integrated circuit (IC) chips |
| CN107144776B (en) * | 2017-04-17 | 2019-10-08 | 深圳先进技术研究院 | A kind of detection method and device of total dose effect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5841790A (en) * | 1997-04-08 | 1998-11-24 | International Business Machines Corporation | Apparatus for testing an adapter card ASIC with reconfigurable logic |
| CN101029918A (en) * | 2007-01-23 | 2007-09-05 | 北京芯技佳易微电子科技有限公司 | System and method for testing controllable integrated circuit based on programmable device |
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| JPH04369242A (en) * | 1991-06-17 | 1992-12-22 | Kawasaki Steel Corp | Automatic circuit allocation apparatus for field programmable gate array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5841790A (en) * | 1997-04-08 | 1998-11-24 | International Business Machines Corporation | Apparatus for testing an adapter card ASIC with reconfigurable logic |
| CN101029918A (en) * | 2007-01-23 | 2007-09-05 | 北京芯技佳易微电子科技有限公司 | System and method for testing controllable integrated circuit based on programmable device |
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