CN103000227A - Method for carrying out failure model modeling upon non-volatile memory product - Google Patents
Method for carrying out failure model modeling upon non-volatile memory product Download PDFInfo
- Publication number
- CN103000227A CN103000227A CN2011102650405A CN201110265040A CN103000227A CN 103000227 A CN103000227 A CN 103000227A CN 2011102650405 A CN2011102650405 A CN 2011102650405A CN 201110265040 A CN201110265040 A CN 201110265040A CN 103000227 A CN103000227 A CN 103000227A
- Authority
- CN
- China
- Prior art keywords
- failure model
- failure
- modeling
- nonvolatile memory
- truth table
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a method for carrying out failure model modeling upon a non-volatile memory product. The method comprises the steps that: first, according to the characteristics of the circuit structure and/or layout of a memory area of the non-volatile memory product, through the analysis upon the circuit node status in a memory array during an operation process of the non-volatile memory product, a failure model-failure characterization truth table is established, wherein the truth table is described by characteristic parameters of three parts which are a potential failure model, a critical circuit analog output, and a failure unit bitmap output; and second, modeling of a true failure model is realized by using the truth table, and physical analysis positioning is guided by using the modeling result. According to the invention, the failure model is established before physical analysis positioning, such that the modeling of the failure model has a systemic feature, and logical rigor and precision of non-volatile memory fault point positioning is greatly improved. Therefore, failure analysis positioning efficiency and success rate are improved.
Description
Technical field
The present invention relates to a kind of semiconductor failure analysis method, be specifically related to a kind of method of the nonvolatile memory series products being carried out the failure model modeling.
Background technology
Disabling unit bitmap (failure bitmap) analytical approach is the common method of storage component part failure analysis.Utilize the bitmap analysis, usually can carry out comparatively accurately localization of fault.But because the diversity of Failure Factors and the complicacy of circuit and domain structure, may bring the deviation of directivity only according to the storage unit bitmap location, thereby bring difficulty for failure analysis.
Summary of the invention
Technical matters to be solved by this invention provides a kind of method that the nonvolatile memory series products is carried out the failure model modeling, and it can provide more accurate reliably Fault Locating Method.
For solving the problems of the technologies described above, the present invention carries out the method for failure model modeling to the nonvolatile memory series products technical solution is may further comprise the steps:
Step 1: according to the circuit structure of nonvolatile memory series products storage area and/or the characteristics of laying out pattern, by the analysis to circuit node state in the memory array in the operating process of nonvolatile memory, set up " failure model-inefficacy a characterizes " truth table, this truth table is described by potential failure model, Key Circuit analog output and disabling unit graphical output three Partial Feature parameters;
Described failure model is circuit level and/or domain level failure model.
The Key Circuit analog quantity of described nonvolatile memory series products has measurability.
Described Key Circuit analog quantity is that nonvolatile memory is carried in program voltage and/or the control voltage in the memory cell array in operating process.
Step 2: use this truth table to realize the modeling of true failure model, then use modeling result to instruct the physical analysis location;
Operation one, storer is tested, obtained the inefficacy characterization information in the truth table, comprise Key Circuit analog quantity and disabling unit message bit pattern;
The inefficacy characterization information that measurement obtains in operation two, the use operation one obtains with input feature vector corresponding failure model by the method for tabling look-up as input in " failure model-inefficacy characterizes " truth table.
The technique effect that the present invention can reach is:
The present invention sets up accurately clearly failure model before carrying out the physical analysis location, can make the modeling of failure model have systematic characteristics, and introduce the Key Circuit analog quantity as the inefficacy characterization parameter, can greatly improve strict logic and the degree of accuracy of nonvolatile memory localization of fault, thereby improve location efficiency and the success ratio of failure analysis, reduce the possibility of artificial error in judgement.
The present invention can overcome the simple limitation that relies on disabling unit bitmap analytical approach in the nonvolatile memory failure analysis, and more accurate reliably Fault Locating Method is provided.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
To be the present invention carry out the failure model that the method for failure model modeling sets up-inefficacy to the nonvolatile memory series products to Fig. 1 characterizes the synoptic diagram of truth table.
Embodiment
The present invention carries out the method for failure of removal locate failure model modeling to the nonvolatile memory series products, may further comprise the steps:
Step 1: according to the circuit structure of nonvolatile memory series products storage area and the characteristics of laying out pattern, by the analysis to circuit node state in the memory array in various operations (such as the wiping/Writing/Reading) process of nonvolatile memory, set up " failure model-inefficacy a characterizes " truth table, this truth table is described by potential failure model (circuit level or domain level failure model), Key Circuit analog output and disabling unit graphical output three Partial Feature parameters, as shown in Figure 1; It is related with the chip features behavior that this truth table comprises the potential failure model;
Failure model refers to the failure model of circuit node level or domain node level, as open circuit short circuit etc.;
Lost efficacy to characterize and referred to that storer was carrying out under the various modes of circuit operation, the disabling unit graphical output result that failure model causes and Key Circuit analog output result's set;
The principle of setting up of this truth table is:
Suppose that one by one the possible case (being the potential failure model) that lost efficacy occurs for circuit node level in the storer or domain node level, then corresponding inefficacy sign can appear in each failure model, namely shows corresponding disabling unit graphical output result and Key Circuit analog output result;
The Key Circuit analog quantity of described nonvolatile memory series products has measurability, namely need to realize in the product circuit design phase design for Measurability of Key Circuit analog output;
The Key Circuit analog quantity can be that nonvolatile memory is carried in program voltage and/or the control voltage in the memory cell array in operating process, such as programming positive high voltage (VPOS), programming negative high voltage (VNEG).
Step 2: use this truth table to realize the modeling of true failure model, then use modeling result to instruct the physical analysis location;
Concrete grammar is:
Operation one, by electric test method storer is tested, obtained the inefficacy characterization information in the truth table, such as Key Circuit analog quantity and disabling unit bitmap (Failure Bitmap) information;
The inefficacy characterization information of measuring acquisition in operation two, the use operation one obtains with input feature vector corresponding failure model (circuit level and domain level) by the method for tabling look-up as input in " failure model-inefficacy characterizes " truth table.
Claims (4)
1. one kind is carried out the method for failure of removal locate failure model modeling to the nonvolatile memory series products, it is characterized in that, may further comprise the steps:
Step 1: according to the circuit structure of nonvolatile memory series products storage area and/or the characteristics of laying out pattern, by the analysis to circuit node state in the memory array in the operating process of nonvolatile memory, set up " failure model-inefficacy a characterizes " truth table, this truth table is described by potential failure model, Key Circuit analog output and disabling unit graphical output three Partial Feature parameters;
Step 2: use this truth table to realize the modeling of true failure model, then use modeling result to instruct the physical analysis location;
Operation one, storer is tested, obtained the inefficacy characterization information in the truth table, comprise Key Circuit analog quantity and disabling unit message bit pattern;
The inefficacy characterization information that measurement obtains in operation two, the use operation one obtains with input feature vector corresponding failure model by the method for tabling look-up as input in " failure model-inefficacy characterizes " truth table.
2. according to claim 1 the nonvolatile memory series products is carried out the method for failure of removal locate failure model modeling, it is characterized in that described failure model is circuit level and/or domain level failure model.
3. according to claim 1 the nonvolatile memory series products is carried out the method for failure of removal locate failure model modeling, it is characterized in that the Key Circuit analog quantity of described nonvolatile memory series products has measurability.
4. method of the nonvolatile memory series products being carried out failure of removal locate failure model modeling according to claim 1, it is characterized in that described Key Circuit analog quantity is that nonvolatile memory is carried in program voltage and/or the control voltage in the memory cell array in operating process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102650405A CN103000227A (en) | 2011-09-08 | 2011-09-08 | Method for carrying out failure model modeling upon non-volatile memory product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102650405A CN103000227A (en) | 2011-09-08 | 2011-09-08 | Method for carrying out failure model modeling upon non-volatile memory product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103000227A true CN103000227A (en) | 2013-03-27 |
Family
ID=47928697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011102650405A Pending CN103000227A (en) | 2011-09-08 | 2011-09-08 | Method for carrying out failure model modeling upon non-volatile memory product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103000227A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1598780A (en) * | 2003-09-16 | 2005-03-23 | 蔚华科技股份有限公司 | Memory shortage diagnostic method using failure mode as guide and its system |
| US20070234161A1 (en) * | 2006-01-10 | 2007-10-04 | Blanton Ronald D | Using neighborhood functions to extract logical models of physical failures using layout based diagnosis |
| CN101178941A (en) * | 2007-11-16 | 2008-05-14 | 浙江大学 | Method for dynamically estimating memory body characteristic ineffective cause of defect |
| CN101241770A (en) * | 2007-01-15 | 2008-08-13 | 三星电子株式会社 | Defect analysis methods for semiconductor integrated circuit devices and defect analysis systems |
-
2011
- 2011-09-08 CN CN2011102650405A patent/CN103000227A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1598780A (en) * | 2003-09-16 | 2005-03-23 | 蔚华科技股份有限公司 | Memory shortage diagnostic method using failure mode as guide and its system |
| US20070234161A1 (en) * | 2006-01-10 | 2007-10-04 | Blanton Ronald D | Using neighborhood functions to extract logical models of physical failures using layout based diagnosis |
| CN101241770A (en) * | 2007-01-15 | 2008-08-13 | 三星电子株式会社 | Defect analysis methods for semiconductor integrated circuit devices and defect analysis systems |
| CN101178941A (en) * | 2007-11-16 | 2008-05-14 | 浙江大学 | Method for dynamically estimating memory body characteristic ineffective cause of defect |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9129678B2 (en) | Method and apparatus for reforming a memory cell of a memory | |
| CN101859606B (en) | Method and equipment for adjusting reference unit threshold parameter and testing system | |
| CN103728516A (en) | Soc chip clock detection circuit | |
| CN103823139B (en) | A kind of ageing method based on SIP module | |
| CN104751896A (en) | Built-in self-testing circuit | |
| CN105580083A (en) | Resistance-based memory cells with multiple source lines | |
| CN102682852B (en) | Semiconductor storage | |
| CN104464824B (en) | The method of testing of metal-oxide-semiconductor threshold voltage in storage array | |
| CN102565682B (en) | Method for positioning fault testing vectors on basis of bisection method | |
| CN104484162A (en) | Software testing case designing and writing method | |
| CN105243013A (en) | Software testing method and system | |
| CN207742296U (en) | A kind of addressable test chip test system | |
| CN104751875A (en) | Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip | |
| US9159455B2 (en) | Data retention error detection system | |
| CN103000227A (en) | Method for carrying out failure model modeling upon non-volatile memory product | |
| CN102903393B (en) | Memory built in self test of sram circuit | |
| CN106154133B (en) | The address test method of chip and the failure analysis method of chip | |
| CN116430826A (en) | Electronic controller working condition coupling test method based on offshore atmospheric environment laboratory | |
| CN202758882U (en) | Trimming device of analog/digital analogy mixed signal processing chip | |
| CN109145338A (en) | A kind of method and device for repairing voltage drop | |
| CN112597002A (en) | Python script based test vector generation method | |
| CN103972122A (en) | Wafer probing method and wafer probing device | |
| CN102737725A (en) | Programmable built-in self testing system capable of automatic optimization on memory performance and built-in self testing method | |
| CN202975264U (en) | Test fixture for performing on-line testing on notebook computer | |
| CN105448333A (en) | Flash memory and processing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130327 |