CN102986013A - 具有电互连的气密晶片间结合 - Google Patents
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- CN102986013A CN102986013A CN2011800325101A CN201180032510A CN102986013A CN 102986013 A CN102986013 A CN 102986013A CN 2011800325101 A CN2011800325101 A CN 2011800325101A CN 201180032510 A CN201180032510 A CN 201180032510A CN 102986013 A CN102986013 A CN 102986013A
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Abstract
本发明公开了一种可植入医疗设备(IMD)。该IMD包括第一衬底,第一衬底具有前侧和后侧。在前侧中形成第一通孔,该通孔从位于前侧的底部点延伸至位于前侧的表面处的第一高度。在第一通孔中形成第一导电板,且第一导电板具有低于第一高度的暴露的顶部表面。第二衬底耦合至第一衬底,第二衬底具有形成在前侧中的第二通孔,该通孔从前侧的底部点延伸至位于前侧表面的第二高度。在第二通孔中形成第二导电板,且第二导电板具有低于第二高度的暴露的顶部表面。被耦合的衬底被加热,直到一个或两个导电板的一部分回流、去湿、凝聚、并合并来形成互连、气密密封、或两者,这取决于设备的要求。
Description
发明领域
本发明大体涉及在材料间创建电互连,且更具体地,涉及在与低温气密晶片间结合兼容的材料之间创建电互连。此外,此处描述的方法可被应用于在晶片之间创建气密金属密封。
背景技术
很多电子组件使用集合电路或芯片。IC包括形成在半导体材料的薄衬底表面中的半导体器件(如,二极管、晶体管等)和无源组件(如,晶体管、电容器、电阻器等)。
通过晶片间结合,一个IC可连接至另一个IC或其他晶片。晶片间结合涉及接合晶片的主要表面。被接合的晶片区域创建了气密密封(多个)。
晶片间结合的一个类型依赖于设置在每个晶片上的铜板。铜板高于晶片的周围平面。一个晶片上的铜板与另一个晶片上的铜板对齐。可采用热压缩扩散结合来接合位于每一个晶片上的铜板。然后IC与靠近独立芯片的外缘处的铜密封环或圈轨(race track)密封在一起。铜不是生物稳定的且对于可植入医疗设备不可在活体内提供充足的密封。此外,与热氧化物共面的铜板可难以平面化和抛光。例如,铜和热氧化物可具有不同的抛光率。因此,为了有效且气密地密封IMD中的电子线路,期望开发新的技术。
发明内容
本发明涉及包括一个或多个集成电路的可植入医疗设备(IMD)。至少一个集成电路包括结合至第二衬底的第一衬底。第一衬底具有前侧和后侧。第一通孔被形成在前侧中。该通孔从底点延伸至位于前侧的表面上的第一高度。第一导电板被形成于第一通孔中。第一导电板具有底部表面和顶部表面。第一导电板具有低于通孔的第一高度的暴露的顶部表面。在一个或多个实施例中,第二衬底具有形成在前侧中的第二通孔。该通孔从底点延伸至位于前侧的表面上的第二高度。第二导电板被形成于第二通孔中。第二导电板具有低于第二高度的暴露的顶部表面。施加热至第一和第二衬底,作为响应,此举引起第一和第二导电板在第一和第二衬底之间流动并形成单个回流的互连。
在一个或多个实施例中,公开了一种方法,用于为可植入医疗设备形成集成电路。在一个或多个实施例中,第一通孔形成在第一衬底的第一侧中。然后第一导电板被沉积于第一通孔中。第一导电板的暴露的顶部表面低于第一通孔的顶部表面。在一个或多个实施例中,第二通孔形成在第二衬底的第一侧中。第二导电板被沉积于第二通孔中。第二导电板的暴露的顶部表面低于第二通孔的顶部表面。施加热,此举使得第一和第二导电板的部分去湿。例如,在其中导电板被沉积在诸如玻璃(也称为热氧化物(即,SiO2))之类的绝缘体上的区域中,第一和第二导电板的部分可去湿。响应于使得第一和第二导电板的暴露的表面低于每一个相应通孔的高度、且响应于热量,导电块或单个回流的互连形成在第一和第二导电板之间并将第一和第二导电板接合在一起。形成在第一和第二衬底之间的导电互连可以是拱顶形、沙漏形、或球形的。该导电互连创建第一和第二衬底之间的机械和电互连。以此方式可在第一和第二衬底之间形成多个互连。当被冷却时,可生产出所得的互连的设备。
在一个或多个其他实施例中,可用上述相同方式、在设置在第一和第二衬底之间的第一和第二导电板之间、围绕设备的外围形成圈轨。在加热和冷去后,沿圈轨形成气密密封。由于圈轨形成的气密密封,沿圈轨形成的气密密封消除了在常规设备中一般会有的附加封装的需要。没有附加封装允许设备相比常规设备在大小上显著地减少。
在一个或多个实施例中,由诸如玻璃或硅之类的生物稳定晶片形成第一和/或第二衬底。例如,结合至第二衬底的第一衬底可以是玻璃-玻璃、玻璃-硅、或硅-硅,如下文将所知的,在整个晶片上除包含板结构和圈轨或密封的较小凹入区域之外,形成结合。
在一个或多个实施例中,由底层的粘合或阻挡材料支撑第一和/或第二导电板。粘合材料可包括诸如铬和/或钛之类的过渡金属元素以及诸如金之类的可湿性材料。诸如金锡(AuSn)之类的第一导电板在可湿性导电板上被沉积为薄层,且AuSn沉积的面积大于可湿性导电板。AuSn金属化的顶部仍位于晶片的上表面之下,从而不干扰晶片结合。在晶片结合后或在晶片结合过程中,温度被提升超过AuSn的熔点(~280℃)。AuSN从围绕金板的玻璃中去湿且可在板上形成基本球形或拱顶形。这个焊料凸点或球的高度由板的尺寸以及在板和周围玻璃上沉积的AuSn的面积与体积所确定。在溶解过程中,AuSn球的顶部接合至类似的AuSn球、或者接合至配对晶片上的可湿性板。可使用相同或类似的过程来创建在设备的外缘周围的密封。
附图简述
图1是示出包含可植入心脏设备(ICD)的示例性治疗系统的概念示图。
图2是更详细地示出图1中的ICD和各引线的概念示图。
图3是更详细地示出图1和2中的ICD和各引线的概念示图。
图4是产生并传递电刺激至患者心脏的示例性ICD的功能框图。
图5是示例医疗设备编程器的功能框图。
图6示出已经经受研磨操作的衬底的示意图。
图7示出已经经受清洁操作的图6的衬底的示意性侧视图。
图8示出形成在图7中所示的衬底的前侧和后侧上的热氧化物的示意性侧视图。
图9示出其中在后侧中形成刻线(scribe)的图8的衬底后侧的示意性侧视图。
图10示出从中移除了热氧化物的图9的衬底的示意性侧视图。
图11示出已经经受清洁操作的图10的衬底的示意性侧视图。
图12示出在图11中所示衬底上形成的热氧化物的示意性侧视图。
图13示出在图12中所示热氧化物上沉积的光致抗蚀剂的示意性侧视图。
图14示出在图13中所示光致抗蚀剂上放置的掩模的示意性侧视图。
图15示出从图14中所示热氧化物层移除的暴露的光致抗蚀剂的示意性侧视图。
图16示出从图15中移除的暴露的热氧化物的示意性侧视图。
图17示出与图16中所示衬底相比,光致抗蚀剂的其余部分的移除。
图18示出经受清洁操作的图17的衬底的示意性侧视图。
图19示出在图18的衬底上形成的热氧化物的示意性侧视图。
图20示出施加光致抗蚀剂至图19中所示衬底后侧的示意图。
图21示出在图20中所示光致抗蚀剂上放置的掩模的示意图。
图22示出从图21中所示衬底移除的所暴露的光致抗蚀剂的示意图。
图23示出在图22中所示衬底的热氧化物中形成的通孔的示意图。
图24示出在图23中所示衬底上的热氧化物中移除光致抗蚀剂的示意图。
图25示出由沉积在位于图24中所示衬底的前侧上的热氧化物中的通孔中的第一、第二、和第三导电材料形成的板的示意图。
图26示出在图25中所示第三导电材料上沉积的光致抗蚀剂的示意图。
图27示出在图26中所示光致抗蚀剂的一部分上放置的掩模的示意图。
图28示出从图27中所示第三导电金属移除的所暴露的光致抗蚀剂的示意图。
图29示出移除第一、第二、和第三导电材料的一部分的示意图。
图30示出移除光致抗蚀剂的剩余部分的侧视图。
图31示出在第一、第二、和第三导电材料上的绝缘层的示意图。
图32示出在图31中所示绝缘层上形成的光致抗蚀剂的示意图。
图33示出在图32中所示光致抗蚀剂上的掩模的示意图。
图34示出从在图33中所示衬底移除的光致抗蚀剂一部分的示意图。
图35示出从图34中所示第三导电材料蚀刻掉绝缘层一部分的示意图。
图36示出从绝缘层移除剩余的光致抗蚀剂的侧视图。
图37示出从第二导电材料所移除的第三导电材料的一部分的示意图。
图38示出在第二导电材料和绝缘层上沉积的金锡示意图。
图39示出在图38中所示金锡上形成的光致抗蚀剂的示意图。
图40示出在图39中所示光致抗蚀剂上的掩模的示意图。
图41示出从图40中所示组件移除所暴露的光致抗蚀剂的示意图。
图42示出从图41中所示热氧化物层中蚀刻金锡的一部分的示意图。
图43示出从图42中所示金锡层移除光致抗蚀剂一部分的示意图。
图44示出抛光绝缘层的顶部表面的示意图。
图44a示出其中导电材料已经经受回流处理的完成的晶片的示意图。
图45示出耦合至第二衬底的前侧的第一衬底的前侧的示意图。
图46示出在第一和第二衬底之间的气密结合的示意图。
图47示出在第一和第二衬底之间延伸从而形成互连的金锡的示意图。
图48示出穿通衬底形成的通孔的示意图。
图49示出从图48中所示衬底之一移除热氧化物的示意图。
图50示出用于形成能够在将经受晶片间结合的晶片之间形成互连的板的方法的流程图。
图51示出带有氧化物交迭的晶片间结合的示意性侧视图。
图52示出没有氧化物交迭的晶片间结合的示意性侧视图。
图53示出在回流处理前凸点与板间结构的示意图。
图54示出在回流处理后图53中所示凸点与板间结构的示意图。
图55示出已经经受清洁操作并在衬底的第一和第二侧上形成热氧化物后的衬底的示意图。
图56示出在衬底侧边上形成第一板层的示意图。
图57示出其中在衬底的整个表面上形成薄层热氧化物的示意图。
图58示出形成在通孔中的导电金属的示意图。
图59示出移除第一、第二、和第三导电材料的一部分的示意图。
图60示出在导电材料上沉积的金锡的示意图。
图61示出其中导电材料的一部分被移除的示意图。
图62示出在经受接触抛光操作后的热氧化物层。
图63示出由图55-62中所示的处理形成的凸点间结构。
图64示出在回流处理后凸点与配对金属板间结构的示意图。
图65示出在回流处理前凸点与板间结构的示意图。
图66示出在回流处理后凸点与板间结构的示意图。
图67示出在衬底的两侧上形成的热氧化物。
图68示出在图67中所示衬底一侧上的热氧化物中的通孔的形成。
图69示出在图68中所示衬底的整个表面上形成的薄层热氧化物。
图70示出沉积到图69中所示通孔中的导电材料示意图。
图71示出被移除的第一、第二、和第三导电材料的部分。
图72示出在导电材料上化学气相沉积氧化物或氮化物或两者。
图73示出从图72中所示结构移除的氧化物或氮化物层的一部分。
图74示出从图73中所示衬底移除的导电层的一部分。
图75示出在图74所示结构上沉积的金锡。
图76示出从图75中所示衬底移除的金锡的一部分。
图77示出在经受光抛光操作后的图76的结构。
图78示出耦合至另一个晶片前侧的一个晶片的前侧。
图79示出从图78中所示的实施例形成的晶片间结合。
图80示出其中晶片之一包括配对金属板的另一个实施例。
图81示出在回流后的凸点与配对金属板。
图82示出其中实现晶片间互联技术来形成气密密封中的密封环的俯视图。
图83示出重要的几何形状被加以标记的凸点结构的示意图。
图84示出在没有配对凸点的情况下,回流的、拱顶型、单个凸点的SEM。
具体实施方式
图6-84中所示的本公开以及随附文本公开了晶片间结合和电连接的形成,其可被用于图1-5中所示的各种可植入医疗设备(IMD),其中期望有较小尺寸、气密、和多个管芯连接。各种组件可采用此处描述的技术。传感器(如,无线传感器、有线传感器)、智能引线和/或微型治疗设备代表了可实现本发明的教导的组件类型。传感器、智能引线或微型化设备可被或可不被保护并封在可植入心律转变除颤器(ICD)钛罐或壳中。明显的是,来自一个实施例的元件可被与其他实施例的元件组合使用,且此处说明的使用特征组合的这样的装置的可能的实施例不限于附图中所示和/或此处描述的特定实施例。进一步,可理解的是此处描述的实施例可包括并不需要按比例绘制的很多元件。进一步,可理解的是此处各元件的大小和形状可被修改但仍落在本发明的范围内,虽然一个或多个形状和/或大小、或元件类型可相比其他有利。
图1是示出可被用于提供治疗至患者14的心脏12的示例性治疗系统10的概念示图。治疗系统10包括结合有此处描述的半导体处理的一个或多个集成电路。患者12通常但不一定是人类。治疗系统10包括IMD16,其耦合至引线18、20、和22以及编程器24。IMD 16可以是,例如,可植入起搏器、复律器、和/或除颤器,经由耦合至一个或多个引线18、20、和22的电极向心脏12提供电信号。
引线18、20、22延伸至患者16的心脏12内来感测心脏12的电活动和/或将电刺激传递至心脏12。在图1所示的示例中,右心室(RV)引线18延伸通过一个或多个静脉(未示出)、上腔静脉(未示出)、和右心房26,并进入右心室28。左心室(LV)冠状窦引线20延伸通过一个或多个静脉、腔静脉、右心房26、并进入冠状窦30至与心脏12的左心室32的自由壁相邻的区域。右心房(RA)引线22延伸通过一个或多个静脉和腔静脉、并进入心脏12的右心房26。
IMD 16,经由耦合至至少一个引线18、20、22的电极(在图1中未示出),可感测进行心脏12的去极化和复极化的电信号。在一些示例中,IMD 16基于在心脏12中感测到的电信号,提供起搏脉冲至心脏12。由IMD 16使用的用于感测和起搏的电极的配置可以是单极的或双极的。IMD 16还可经由位于至少一个引线18、20、22上的电极提供去心脏纤颤治疗和/或复律治疗。IMD 16可检测心脏12的心律不齐,诸如心室28和32的心室纤颤,并将去心脏纤颤治疗以电脉冲的形式传递至心脏12。在一些示例中,可对IMD 16编程以传递治疗的进展,例如具有递增能级的脉冲,直到心脏12的心室纤颤停止为止。IMD 16利用本领域已知的一种或多种心室纤颤检测技术来检测心室纤颤。
在一些示例中,编程器24可以是手持式计算设备或计算机工作站。编程器24可包括从用户处接收输入的用户接口。用户接口可包括例如键区和显示器,所述显示器例如可以是阴极射线管(CRT)显示器、液晶显示器(LCD)或发光二极管(LED)显示器。键区可以采用字母数字键盘或与特定功能相关联的键的精简集。编程器24可附加或替代地包括外围定点设备,例如鼠标,通过该外围定点设备用户可通过用户接口形成交互。在一些实施例中,编程器24的显示器可包括触摸屏显示器,并且用户可经由显示器与编程器24进行交互。
例如医师、技术人员、或其它临床医生之类的用户可与编程器24交互以与IMD 16通信。例如,用户可与编程器24交互以从IMD 16得到生理学或诊断信息。用户也可与编程器24交互以对IMD 16编程,例如为IMD的操作参数选择一些值。
例如,用户可使用编程器24从IMD 16得到有关心脏12的心律、其随时间的趋势、或快速性心律失常症状的信息。作为另一个示例,用户可使用编程器24从IMD 16获得有关病人14的其他所感测到的生理学参数(诸如心脏内或血管内的压力、活动、姿态、呼吸、或胸阻力)有关的信息。作为另一个示例,用户可使用编程器24从IMD 16获得关于IMD 16或系统10的其它组件(诸如IMD 16的引线18、20和22、或电源)的性能或完整性的信息。
用户可使用编程器24编程治疗进展、选择用于传递去纤颤脉冲的电极、选择去纤颤脉冲的波形、或者选择或配置IMD 16的去纤颤检测算法。用户也可使用编程器24编程由IMD 14提供的其它治疗的各方面,例如复律或起搏治疗。在一些示例中,用户可通过经由编程器24输入单个命令,诸如按下键盘的单个键或多个键组合或通过定点设备的单次点击和选择动作,来激活IMD 16的特定特征。
IMD 16和编程器24可使用本领域已知的任何技术通过无线通信来通信。通信技术的示例可包括例如低频或射频(RF)遥测,但也可考虑采用其它技术。在一些示例中,编程器24可包括设置在靠近IMD 16植入点附近的患者身体的编程头,从而改进IMD 16和编程器24之间的通信的质量和安全性。
图2是更详细地示出治疗系统10的IMD 16和引线18、20和22的概念图。引线18、20、22可经由连接器块34电耦合至刺激发生器、感测模块、或其他模块IMD 16。在一些示例中,引线18、20、22的近端可包括电触点,其电耦合至连接器块34中的各对应电触点。此外,在一些示例中,引线18、20、22可在定位螺丝、连接销、或另一个合适的机械耦合装置的帮助下,机械地耦合至连接器块34。
引线18、20、22中的每一个包括细长绝缘引线本体,该细长绝缘引线本体可承载数根同心绕制的线圈式导体,这些同心绕制的线圈式导体通过管状绝缘包鞘彼此分隔开。在图示示例中,压力传感器38和双极电极40和42位于邻近引线18的远端处。此外,双极电极44和46位于邻近引线20的远端处,且双极电极48和50位于邻近引线22的远端处。在图2中,压力传感器38被配置在右心室28中。压力传感器38可响应于右心室28内的绝对压力,且可以是,例如,电容性或压电绝对压力传感器。在其他示例中,压力传感器38可被放置在心脏12的其他区域中,且可监测心脏12的一个或多个其他区域中的压力,或可被放置在患者14的心血管系统中任何地方或邻近心血管系统的任何地方,来监测与心脏的机械收缩相关联的心血管压力。
电极40、44和48可采用环形电极的形式,且电极42、46和50分别可采用可伸缩地安装在绝缘电极头52、54和56中的可伸长的螺旋尖端电极的形式。电极40、42、44、46、48、和50中的每一个可电耦合于其相关联引线18、20、22的引线本体内各相应的线圈式导体之一,并由此耦合至位于引线18、20、和22的近端上的各相应的一个电触点。
电极40、42、44、46、48、和50可感测进行心脏12的去极化和复极化的电信号。电信号经由各相应引线18、20、22被传导至IMD 16。在一些示例中,IMD 16还经由电极40、42、44、46、48、和50传递起搏脉冲来引起心脏12的心脏组织的去极化。在一些示例中,如图2中所示,IMD 16包括一个或多个外壳电极,诸如外壳电极58,其可被与IMD 16的气密外壳60的外表面一体地形成或耦合至外壳60。在一些示例中,外壳电极58由IMD 16的外壳60的面朝外部分的非绝缘部分限定。可采用外壳60的绝缘和非绝缘部分的其他区分来定义两个或更多个外壳电极。在一些示例中,外壳电极58包括基本全部的外壳60。可使用电极40、42、44、46、48、和50中的任意用于单极感测或与外壳电极58相组合的起搏。
如参看图4更详细地描述地,外壳60可封入产生心脏起搏脉冲和去极化或复律冲击的刺激发生器,还有用于检测患者心律的感测模块。
引线18、20、22还各自包括细长电极62、64、66,它们可采取线圈的形式。IMD 16可经由细长电极62、64、66和外壳电极58的任意组合来将去极化冲击传递至心脏12。还可使用电极58、62、64、66来将复律脉冲传递至心脏12。电极62、64、66可从任何合适的导电材料制成,诸如但不限于,铂、铂合金或已知可用在可植入去极化电极中的其他材料。
压力传感器38可被耦合至引线18中的一个或多个线圈式导体。在图2中,压力传感器38相比细长电极62,位于更为远离引线18处。在其他示例中,压力传感器38相比细长电极62可被放置为更为靠近、而不是远离电极62。进一步,在其他示例中,压力传感器38可被耦合至引线20、22中的另一个,或者耦合至除携载刺激的引线18、20、22和感测电极之外的引线。此外,在一些示例中,压力传感器38可以是植入在心脏12内(诸如在将右心室28与左心室32分离的隔膜中、或在将右心房26与左心房33分离的隔膜中)的自包含设备。在这样的示例中,压力传感器38可与IMD 16无线通信。
图1和2中示出的治疗系统10的配置仅为一个示例。在其他示例中,除了在图1中所示的经静脉引线18、20、22之外,或替代其,治疗设备可包括心外膜引线和/或贴片电极。进一步,IMD 16不需要被植入在患者14中。在其中IMD 16未被植入在患者14体内的示例中,IMD 16可经由经皮引线将去极化冲击和其他治疗传递至心脏12,该经皮引线通过患者14的皮肤延伸到心脏12内或外的各个位置。
在提供电刺激治疗至心脏12的治疗系统的其他示例中,治疗系统可包括耦合至IMD 16的任何合适数量的引线,且每一个引线可延伸至心脏12内或邻近心脏12的任何位置。例如,治疗系统的其他示例可包括如图1和2中被放置的三个经静脉引线,和置于左心房33或邻近左心房33的附加引线。作为另一个示例,治疗系统的其他示例可包括从IMD 16延伸至右心房26或左心室28的单个引线、或延伸至右心室26和右心房28中的各对应一个的两个引线。这个类型的治疗系统的示例被图示于图3中。
图3是示出另一示例治疗系统70的概念图,其类似于图1-2的治疗系统10但包括两个引线18、22,而不是三个引线。引线18、22分别被植入右心室28和右心房26。图3中所示的治疗系统70可用于提供去极化和起搏脉冲至心脏12。
图4是IMD 16的一个示例性配置的功能框图,其包括处理器80、存储器82、刺激发生器84、感测模块86、遥测模块88、和电源90。存储器82包括计算机可读指令,当其在处理器80上被执行时,引起IMD 16和处理器80执行归于此处的IMD 16和处理器80的各种功能。存储器82可包括任何易失性、非易失性、磁、光或电介质,例如随机存取存储器(RAM)、只读存储器(ROM)、非易失性RAM(NVRAM)、电可擦除可编程ROM(EEPROM)、闪存或任何其它数字介质。
处理器80可包括微处理器、控制器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或等效的分立或集成逻辑电路中的一个或多个。在一些示例中,处理器80可包括多个组件,例如一个或多个微处理器、一个或多个控制器、一个或多个DSP、一个或多个ASIC或者一个或多个FPGA以及其它分立或集成逻辑电路的任意组合。归于此处的处理器80的功能可体现为软件、固件、硬件、或者其任意组合。处理器80,根据可存储在存储器82内的选定的一个或多个治疗程序,控制刺激发生器84来将刺激治疗传递至心脏12。特定地,处理器44可控制刺激发生器84以传递具有由选定的一个或多个治疗程序指定的振幅、脉宽、频率或电极极性的电脉冲。
刺激发生器84,如,经由各相应引线18,20,22、或在外壳电极58的情况下经由设置在IMD 16的外壳60内的电导体,电耦合至电极40,42,44,46,48,50,58,62,64,和66。刺激发生器84被配置为产生并传递电刺激治疗至心脏12。例如,刺激发生器84可经由至少两个电极58,62,64,66传递去极化冲击至心脏12。刺激发生器84可经由耦合至引线18、20、和22的各环形电极40、44、48,和/或引线18、20、和22的各螺旋形电极42、46、和50,传递起搏脉冲。在一些示例中,刺激发生器84以电脉冲的形式传递起搏、复律、或去极化刺激。在其它示例中,刺激发生器可以诸如正弦波、方波或其它基本连续时间信号之类的其它信号形式传递这些类型的刺激中的一种或多种。
刺激发生器84可包括开关模块,且处理器80可使用开关模块,例如经由数据/地址总线,来选择可用电极中的哪些用来传递去极化冲击或起搏脉冲。开关模块可包括开关阵列、开关矩阵、多路复用器或适于有选择地将刺激能量耦合于所选电极的任意其它类型开关器件。
感测模块86监测来自电极40,42,44,46,48,50,58,62,64,或66中的至少一个的信号,从而例如,经由心电图(ECG)信号监测心脏12的电活动。感测模块86还可包括开关模块来选择哪些可用电极被用于感测心脏活动。在一些示例中,处理器80可经由感测模块86中的开关模块,例如通过藉由数据/地址总线提供信号,来选择用作感测电极的电极。在一些示例中,感测模块86包括一个或多个感测通道,每个感测通道可包括一放大器。响应来自处理器80的信号,感测模块86中的开关模块可将来自所选电极的输出耦合至其中一个感测通道。
在一些示例中,感测模块86的一个通道可包括R-波放大器,其从电极40和42接收信号,该信号被用于起搏并感测心脏12的右心室28。另一个通道可包括另一个R-波放大器,其从电极44和46接收信号,该信号被用于在邻近心脏12的左心室32之处起搏并感测。在一些示例中,R-波放大器可采用自动增益受控放大器的形式,其提供可调节感测阈值,该阈值因变于心律的测得的R-波幅值。
此外,在一些示例中,感测模块86的一个通道可包括P-波放大器,其从电极48和50接收信号,该信号被用于在心脏12的右心房26内起搏并感测。在一些示例中,P-波放大器可采用自动增益受控放大器的形式,其提供可调节感测阈值,该阈值因变于心律的测得的P-波幅值。R波和P波放大器的示例描述在1992年6月2日授权的名为“APPARATUS FOR MONITORINGELECTRICAL PHYSIOLOGIC SIGNALS”的Keimel等人的美国专利No.5,117,824中,并全文援引纳入本文中。也可使用其它放大器。此外,在一些示例中,感测模块86的一个或多个感测通道可选择性地耦合至外壳电极58、或细长电极62、64或66,与一个或多个电极40、42、44、46、48或50一起或取代一个或多个电极40、42、44、46、48或50,例如用于单极感测心脏12的任意腔26、28或32中的R波或P波。
在一些示例中,感测模块86包括一通道,该通道包括具有比R波或P波放大器相对更宽通频带的放大器。来自被选择用于耦合至该宽带放大器的所选感测电极的信号可被提供至多路复用器,并随后通过模数转换器转换成多位数字信号用于存储在存储器82中作为心电图(EGM)。在一些示例中,将该EGM存储在存储器82中可在直接存储器存取电路的控制下进行。处理器80可采用数字信号分析技术来表征存储在存储器82中的数字化信号的特征以从电信号检测并分类患者的心率。处理器80可通过采用本领域内已知的众多信号处理方法中的任何方法来检测并分类患者14的心率。
如果IMD 16被配置为产生并传递起搏脉冲至心脏12,处理器80可包括起搏定时与控制模块,其可被实现为硬件、固件、软件、或其组合。起搏器定时与控制模块可包括与诸如微处理器之类的其他处理器80组件分离的专用硬件电路,例如ASIC、或包括可由处理器80的组件(可以是微处理器或ASIC)执行的软件模块。起搏器定时与控制模块可包括可编程计数器,其控制与DDD、VVI、DVI、VDD、AAI、DDI、DDDR、VVIR、DVIR、VDDR、AAIR、DDIR/以及单和双腔起搏的其他模式,相关联的基本时间间隔。在前面提到的起搏模式中,“D”可指示双腔,“V”可指示心室,“I”可指示被禁止的起搏(例如无起搏),而“A”可指示心房。起搏模式中的第一个字母可指示被起搏的腔,第二个字母可指示其中感测到电信号的腔,而第三个字母可指示其中提供对感测的响应的腔。
处理器80中的起搏器定时与控制模块所定义的间隔可包括心房与心室逸搏间隔、不应期(其中所感测的P-波和R-波不能有效地重启逸搏间隔的定时)、和起搏脉冲的脉冲宽度。作为另一个示例,起搏器定时与控制模块可定义消隐期(blanking period),并提供来自感测模块86的信号来,在电刺激传递至心脏12的过程中或之后,消隐一个或多个通道,如,放大器,达一段时间。这些间隔的持续时间可由处理器80响应于存储器82中所存储的数据来确定。处理器80的起搏器定时与控制模块还可确定心脏起搏脉冲的幅值。
在起搏过程中,一旦感测到R-波或P-波,处理器80的起搏器定时与控制模块内的逸博间隔计数器可被重设。刺激生成器84可包括起搏器输出电路,该电路,如,通过转换模块被选择性地耦合至电极40,42,44,46,48,50,58,62,或66的任意组合,该组合适于传递单极或双极起搏脉冲至心脏12的一个腔。一旦刺激生成器84产生起搏脉冲,处理器80可重置逸博间隔计数器,且藉此控制心脏起搏功能(包括抗快速性心律失常起搏)的基本定时。
当由所感测到的R-波和P-波重置时逸博间隔计数器中现有的计数的值可由处理器80使用来感测R-R间隔、P-P间隔、P-R间隔、和R-P间隔的持续时间,这是可被存储于存储器82中的测量。处理器80可使用间隔计数器中的计数来检测快速性心律失常起搏事件,诸如心室纤颤事件或心室心动过速事件。一旦检测到阈值数目的快速性心律失常事件,处理器80可标识快速性心律失常症状的存在,诸如心室纤颤症状、心室心动过速症状、或非持久心动过速(NST)症状。
在一些示例中,处理器80可作为中断驱动设备工作,且响应于来自起搏器定时与控制模块92的中断,其中中断可对应于所感测的P波和R波的发生以及心脏起搏脉冲的产生。将由处理器80执行的任何必要的数学计算以及受处理器80的起搏器定时与控制模块所控制的值或间隔的任何更新可紧随这些中断之后发生。存储器82的一部分可被配置为多个再循环缓存,能保持一系列所测得的间隔,处理器80响应起搏或感测中断的发生来分析这些间隔以确定患者的心脏12目前是否表现出心房或心室快速性心律失常。
在一些示例中,心律失常检测方法可包括任何合适的快速性心律失常检测算法。在一个示例中,处理器80可利用1996年8月13日授权的名为“PRIORITIZED RULE BASED METHOD AND APPARATUS FORDIAGNOSIS AND TREATMENT OF ARRHYTHMIAS”的Olson等人的美国专利No.5,545,186、或1998年5月26日授权的名为“PRIORITIZED RULE BASEDMETHOD AND APPARATUS FOR DIAGNOSIS AND TREATMENT OFARRHYTHMIAS”的Gillberg等人的美国专利No.5,755,736中记载的基于规则的检测方法的全部或其一部分。Olson等人的美国专利No.5,545,186和Gillberg等人的美国专利No.5,755,736通过援引整体并入此处。然而,在其它示例中,其它心律失常检测方法也可由处理器80采用。
在本文描述的示例中,处理器80可通过检测指示快速性心律失常的平均速率的一系列快速性心律失常事件(例如具有小于或等于阈值的持续时间的R-R或P-P间隔)或不间断的一系列短暂R-R或P-P间隔,来标识心房或心室快速性心律失常症状的存在。用于确定指示快速性心律失常事件的R-R或P-P间隔的阈值可被存储于IMD 16的存储器82中。此外,被检测来确认快速性心律失常症状的存在的快速性心律失常事件的次数可被存储为存储器82中多个的检测间隔数(NID)阈值。在一些示例中,处理器80还可通过检测心脏信号的R-波之间的可变耦合间隔来标识快速性心律失常症状的存在。例如,如果连续快速性心律失常事件之间的间隔变化特定百分比或耦合间隔之间的差超过预定数量的连续循环均高于给定阈值,则处理器80可确定快速性心律失常存在。
如果处理器80基于来自感测模块86的信号检测出心房或心室快速性心律失常、且期望抗快速性心律失常起搏疗法(regimen)的状况下,可通过处理器80,将用于控制信号发生器84产生抗快速性心律失常起搏治疗的时间间隔加载入起搏器定时与控制模块以控制其中的逸博间隔计时器的操作并定义其中R波和P波的检测不能有效重启逸博间隔计时器的不应期。
如果IMD 16被配置成产生去纤颤脉冲并将其传递至心脏12,则刺激发生器84可包括高压充电电路和高压输出电路。在需要产生复律或去纤颤冲击的情况下,处理器80可利用逸博间隔计数器来控制这样的复律和去纤颤冲击的定时、以及相关联的不应期。响应于心房或心室纤颤或要求复律脉冲的快速性心律失常的检测,处理器80可激活复律/去纤颤控制模块,其可以,同起搏器定时与控制模块一样,是处理器80的硬件组件和/或固件或由处理器80的一个或多个硬件组件所执行的软件模块。在高压充电控制线的控制下,复律/去纤颤控制模块可初始化刺激生成器84的高压充电电路的高压电容的充电。
处理器80可例如经由电压充电与电位(VCAP)线监测高压电容器上的电压。响应于高压电容器上的电压达到由处理器80设定的预定值,处理器80可产生终止充电的逻辑信号。此后,刺激生成器84的对于去纤颤或复律脉冲的传递受控于处理器80的复律/去纤颤控制模块。在纤颤或心动过速的治疗传递之后,处理器80可将刺激生成器84恢复至心脏起搏功能并等待由于起搏或所感测到的心房或心室去极化的发生引起的下一个连续的中断。
刺激生成器84可借助输出电路传递复律或去纤颤冲击,该输出电路确定是传递单相还是双相脉冲、外壳电极58用作阴极还是阳极、以及传递复律或去纤颤脉冲涉及哪些电极。此功能可由刺激生成器84的一个或多个开关或开关模块提供。
遥测模块88包括任何合适的硬件、固件、软件或其任意组合,从而与例如编程器24(图1)的另一设备通信。在处理器80的控制下,遥测模块88可在天线(可以是内部天线和/或外部天线)的帮助下从编程器24接收下行链路遥测并将上行链路遥测送至编程器24。处理器80可例如经由地址/数据总线提供将被上行链路至编程器24的数据以及遥测模块88中的遥测电路的控制信号。在一些示例中,遥测模块88可经由多路复用器将所接收的数据提供至处理器80。
在一些示例中,处理器80可将由感测模块86中的心房和心室感测放大电路产生的心房和心室心脏信号(如,心电图信号)传输至编程器24。编程器24可询查IMD 16来接收心脏信号。处理器80可将心脏信号存储在存储器82中、并从存储器82中获得所存储的心脏信号。处理器80还可产生并存储指示感测模块86检测的不同心脏症状的标记代码,并将这些标记代码传输至编程器24。具有标记通道能力的示例性起搏器在1983年2月15日授权的名为“MARKER CHANNEL TELEMETRY SYSTEM FOR A MEDICAL DEVICE”的Markowitz的美国专利No.4,374,382中有所描述,该专利通过援引全部并入此。
IMKD 16的各组件耦合至电源90,电源90可包括可充电和不可充电电池。可选择不可充电电池来维持数年,但是可再充电电池可从外部设备例如以每日或每周地电感性地充电。
图5是示例性编程器24的框图。如图5所示,编程器24包括处理器100、存储器102、用户界面104、遥测模块106、以及电源108。编程器24可以是带有用于编程IMD 16的专用软件的专用硬件设备。可选地,编程器24可以是运行能使编程器24对于IMD 16编程的应用的现成计算设备。
用户可使用编程器24选择治疗程序(例如各组刺激参数)、生成新的治疗程序、通过个别或全局调整修改治疗程序、或将新程序传输至医疗设备,例如IMD 16(图1)。临床医生经由用户界面104与编程器24交互,该界面104可包括向用户显示图形用户接口的显示器以及从用户处接收输入的键盘或另一机构。
处理器100可采用一个或多个微处理器、DSP、ASIC、FPGA、可编程逻辑电路等的形式,并且此处分配给处理器100的功能可被实现为硬件、固件、软件或其任意组合。存储器102可存储指令。例如,只读存储器(ROM)存储计算机指令。处理器80被配置为从ROM处获取计算机指令,然后处理器80执行该计算机指令。处理器80的计算机指令的执行可导致处理器100来生成控制信号至IMD 16的组件或电和/或机械地耦合至IMD 16的组件。处理器80可提供归属于此处编程器24的功能、并提供由处理器100所使用的信息来提供归属于此处编程器24的功能。存储器102可包括任何固定或可移动的磁、光或电学介质,例如RAM、ROM、CD-ROM、硬盘或软磁盘、EEPROM等。存储器102也可包括可用于提供存储器容量的存储器升级或增加的可移动存储器部分。可移动存储器还可允许将患者数据容易地转移到另一计算设备,或者在使用编程器24对另一患者的进行治疗编程之前去除该患者数据。存储器102也可存储控制IMD 16的治疗传递的信息,例如刺激参数值。
编程器24可无线地与IMD 16通信,例如使用RF通信或近侧电感性交互。该无线通信可能通过使用遥测模块102实现,遥测模块106可耦合于内部天线或外部天线。耦合至编程器24的外部天线可对应于可被置于心脏12上的编程头,如参考图1所描述的。遥测模块102可类似于IMD 16的遥测模块88(图4)。
遥测模块102也可配置成经由无线通信技术与另一计算设备通信,或通过有线连接直接通信。可利用以促成编程器24和另一计算设备之间的通信的本地无线通信技术的示例,包括根据802.11或蓝牙规范集的RF通信、红外通信,例如根据IrDA标准、或其它标准或专用遥测协议。以此方式,其他外部设备能够与编程器24通信,而无需建立安全的无线连接。
电源108将操作功率传送到编程器24的组件。电源108可包括电池以及产生操作功率的功率生成电路。在一些实施例中,电池可以是可充电的以允许延长的操作。充电可通过将电源108电耦合到连接至交流(AC)出口的支架或插头来完成。另外或可选地,充电可通过外部充电器与编程器24内的电感充电线圈之间的近侧电感性交互来完成。在其他实施例中,可使用常规电池(例如,镉镍或锂离子电池)。此外,编程器24可直接将交流出口耦合至电源编程器24。电源104可包括监测保留在电池内的电力的电路。以此方式,用户界面104可提供当前电池水平指示符、或者当需要更换电池或对电池充电时的低电池水平指示符。在一些情况下,电源108能够估计使用当前电池剩余的操作时间。
再次参看图4,IMD 16的处理器80,基于经由感测模块86监测的心脏12的电心动描记活动,可检测快速性心律失常症状,诸如心室纤颤、心室心动过速、快速心室快速性心律失常症状、或NST症状。例如,感测模块86,在电极40,42,44,46,48,50,58,62,64,和66(如图1-2中所示)的至少一些的帮助下,可产生表示电心动描记活动的心电图(ECG)或电描记图(EGM)信号。可选地,感测模块86可被耦合至与传递电刺激至心脏12的刺激电极不同的感测电极(如图1-3中所示)、且可被耦合至不同于引线18、20、22的一个或多个引线(如图1-2中所示)。ECG信号可表示心脏12的去极化。
例如,如上所述,在一些示例中,处理器80,通过检测阈值数量的快速性心律失常事件(如,具有小于或等于阈值的R-R或P-P间隔),可标识快速性心律失常症状的存在。在一些示例中,处理器80还可通过检测心脏信号的R-波之间的可变耦合间隔来标识快速性心律失常症状的存在。
本公开中描述的技术,包括归于IMD 16、编程器24、或各构成组件的那些技术,可至少部分地以硬件、软件、固件或其任意组合来实现。例如,这些技术的各方面可实现在包括一个或多个微处理器、DSP、ASIC、FPGA或任何其他等效的集成或分立逻辑电路以及这些组件的任意组合的一个或多个处理器中,体现在诸如医生或患者的编程器、刺激器、图像处理设备或其他设备之类的编程器中。术语“处理器”或“处理电路”一般可以指单独或结合其他逻辑电路组合的任一前述逻辑电路、或者任何其他等效电路。
这些硬件、软件、固件可在同一设备或单独的设备内实现,以支持本公开中所描述的各种操作和功能。另外,任一所述单元、模块或组件可一起或者作为分立但可互操作的逻辑设备单独实现。将不同特征描绘为模块或单元旨在强调不同的功能方面,并且不一定暗示这些模块或单元必须通过单独的硬件或软件组件来实现。相反,与一个或多个模块或单元相关联的功能可由单独的硬件或软件组件执行,或者集成在共同或单独的硬件或软件组件内。
当以软件实现时,对于本公开中所描述的系统、设备和技术的功能可体现为诸如RAM、ROM、NVRAM、EEPROM、FLASH存储器、磁性数据存储介质、光学数据存储介质等计算机可读介质上的指令。可由一个或多个处理器执行这些指令以支持本公开中所描述的功能的一个或多个方面。
图6-50和相应文本中呈现的是在晶片上执行的一系列操作从而形成为晶片间互连以及气密密封来形成气密设备。下列的表1简短地汇总了相对于每一个附图的每一个操作。
参看图6,衬底300,也被称为晶片,被获得并被放置在位置上,来经受多个顺序的处理操作,其中一些可以是自动化的。衬底300一般包括硅晶体,通常被称为单晶硅或玻璃复合物。示例性玻璃复合物可包括硼硅玻璃(BSG),从位于德国、Elsoff的Plan Optik商业地可获得。衬底300包括前侧302a(第一侧或顶侧)和后侧302b(第二侧或底侧)。后侧302b被图示为水平地沿着x-轴,而顶侧302a被图示为沿y-轴比后侧302b垂直地更高并平行于后侧302b。在用于图案化前侧和后侧302a、b的准备中,前和后侧302a、b经受一系列操作。
硅衬底300的后侧302b被图示为已经经受了研磨和抛光操作,从而后侧302b可接收刻线,其标识晶片为特定批次晶片中的个别晶片。优选地,在研磨操作过程中从后侧302b上移除硅的约Δy(y2-y1),约为1.5mil;然而,本领域技术人员了解被移除的硅的量可被调节。例如,取决于经受研磨操作的后侧302n的最终期望特性,可移除增加量或减少量的硅。由位于日本的disco制造的研磨装置可被用于从后侧302b上研磨一部分硅。
在研磨操作完成后,然后衬底300可被装载在衬底移动器(也被称为舟皿)中,从而衬底可被移动到位用于清洁操作。该衬底移动器被配置为在清洁操作过程中持有并沿x-轴和/或y-轴方向移动衬底300。例如,在操作2,衬底300被放置在衬底移动器中,衬底移动器然后被置于清洁装置中。清洁装置包括清洁喷雾301,其中如图7中所示复合物(多个)被喷洒在衬底300上,同时衬底300被围绕x-轴旋转。清洁装置从位于明尼苏达Chaska的FSI装置商业地可获得,商标名Mercury。过氧化氢(H2O2)/氢氧化铵(NH4OH)和/或H2O2/盐酸(HCl)可被用作用清洁喷雾301或清洁喷雾301的一部分,用于清洁衬底300。一旦特定物质,有机、离子的、和/或金属杂质被从衬底300的表面302a、b移除,则认为衬底300被充分地清洁。
在衬底300被清洁后,阻挡层308a(或诸如氧化物、氮化物等的热氧化物)被形成在衬底300上,如图8中所示,从而保护硅300,同时在后侧302b上放置刻线。可理解的是,可使用其他阻挡材料,诸如Silox、TEOS、氮化硅、或各种聚酰亚胺。为了形成阻挡层308a,衬底300被放置在诸如被配置为耐受高温的氮化硅舟皿之类的衬底移动器中。碳化硅舟皿,携载着衬底300,被推入卧式扩散炉,此时气体(氧气O2(4slm)和/或H2)被引入热处理腔中。扩散炉的热处理腔处于大气压力和约10000C的温度下。扩散炉从位于CA、Sonora的MRL企业商业地可获得。在一部分硅已经被氧化来形成阻挡层308a之后,气体(氧气O2(4slm)和/或H2)被关掉且氮化硅舟皿从热处理腔中被移出。阻挡层308a,也被称为热氧化物层,诸如二氧化硅,被形成在衬底300的顶侧302a和后侧302b上,从而在经受操作4的刻线时保护晶片。如图所示,阻挡层308a具有约5000埃的厚度。阻挡层308a的厚度可在约4,000到约30,000范围内。在一个或多个实施例中,阻挡层308a的厚度优选地约为15000埃
在操作4,硅衬底300一般在后侧302b上接收刻线306,如图9中所示。对衬底300进行刻线允许晶片在剩余的处理步骤中被追踪。刻线306优选地被用在后侧302b上避免颗粒和污染物在例如衬底步骤过程中被收集在经刻线的区域中,此后在之后的处理步骤过程中被扩散至晶片的其他区域。此外,简短地参看图45,由于第一衬底300a的前侧402被结合至第二衬底300b的前侧402,可视地检测每一个刻线306的唯一方法是确保刻线306被放置在每一个晶片的后侧302b上。
在如图10中所示的操作5,通过剥离操作,阻挡层308被从衬底300移除。为了将阻挡层308从衬底300移除,衬底300被放置在诸如舟皿之类的另一个衬底移动器中。舟皿稳固地持有并移动衬底300通过剥离器的容器,直到阻挡层308被移除,且硅被暴露在前和后侧302a、b的表面处。例如,舟皿可被放置在诸如氢氟酸(HF)之类的剥离溶剂的容器中达约一分钟来移除阻挡层308。
在如图11中所示的操作6处,衬底300的第一和第二侧302a、b通过湿法化学清洁操作被清洁,诸如之前相对操作2而描述的那样。包括H2O2/NH4OH和/或H2O2/HCl的清洁喷雾301被用于清洁第一和第二侧302a、b。衬底300然后被从舟皿移除并被放置为氮化硅移动器或舟皿中,准备用于将衬底300移动至扩散炉的热处理腔中。
在如图12中所示的操作7,第一和第二阻挡层308b(也被称为热氧化物层)被形成在衬底300的第一和第二侧302a、b上、通过如上文所述的湿法热氧化处理,第一和第二阻挡层308b在第一和第二侧302a、b上生长。湿法热氧化在例如12000C执行达约三小时,此时O2和H2被持续地引入扩散炉的热腔中。如图12中所示,阻挡层308b具有约15,000的厚度。
在操作8,如图13中所示,过量的光致抗蚀剂310a被引入或放置在阻挡层308b上。例如,可使用被称为旋涂的技术来在衬底300的第一侧302a上形成光致抗蚀剂310a的薄的均匀层。衬底300被固定在旋涂器内,旋涂器然后被以高速旋转从而通过离心力涂布液体。旋转被继续,同时过量光致抗蚀剂310a被旋出衬底300的边缘且直到实现了期望厚度的膜。光致抗蚀剂310a的厚度可取决于光致抗蚀剂310a的速度、光致抗蚀剂310a的挥发性、和/或在旋涂器中旋转衬底300的角速度。光致抗蚀剂310a厚度标称约为1.5微米。
在这个示例中,采用了正性光致抗蚀剂310a。示例性正性光致抗蚀剂是从位于Philadelphia,PA的Rohm和Hass(且现在是陶氏化学公司的全资子公司)商业可获得的SPR3010光致抗蚀剂。
在如图14所示的操作9,掩模312a被放置在正性光致抗蚀剂310a上并在其上被对齐。被手动地装载至其固定装置(fixture)中的掩模312a,包括阻挡或覆盖光致抗蚀剂310a的预定区域的连续暗区和允许光致抗蚀剂310a暴露于通过UV光孔(未示出)的紫外(UV)光316的孔314。UV光316接触光致抗蚀剂310b,此举使得光致抗蚀剂310b可溶于水性显影液。示例性水性显影液可以是MF26A显影剂,可从罗门哈斯(Rohmand Hass)商业地获得。在如图15中所示的操作10,显影液(未示出)被引入在被暴露于UV光316的光致抗蚀剂310b之上。例如,通过上述的旋涂技术,显影液被旋转喷在衬底300上。在显影液洗刷暴露于UV光316的光致抗蚀剂310a之后,被暴露的光致抗蚀剂310b被移除。特定地,当衬底300在旋涂器中连续地围绕y-轴(这是相对地面的垂直轴)旋转,由于施加至衬底300的离心力,被暴露的光致抗蚀剂310b旋落。然后衬底300被移动至蚀刻处理腔,被称为Rainbow模型蚀刻器,从位于加州Fremont的Lam Research公司商业地可获得。
在如图16中所示的操作11,通过等离子体活性离子蚀刻(RIE),一部分的阻挡层308被蚀刻掉,藉此形成通孔318。通孔是平板开口或凹入。通孔318一般直径约5到20微米且具有约0.1到1微米的高度。干法蚀刻涉及施加或引入等离子体至衬底300的表面,从而等离子体撞击并蚀刻衬底300的表面。等离子体包括诸如四氟化碳(CF4)之类的反应气体添加诸如氮、氩、和/或氦或其他合适的气体之类的离子化气体。
在如图17中所示的操作12,通过使用离子化氧等离子体剥离操作直到被暴露的光致抗蚀剂310b被移除,剩余的光致抗蚀剂310b被从衬底300的顶部表面302a剥离。氧等离子体撞击并蚀刻掉有机材料(如,光致抗蚀剂)但不影响无机材料(如,硅等)。剥离处理腔,在低压真空(如,1.5托)下,持续地将被蚀刻下来的挥发性颗粒移除。剥离装置中的剥离处理腔从位于加州Richmond的Matrix可商业地获得。在光致抗蚀剂310b已经被移除后,分别通过第一、和第二表面327a-b形成通孔318。
此后,衬底300被移动至衬底300移动器,从而衬底300可经受又一个清洁操作。在如图18所示的操作13,使用湿法化学剂317来清洁衬底300,类似于相对操作2和6所描述地那样。操作13的示例性清洁化合物包括H2O2/NH4OH和/或H2O2/HCl。
在如图19中所示的操作14,阻挡层308c被形成在衬底300的第一和第二侧302a、b上,如上文相对操作3和7所描述地,区别在于处理条件不同。为了说明,干法热氧化在例如1,0000C执行达约三十分钟,此时O2和H2被持续地引入扩散炉的热腔中。阻挡层308c、d相对较薄且具有约2,000的厚度。一般而言,阻挡层308c用于增加通孔层308d的厚度。
图20-24中所示的,任选的操作15-19,在衬底300的后侧302b中形成通孔324、314,从而形成对齐特征来在第一和第二晶片之间的结合操作前,将第一和第二晶片(也被分别称为第一和第二衬底300a、b)对齐在一起。在如图20中所示的操作15,通过旋涂,光致抗蚀剂310c被施加在衬底300的后侧302b。示例性正性光致抗蚀剂是从位于Philadelphia,PA的Rohm and Hass(且是陶氏化学公司的全资子公司)商业可获得的SPR3010光致抗蚀剂。衬底300被放置在热板上,依靠热板,衬底300被暴露于较短的软烤来硬化光致抗蚀剂310c并逐出挥发性组分。
软烤可发生在约95摄氏度达约60秒。软烤有助于照片成像且从光致抗蚀剂310c移除任何残余的溶剂。
在如图21中所示的操作16,掩模312b被放置在光致抗蚀剂310c上。类似于操作9,光致抗蚀剂310c的区域通过掩模312b被暴露从而允许UV光穿过掩模312b中的孔。在如图22中所示的操作17,在旋涂器中,通过衬底300的旋转,显影剂移除被暴露的光致抗蚀剂310c。在被暴露的光致抗蚀剂310c被移除后,在光致抗蚀剂310c中形成通孔314、324。在如图23中所示的操作18,在Lam 4520干法蚀刻器中,后侧302b被干法蚀刻。具有四氟化碳(CF4)的等离子体被用于蚀刻热氧化物308d。具有三氟化氮(NF3)的等离子体被用于蚀刻热氧化物308d。在图24中所示的操作19,通过如上所述的氧化物等离子体RIE剥离操作,光致抗蚀剂310c从热氧化物308d被移除。
在如图25中所示的操作20,导电板320(也被称为导电板、可焊接板、或金属叠层),包括粘合材料,通过金属和/或合金沉积被形成。金属和/或合金沉积在通孔318中并沿热氧化物308d的表面发生。粘合材料可以是多层的且包括过渡金属元素,诸如铬和/或钛(Ti),还有任选的阻挡金属,诸如铂(Pt)和/或镍(Ni),和诸如金之类的可湿性层。
可采用各种方法来将金属或合金沉积到通孔318中。溅射沉积是可被使用的示例性方法。例如,诸如Ti之类的第一导电材料322a可被沉积在通孔318中。诸如Ti之类的第一导电材料322a可具有约300的厚度。
由多于一层导电材料形成的典型的金属叠层,可以是Ti/Au/Ti(300/5000/300)或Cr/Au/Ti(300/5000/300)。在一个或多个实施例中,粘合层总是被放置在阻挡材料308d上。典型的粘合层可以是Ti或Cr,因为金与下层材料无法良好粘合。此后,金被放置在粘合层上。最终,Ti层被放置在第二层的顶部,从而后续氧化层将粘贴或粘合至金属叠层。一般而言,氧化物不与Au良好地粘贴或粘合。此后,在AuSn被期望凝聚之处,顶部钛层被移除,但是在期望氧化物继续覆盖的区域中,Ti留存,如附图中所示。
诸如铬(Cr)之类的第三导电材料322c可被引入在第二导电材料322b上。例如,在第二导电材料322b上,Cr可被沉积至约300的厚度。在一个或多个实施例中,通过其中采用氩的溅射,Cr被沉积在第二导电材料322b上。溅射处理可在高达300℃的温度下在晶片上发生。在溅射开始前,真空腔压力一般被泵浦至1x10-7托,且在氩处理过程中,压力一般是3到10毫托。在一个或多个其他实施例中,第二导电材料322b(如,金等)的更薄的层可被形成。例如,金材料可以约1000厚。在一个或多个其他实施例中,第一、第二、和第三导电材料322a-c可各自包括钛、铂、和钛(Ti/Pt/Ti)材料。在一个或多个实施例中,优选的厚度为约300Ti、约2000Pt、和300Ti。
在一个或多个其他实施例中,板320(也被称为导电板、可焊接板、或金属叠层)各自可采用矾化镍(NiV)/Au/Ti作为第三导电材料322c、第二导电材料322b、第一导电材料322a。
在一个或多个其他实施例中,可理解的是,板320可由四个或更多个导电材料形成。例如,板320可包括Ti/Pt/Au/Ti,其中第四导电材料(图25中未示出)是沉积在第三导电材料322c上的Ti。第三导电材料322c是Ni。第二导电材料322b是Au。第一导电材料322a是Ti。
在一个或多个其他实施例中,可理解的是,板320可由四个或更多个导电材料形成。例如,板320可包括Ti/Ni/Au/Ti,其中第四导电材料(图25中未示出)是沉积在第三导电材料322c上的Ti。第三导电材料322c是Ni。第二导电材料322b是Au。第一导电材料322a是Ti。
在如图26中所示的操作21中,使用旋涂操作,光致抗蚀剂310d被施加至第三导电金属322c。例如,正性光致抗蚀剂被旋涂在后侧302b上。示例性正性光致抗蚀剂是从Rohmand Hass商业可获得的SPR3010抗蚀剂。
使用短时软烤来硬化光致抗蚀剂310d并从光致抗蚀剂中逐出挥发性组分。软烤可发生在约95摄氏度达约60秒。
在如图27中所示的操作22,掩模312c部分地覆盖光致抗蚀剂310d。然后光致抗蚀剂310d被暴露于UV光316,藉此使得该光致抗蚀剂可溶于显影液。用于该光致抗蚀剂310d的特定波长的UV光316通过孔(多个)接触光致抗蚀剂310d。
在图28所示的操作23,暴露于UV光316的光致抗蚀剂310d然后通过使用水性显影剂被移除。如上文所述,显影液在光致抗蚀剂310d上冲刷,这有助于将被暴露的光致抗蚀剂310d从第三导电金属322c上释放掉。
在图29所示的操作24,第一、第二、和第三导电材料322a-c(如,Cr/Au/Ti金属)被蚀刻。氯气被引入Lam蚀刻器的反应腔且之后被离子化为等离子体。然后,等离子体蚀刻钛。反之,使用湿法蚀刻处理来蚀刻第一和第二导电金属322a、b。晶片被放置在舟皿中,且然后,对于被蚀刻的特定材料,被放置在湿法蚀刻剂中。例如,湿法蚀刻碘化钾(KI)和/或碘(I2)被用在第二导电材料322b上。特定地,晶片被置于KI或I2的容器中。在第二导电材料322b被充分地蚀刻后,晶片然后在去离子化的水中冲洗。然后晶片被移动至下一个蚀刻操作。例如,晶片然后被移动至蚀刻剂。使用标准的Cr蚀刻剂。例如,铬蚀刻可包括硝酸高铈铵和硝酸的混合物。示例性铬蚀刻可从Rhode Island、North Kingstown的Fujifilm Electronic Materials商业可获得。
在图30中所示的操作25,通过例如,氧化物等离子体RIE剥离操作,从第三导电材料322c移除光致抗蚀剂310d。
在图31中所示的操作26,使用化学蒸镀(CVD)来在阻挡材料308d和光致抗蚀剂310d上沉积绝缘材料326(如,氧化物、氮化物等),从而在例如,第二导电材料322b和导电材料340(之后被用于形成晶片间互连)(如,金锡)之间创建阻挡件。绝缘材料326位于各处,除了之后在操作30所创建的通孔中。
在图32中所示的操作27,光致抗蚀剂310e被施加至绝缘材料326(也被称为阻挡材料)。例如,使用旋涂器,正性光致抗蚀剂310e被旋涂在顶部侧302b上。示例性正性光致抗蚀剂是从位于Philadelphia,PA的Rohm和Hass商业可获得的SPR3010光致抗蚀剂。使用短时软烤来硬化光致抗蚀剂310e并逐出挥发性组分。在如图33中所示的操作28,掩模312d被放置在光致抗蚀剂310e上,这允许光致抗蚀剂310e的一部分通过掩模312d暴露于UV光316。然后,被暴露的光致抗蚀剂310e可溶于显影液。在图34中所示的操作29,通过在所暴露的光致抗蚀剂310e上放置基于水性的显影剂来移除所暴露的光致抗蚀剂310e。在图35中所示的操作30,使用包括CF4的等离子体反应离子从所暴露的区域中蚀刻掉绝缘材料326(如,氧化物、氮化物等)。在图36中所示的操作31,使用氧等离子体RIE剥离来移除所暴露的光致抗蚀剂310e。在图37中所示的操作32,通过其中等离子体包括氯的等离子体蚀刻处理,从第二导电材料322b,移除诸如钛之类的第三导电材料322c的一部分。
在图38中所示的操作33,在绝缘材料326的顶部表面和第二导电材料322b(如,金)的一部分上沉积典型厚度为0.5微米的诸如金锡(AuSn)(按重量80%/20%)合金之类的导电材料340a。特定地,AuSn可被溅射沉积或电镀为约5000的厚度。在一个或多个其他实施例中,可使用不同厚度的AuSn。在一个或多个实施例中,可使用另一个合金,诸如AuSn 78%/22%。
在图39-43中所示的操作34-38涉及光刻处理。在图39所示的操作34,光致抗蚀剂310f被施加在导电材料340a上。例如,正性光致抗蚀剂310f被旋涂在导电材料340a上。使用短时软烤来硬化光致抗蚀剂并逐出挥发性组分。在如图40中所示的操作35,掩模312e被放置在光致抗蚀剂310f上,这允许光致抗蚀剂310f的一部分通过掩模312e暴露于UV光。然后,被暴露的光致抗蚀剂310f可溶于显影液。在图41中所示的操作36,通过在所暴露的光致抗蚀剂310f上放置基于水性的显影剂来移除所暴露的光致抗蚀剂310f。在图42所示的操作37,从所暴露的区域蚀刻掉导电材料340a(如,AuSn)。例如,可使用溴化氢(HBr)的等离子体蚀刻蚀刻掉Sn,而使用湿性蚀刻KI或I2蚀刻Au。可使用HBr等离子体进一步蚀刻掉残余的锡。示例性等离子体蚀刻工具是从位于Freemont CA的Lam Research商业可获得的Lam 9400TCP蚀刻器。
在如图43中所示的操作38,使用氧化物等离子体RIE剥离移除所暴露的光致抗蚀剂310f,接着是常规的溶剂抗蚀剂剥离操作。
在图44所示的操作39,使用化学机械抛光(CMP)来抛光绝缘材料326的顶部表面,其被部分地从阻挡材料308d的顶部表面移除。在完成CMP后,形成了完成后的晶片400。完成后的晶片400具有前侧402(顶部侧)和底侧404。图44示出在导电材料340a经受回流处理前,晶片的一个实施例的细节。回流处理是指完成后的晶片400、402(也被称为第一和第二衬底)被暴露于热,直到第一和第二导电材料340a的至少一部分回流并形成互连340b(也被称为导电板)。
图44a示出在导电材料340a经受回流处理后从而形成导电板340b,晶片的一个实施例的细节。
板开口、AuSn直径和AuSn厚度、以及阻挡材料308d(如,玻璃)厚度直径的关系可相对图83被示出,且被表达如下。
Vtotal:全部焊料体积
V1/2:在每一个板上的焊料体积
rpad:板开口的半径
rmetal:AuSn沉积的半径
Hmetal:AuSn沉积的厚度
Hglass:顶部玻璃的厚度
B:突起因子
板开口的半径(rpad)(图示在图36的第三导电材料322c中)从导电板的中心延伸至第二导电材料322c(如,Au或Pt)的端部,且rmetal从导电板的中心延伸至导电材料340a(如,AuSn)的端部。尽管上述所列等式可获得期望的AuSn体积、板尺寸、和互联间隙,还可写出其他等式来表达这些关系。
导电材料340a的高度(H340a)在从约0.25微米到约1.0微米的范围内。更优选地,H340a具有0.5微米的高度。当加上导电材料322a、322b、322c、和326的高度,H340a必须小于通孔高度(Hvia),优选为1.5微米。参看图44a,H1的高度是1.5微米而H2的高度是0.2微米。全部高度Htotal是H1+H2,等于1.7微米。Hgap是H340a(也被称为Hmetal)和阻挡材料308d的顶部表面327之间的高度。如图43中所示,在回流处理后,当没有配对衬底地被回流时,导电板340c,基本成为球状,且具有垂直地高于H340a的高度Hpad。优选地,Hpad从约0.5微米到约2微米范围内。优选地,Hpad具有1.75微米的高度。取决于阻挡材料的去湿性质,所得的形状可不是球状而是拱顶形的。图41(不带配对晶片地示出),例如,可在回流处理后,在第一和第二衬底之间产生拱顶形互连。
在如图45中所示的操作40,在从位于的Tempe,Arizona的EV公司商业可获得的EVG 500系列装置的晶片结合腔中形成晶片间结合(也被称为衬底300a与沉积300b间结合)。晶片结合腔被设置为约200摄氏度温度,且在大气压力下操作从而形成晶片间结合。一般而言,晶片间结合的形成可花费约60分钟到约120分钟。
如图45的晶片间结合500所示,完成的晶片400可被接合或结合至另一个完成的晶片420。在一个实施例中,晶片420是晶片400的镜像图像。
完成的晶片400的前侧402被对齐并结合至完成的晶片420的前侧402。完成的晶片420可与完成的晶片400一样或不同。例如,完成的晶片420不同于完成的晶片400之处在于,完成的晶片402没有通孔314b和318。结合至第二衬底420的第一衬底400可以是玻璃间结合、玻璃-硅间结合、硅间结合、硅兰宝石间、兰宝石间、和/或玻璃兰宝石间。玻璃间结合、玻璃-硅间结合、或硅间结合可在整个晶片上形成,除了包含板结构的较小的凹入区域。
在图46中所示的操作41,结合在完成的晶片400、402的前面侧402之间的界面处开始发生。在完成的晶片400、402之间形成的结合发生在基本低于250℃的温度下。
在图47中所示的操作42,导电材料340a(如,AuSn)经受回流处理来在从位于Downey,California的SST国际商业可获得的诸如SST型号3130之类的真空压力炉的腔中形成经回流的导电材料340b。导电材料340a一般可在约305℃的温度和N2气氛下被回流。腔内的压力优选地是标准大气压力。在腔内温度开始回到常规大气温度和/或压力时,导电材料340b固化。
在图48中所示的操作43,通过蚀刻处理,在衬底300中形成通孔328、330。例如,可使用湿法蚀刻,其包括氢氧化四甲铵(TMAH)。通过有线沿硅的晶格蚀刻的TMAH,通孔328、330被形成为基本三角形或沟槽。通过沿硅的晶格蚀刻,实现了倾斜的通孔328、330。在图49所示的操作44,阻挡材料308d被从衬底300剥离。
以下的表格1提供了被用于如每个附图随附的文本中所述那样形成晶片间互连和/或密封的处理操作的简短描述。
表格1每一个操作的简短描述
操作号 | 图 | 操作 |
1 | 6 | 研磨衬底的后侧 |
2 | 7 | 清洁衬底 |
3 | 8 | 在衬底上形成阻挡件 |
4 | 9 | 在衬底的后侧刻线 |
5 | 10 | 从衬底移除阻挡件 |
6 | 11 | 清洁衬底 |
7 | 12 | 在衬底上形成热氧化物 |
8 | 13 | 在热氧化物上沉积光致抗蚀剂 |
9 | 14 | 在光致抗蚀剂上放置掩模 |
10 | 15 | 移除被暴露的光致抗蚀剂 |
11 | 16 | 干法蚀刻热氧化物 |
12 | 17 | 移除剩余的光致抗蚀剂 |
13 | 18 | 清洁衬底 |
14 | 19 | 在衬底上形成热氧化物 |
15 | 20 | 施加光致抗蚀剂至在衬底的后侧 |
16 | 21 | 在光致抗蚀剂上放置掩模 |
17 | 22 | 移除所暴露的光致抗蚀剂 |
18 | 23 | 干法蚀刻衬底的后侧来形成通孔 |
19 | 24 | 移除抗蚀剂 |
20 | 25 | 在热氧化物上形成粘合或阻挡材料 |
21 | 26 | 在阻挡材料上沉积光致抗蚀剂 |
22 | 27 | 在光致抗蚀剂上放置掩模 |
23 | 28 | 移除暴露的光致抗蚀剂 |
24 | 29 | 蚀刻阻挡材料 |
25 | 30 | 从阻挡材料移除光致抗蚀剂 |
26 | 31 | 在阻挡材料上沉积氧化物 |
27 | 32 | 在氧化物材料上沉积光致抗蚀剂 |
28 | 33 | 在光致抗蚀剂上放置掩模 |
29 | 34 | 移除所暴露的光致抗蚀剂 |
30 | 35 | 蚀刻氧化物 |
31 | 36 | 移除光致抗蚀剂 |
32 | 37 | 移除钛 |
33 | 38 | 沉积导电材料来形成导电板 |
34 | 39 | 向导电材料施加光致抗蚀剂 |
35 | 40 | 通过掩模暴露光致抗蚀剂 |
36 | 41 | 移除所暴露的光致抗蚀剂 |
37 | 42 | 蚀刻导电材料 |
38 | 43 | 从导电板移除光致抗蚀剂 |
39 | 44 | 抛光顶部表面 |
40 | 45 | 耦合第一和第二衬底 |
41 | 46 | 稳定化结合 |
42 | 47 | 回流导电板中的导电材料 |
43 | 48 | 在衬底中蚀刻通孔 |
44 | 49 | 移除热氧化物 |
如下所呈现地表格2,提供了关于通孔、和导电板的高度、半径、和体积测量的实验数据。表格2中所提供的测量以微米为单位。例如,高度和半径为微米单位,而体积是立方微米。
图50是形成晶片间互连和/或密封的流程图。在框600,第一通孔形成在第一衬底的第一侧中。在框602,第一导电板形成在第一通孔中,以使第一导电板的被暴露的顶部表面低于第一通孔的顶部表面。在框604,第二通孔形成在第二衬底的第一侧中。在框606,第二导电板形成在第二通孔中,以使第二导电板的被暴露的顶部表面低于第二通孔的顶部表面。在框608,回流过程形成互连(多个)和/或密封(多个)。此处公开的处理显著简化了抛光处理。例如,相对于操作39的CMP描述所讨论的抛光处理,仅使得一个材料,氧化物或氮化物,经受抛光。本公开的CMP处理一般在不需要将CMP施加至导电材料(如,金属、合金)的情况下发生。反之,常规方法一般要求CMP被施加至氧化物和金属。此外,本公开还允许需要电连接指出的电连接,且没有必要添加“虚拟”连接。例如,为了确保CMP抛光被均匀地施加在整个表面上,常规处理需要数量众多的导电板均匀地分布在晶片表面。实质上,额外的导电板起到加载作用来帮助CMP,但不贡献于电连接。
在一个或多个实施例中,导电板或可焊接板可以是钛上的金或铬上的金。下层的钛或铬层(多个)仅需要足够厚来提供良好粘合。例如,钛或铬层(多个)应该处于的数量级。优选地,钛的范围应该是约100埃到约优选地,钛的范围应该是约200埃到约将在金上覆盖有玻璃的区域中采用钛,从而改进玻璃与板间的粘合。
在涉及可焊接板的又一个实施例中,金可被铂所替代。铂板不被焊料所消耗;因此,由于金的吸收,液相线没有变化。优选地,铂厚度可在约100到厚的范围内。更优选地,铂厚度可在约100到厚的范围内。对于在AuSn焊料下的板、和对于可在此处描述的焊料回流处理过程中AuSn可结合至其的板,均可用铂替代金。
导电板或凸点可加在通孔的中间。在另一个实施例中,导电板或凸点可位于一个晶片上,做出与位于配对晶片上的板的连接。
在一个或多个其他实施例中,诸如钯、铜、镍、铑、锡之类的其他金属可被用于在可焊接板中替代金。
在涉及可焊接板(Ti/Au/Ti或等效物)的一个或多个实施例中,并非如图51中所示将玻璃覆盖金属并定义导电板320周界,玻璃可被拉回(且板320大小和形状由板320本身的图案化所定义,如图52中所示。拉回是指绝缘材料326(如,玻璃)仍存在但不位于导电材料322a、b、和c的顶部。实际上,绝缘材料326变得不可见且阻挡材料308的一体部分如图52中所示。)。图52的实施例包括板320,由图案化和蚀刻过程所定义,当它从周围表面中去湿时不在玻璃下通过毛细吸附Au/Sn,因为在导电板320的顶部没有玻璃。.导电板320由导电材料322b和322c制成。导电材料322a不是必要的,因为不需要粘合层来使得氧化物326变粘。
图53-54是晶片间互连的又一个实施例的示意图。图53示出在回流处理前凸出与板间的结构。如图所示,晶片之一400包括含有两个导电材料322b、c的导电板346。导电板322bc可包括相比图示更少的导电材料。导电板322bc在导电材料340a中的通孔上方水平地延伸,但没有延伸超过导电材料340a的水平长度。在一个或多个其他实施例中,导电板322bc可仅略超过导电材料340a的接触面积的长度。
图54示出在回流过程完成后,凸点与板间结构。此处示出的晶片间互连可使用此处描述的任何导电材料。
图55-64涉及通过晶片间结合将两个晶片密封在一起并因此形成晶片间互连和/或气密金属密封的一个或多个其他实施例。图55是在衬底300的第一和第二侧302a、b已经经受清洁操作(诸如相对图1-2所描述的清洁操作)后的示意图。参看图56,然后使用例如,相对于操作8-14描述且相对于图13-19所示的处理,在衬底300上形成热氧化物308a。热氧化物308a、b可具有约例如1.5um的厚度。
图57是其中在热氧化物308a中形成通孔318的示意图。可通过很多不同操作形成通孔318。如上所述,操作15-19提供其中可形成通孔318的一个方法。
图58示出在通孔318中沉积的导电金属的示意图。可采用各种方法来将金属或合金沉积到通孔318中。例如,可使用溅射沉积。诸如Cr之类的第一导电材料322a可被溅射沉积在通孔318中。诸如Cr之类的第一导电材料322a可具有约300的厚度。此后,诸如Au或Pt之类的第二导电材料322b可被引入或沉积在第一导电材料322a上。如图58中所示,第二导电材料322b,诸如Au或Pt,可具有约5,000的厚度。
图59示出通过蚀刻金属板704的一部分形成的金属板704。本领域内技术人员了解,尽管可使用干法或湿法蚀刻处理来蚀刻金属板704,此处呈现的实施例使用了湿法蚀刻剂,如,碘化钾,后跟用BCl3的干法蚀刻。在通过蚀刻将导电层322a、b的一部分被移除后,形成包括第一和第二导电层322a、b的金属板704。
如图60中所示,诸如AuSn之类的第三导电金属702可被引入在第二导电材料322b之上。AuSn在第二导电材料322b之上可被沉积(如,溅射沉积等)至约5000的厚度。在一个或多个实施例中,通过其中采用氩的溅射,AuSn被沉积在第二导电材料322b上。溅射处理可在高达300℃的温度下在晶片上发生。在溅射开始前,真空腔压力一般被泵浦至1x10-7托,且在氩处理过程中,压力一般是3到10毫托。在一个或多个其他实施例中,第二导电材料322b(如,金、Pt等)的更薄的层可被形成。例如,金或Pt可以约1000厚。在一个或多个其他实施例中,第一、第二、和第三导电材料322a-b、702可各自包括钛、铂、和AuSn(Ti/Pt/AuSn)材料。在一个或多个其他实施例中,第一、第二、和第三导电材料322a-b、702可各自包括钛、铂、和AuSn(Ti/Au/AuSn)材料。在一个或多个实施例中,优选的厚度为约300Ti、约5000Au、和300Ti。
图61示出其中第三导电金属702的一部分718经受移除处理的示意图。可通过各种操作执行AuSn的移除。例如,可在其中期望移除一部分718AuSn的区域中放置光致抗蚀剂材料。此后,光致抗蚀剂连同AuSn一起可经受蚀刻处理,如上文所述。例如,可使用溴化氢(HBr)的等离子体蚀刻蚀刻掉Sn,而使用湿性蚀刻KI或I2蚀刻Au。可使用HBr等离子体进一步蚀刻掉残余的锡。
在第三导电材料302的一部分718被移除后,图62示出如上文所述经受接触抛光操作的热氧化物层308a的顶部表面。
图63示出在经受回流处理从而在两个完成的晶片400、420之间形成低温结合前的凸点间结构722。图64示出在经受回流处理从而在两个完成的晶片400、420之间形成低温结合后的凸点间结构722。回流凸点间结构722的回流处理条件涉及使用约300到约310°C的腔温度达约3分钟到约10分钟。在经受回流处理后,在第一和第二完成的晶片400、420之间形成经回流的导电材料724。
图65-66示出在完成的晶片400、420之间形成低温结合的凸点与配对金属板间结构712。以与图56-64中所示的完成的晶片400、420相同或类似的方式形成完成的晶片400和420,不同之处在于,图65-66的完成的晶片400、420包括配对金属板712代替第一、第二、和第三导电材料322a、322b、702。特定地,完成的晶片之一400包括相对另一个完成的晶片420上的配对金属板712的具有AuSn的前侧402。相对的、配对金属712可以是任何可焊接的金属、金属合金、和/或金属叠层。金属叠层包括有效地与有源设备或无源设备相关联的一个或多个金属层。例如,配对金属712可以是Ti/Ni、Ti/Pt/Au、或Cr/Au。一般而言,配对金属可被形成为各种厚度。例如,Ti/Ni可约250/2000Ti/Pt/Au可约250/500/3000Cr/Au可约
凸点与配对金属板间结构712经受回流处理来形成由经回流的导电材料形成的低温互连726。回流处理使用在腔内约305°C的温度和惰性气氛。一般而言,回流处理可花费约3到约10分钟。一般而言,配对金属712不回流。当配合金属凝聚在相对表面上时,它仅是湿润了凸点。在回流处理后,图66示出在完成的晶片400、420之间的结合726。
图67-68涉及通过晶片间结合来将两个晶片密封在一起的一个或多个其他实施例。图67是在衬底300的第一和第二侧302a、b已经经受清洁操作(这允许热氧化物308a将在其上形成)后的示意图。相对图1-2描述了示例性清洁操作。例如,使用相对于操作8-14和相对于图13-19中所示的处理,可形成热氧化物308a。热氧化物308a、b具有约15k埃的厚度。
图68是其中在阻挡材料308a中形成通孔318的示意图。可通过很多不同操作形成通孔318。如上所述,操作15-19提供其中可形成通孔318的一个方法。
图69示出形成在阻挡材料308上以及形成在通孔318中的阻挡材料或热氧化物的薄层(如,2k埃)。
图70示出沉积在如图68中所示被形成的通孔318中的多层导电材料322a-c。可采用各种方法来将金属或合金沉积到通孔318中。例如,可使用溅射沉积。诸如Cr之类的第一导电材料322a可被溅射沉积在通孔318中。诸如Cr之类的第一导电材料322a可具有约300的厚度。此后,诸如Au或Pt之类的第二导电材料322b可被引入或沉积(如,溅射沉积等)在第一导电材料322a上。诸如Au或Pt之类的第二导电材料322b可具有约5,000的厚度。第三导电材料322c是具有高达或约500的厚度的Ti。
图71示出从热氧化物308a移除第一、第二、和第三导电材料322a-c的一部分,藉此留下板804。可使用各种方法来从热氧化物层308a移除第一、第二、和第三导电材料322a-c的一部分。图26-30和随附文本提供了其中移除第一、第二、和第三导电材料322a-c的一部分的一个方法。
图73示出阻挡层342的一部分被移除藉此暴露出第三导电材料322c的一部分。通过等离子体反应离子蚀刻(RIE),蚀刻掉阻挡层342的一部分,藉此形成通孔344。通孔344一般半径约5到20微米且具有约0.1到1微米的高度。干法蚀刻涉及施加或引入等离子体至阻挡层342的表面,从而等离子体撞击并蚀刻阻挡层342的表面。等离子体包括诸如四氟化碳(CF4)之类的反应气体添加诸如氮、氩、和/或氦或其他合适的气体之类的离子化气体。
通过使用离子化氧等离子体剥离操作直到被暴露的光致抗蚀剂被移除,将任何剩余的光致抗蚀剂(未示出)从阻挡层342的顶部表面被剥离。氧等离子体撞击并蚀刻掉有机材料(如,光致抗蚀剂)但不影响无机材料(如,金属等)。剥离处理腔,处于低压真空(如,1.5托),持续地将被蚀刻下来的挥发性颗粒移除。
图74示出从图33中所示的第二导电层322b的一部分移除的第三导电层322c(即,Ti)的一部分。可通过各种光刻处理移除第三导电层322c。
图39-43中所示的操作34-38,可被类似地应用于这个实施例中,来在其中从图72移除阻挡层342的区域下方移除第三导电材料322c(如,Ti)。例如,可使用溴化氢(HBr)的等离子体蚀刻蚀刻掉Ti,而可使用湿性蚀刻KI或I2蚀刻Au。用于蚀刻Ti的示例性等离子体蚀刻工具是从位于Freemont CA的Lam Research商业可获得的Lam 9400TCP蚀刻器。
图75示出在图74所示结构上沉积的金锡。在阻挡材料342和第二导电材料(如,Au或Pt)的顶部表面上,沉积诸如金锡(AuSn)(按重量80%/20%)之类的第四导电材料322d约0.5微米的厚度。特定地,AuSn可被溅射沉积或电镀为约5000的厚度。在一个或多个其他实施例中,可使用不同厚度的AuSn。在一个或多个实施例中,可使用另一个合金,诸如AuSn 78%/22%。
图76示出从图75中所示衬底移除金锡的一部分。例如,可使用溴化氢(HBr)的等离子体蚀刻蚀刻掉Sn,而使用湿性蚀刻KI或I2蚀刻Au。可使用HBr等离子体进一步蚀刻掉残余的锡。图77示出在经受通过CMP的轻度抛光操作后的图76的结构。
图78示出在第一和第二晶片400、420之间的晶片间结合。结合在完成的晶片400、402的前侧402之间的界面处开始出现。在基本低于250℃的温度处,在完成的晶片400、402之间形成结合。
导电材料340a(如,AuSn)经受回流处理来在从位于Downey,California的SST国际商业可获得的诸如SST型号3130之类的真空压力炉的腔中形成经回流的导电材料340b(图79)。导电材料340a一般可在约305℃的温度和N2气氛下被回流。腔内的压力可以是标准大气压力。在腔内温度开始回到常规大气温度和/或压力时,导电材料340b被形成。
图80-81和实施例78-79一样,不同之处在于,完成的晶片之一400包括之前所述的配对金属板712,替代导电材料340a。在回流后,晶片间互连如图81中所示。
图82示出使用此处所述的晶片间结合和互连技术来形成密封环的单个晶片900。导电材料(如,AuSn等)908被放置在热氧化物906上。例如,衬底902可以是硅或Borofloat 33,具有设置在其上的阻挡材料904。有源和无源电路910被示意性地示出。这个单个晶片900接着被晶片间结合至包含镜像成像的密封环的镜像成像的晶片,然后被回流来创建多个气密金属密封。对于可植入医疗设备,一般不使用铜,因为铜缺乏生物稳定性且在活体内不提供足够的密封。
图84为了能展示,在没有第二衬底的情况下,示出经回流的拱顶形凸点的SEM。在回流处理后,凸点对应于图62中所示的结构。如图所示,没有配对凸点或板。在回流处理以前存在的板已经被去湿且凝聚为拱顶形,具有比周围绝缘体308a高的最终高度。
尽管已经参看其中的特定实施例描述和图示了本发明的各实施例,其并不意在将本发明限制在这些图示实施例中。例如,可理解的是尽管提供了处理装置的特定实施例,可使用各种类型的处理装置。此外,本领域技术人员理解,尽管在此处描述的处理中使用了正性光致抗蚀剂,可替代正性光致抗蚀剂使用负性光致抗蚀剂。如果使用负性光致抗蚀剂,掩模应被配置为适应负性光致抗蚀剂。
此外,可使用可选的处理和流程来实现相同的终端结果。例如,剥离处理而不是沉积、图案化、和蚀刻,可被用于形成如图25和图38-43所示的结构。示例性剥离处理可见1986年1月14日授权给Fredericks等人的名为PHOTORESIST LIFT-OFF PROCESS FOR FABRICATING SEMICONDUCTORDEVICES的美国专利No.4,564,584,该专利的公开通过参考全部并入此。
相比常规方法,将低温气密晶片结合与电互连组合起来更易于且更便宜地实现。例如,由于每一个导电板被放置在凹入的腔内,导电板不干扰CMP。另外,由于焊接凸点没有被放置在晶片表面上,电互连可被设置在晶片上的任何位置。另外,没有必要添加“虚设”连接仅是为了在晶片上提供导电板的均匀的分布。
本发明提出了使用沉积的或以其他方式施加在要被连接的相对的板320上的AuSn或其他合金来创建晶片之间的电互连的各实施例。本发明还可被应用于凸点和板间配置,如图53-54中所示。并非如前所述的两个凸点进行聚结,单个凸点经受回流处理且然后与略位于配合晶片表面下的可焊接板做出接触,如图54中所示。还可能施加AuSn或其他形成连接的合金至仅其中一个表面,另一侧是板320,由在融化过程中形成其近球状时AuSn湿润至其的AuSn形成。
通过仅施加AuSn至一个晶片而非两个可减少凸点与板间配置的成本。如果该晶片在其表面上具有AuSn,凸点与板间配置还允许仅板晶片以不与晶片兼容的方式被处理。例如,氧等离子体清洁或氧化酸将氧化AuSn中的Sn并阻碍其后的球状或球形成。然而,这个配置不影响晶片上金板的可湿性。
以与上述双侧设计一样的方式,用单侧设计完成互连。将板对齐来将晶片放在一起,且晶片叠层被加热至AuSn的液相(2800C)之上。AuSn将从围绕可湿性板的玻璃环状物中去湿,且试图来形成球状或拱顶型来减少表面能量。AnSn体积不足以使得近球状AuSn接触到位于相对晶片上的可湿性(最可能是金)板并形成电接触。同样,没有液相或胶状物流被使用或被期望。这可在晶片结合热激活处理过程期间或之后被完成。
上文描述了80/20重量百分比的AuSn合金,且因其在没有流动(flux)情况下被沉积、图案化和被回流的能力,其良好地适于本申请。如上文所述,可从气氛中消除氧来排除加热过程中的氧化。AuSn系统中的其他合金,诸如AuSn 78/22,可被证明为有益的。附加的Sn内容允许液体AuSn消耗来自可湿性板的所溶解的金,而不提升液相温度。这从AuSn二元相图中可明显看出。AuSn 79/21和其他合金是可能的。
其他合适的合金可包括Au、Sn、Ag等的二元或更高阶的组合。选择具有期望液相温度和湿润性质的合金的选择可提供优选的结果。还应理解的是,尽管在很多实施例中使用Au,还可使用Pt替代Au。
此处描述的互连方法可被应用于被合适地对齐在叠层中的任意数量的晶片。单侧和双侧结合可甚至被混合在叠层中。可通过每次向之前处理的晶片子组添加一个或多个晶片连续地、或通过同时处理整个叠层,来完成单侧或双侧结合。
如此处所使用的,“具有”、“有”、“包括”、“含有”、“包含”、“由…组成”等被用于它们开放的形式,且一般意味着“包括但不限于”。可理解的是“基本包括”、“包括”、等被假设为“包含”等。因此,包括钛的第一导电材料包括基本包含、或包含钛的第一导电材料。
各种组件可采用此处描述的技术。传感器(如,无线传感器、有线传感器)、智能导线和/或微型治疗设备代表了可实现本发明的教导的组件类型。传感器、智能导线或微型化设备可或不可被保护并封在可植入心律转变除颤器(ICD)钛罐或壳中。传感器的示例可被相对于2011年2月15日授权、且转让给本发明的受让人的美国专利No.7,886,608,其内容通过参看全部并入此处。生物稳定开关的示例可被相对于2008年6月17日授权、且转让给本发明的受让人的美国专利No.7,388,459,其内容通过参看全部并入此处。血管内设备的示例可见参看2007年8月2日公开的,授予Dennis等人的美国预授权公开2007/0179552,授予Lund等人且转让给本发明的受让人的US2010/0305628,其内容通过援引全部并入此处。可植入神经刺激器的示例可被相对于2010年10月5日授权、且转让给本发明的受让人的美国专利No.7,809,443,其内容通过援引全部并入此处。可植入治疗剂传递系统的示例可见2010年10月28日公开的、授权给Sigg等人、且转让给本发明的受让人的美国预授权公开No.2010/0274221A1,其内容通过援引全部并入此处。
此处呈现的本发明的描述仅是本质上示例性的,且因此,不背离本发明要点的变化意在落在本发明的范围内。变化并不视为本发明精神和范围的背离。
Claims (16)
1.一种用于形成集成电路的方法,包括:
提供第一衬底;
形成第一导电材料,所述第一导电材料相对于所述第一衬底的表面是完全凹入的;
提供第二衬底;
形成第二导电材料,所述第二导电材料相对于所述第二衬底的表面是完全凹入的;且
回流所述第一和第二导电材料中的至少一个来在所述第一和第二衬底之间形成单个经回流的互连。
2.如权利要求1所述的方法,其特征在于,在所述第一和第二衬底之间形成气密密封。
3.如权利要求1所述的方法,其特征在于,所述单个经回流的互连是沙漏形的。
4.如权利要求1所述的方法,其特征在于,所述第一导电材料是向着直径上正相对的板凝聚的可回流板。
5.如权利要求4所述的方法,其特征在于,所述第一导电材料是金-锡(AuSn)。
6.如权利要求4所述的方法,其特征在于,所述第二导电材料是可回流板和不可回流板中的一个,所述不可回流板不回流。
7.如权利要求1所述的方法,其特征在于,所述第一导电材料不是铜。
8.如权利要求1所述的方法,其特征在于,所述第一衬底和第二衬底是如下中的一个:硅和玻璃、玻璃对玻璃、玻璃对硅、硅对硅、硅对兰宝石、兰宝石对兰宝石、和玻璃对兰宝石。
9.如权利要求5所述的方法,其特征在于,Au被呈现为AuSn的约80重量百分比的量,且Sn被呈现为AuSn的约20重量百分比的量。
10.如权利要求5所述的方法,其特征在于,Au被呈现为AuSn的约78重量百分比的量,且Sn被呈现为AuSn的约22重量百分比的量。
11.如权利要求5所述的方法,其特征在于,所述第一导电板和所述第二导电板中的一个包括钯、铜、镍、铑、锡、铂、或金。
12.根据权利要求1-11中任一个制成的可植入医疗设备。
13.根据权利要求1-11中任一个制成的起搏引线。
14.根据权利要求1-11中任一个制成的传感器。
15.根据权利要求1-11中任一个制成的通信设备。
16.根据权利要求1-11中任一个制成的开关。
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WO2013126458A1 (en) * | 2012-02-24 | 2013-08-29 | Skyworks Solutions, Inc. | Improved structures, devices and methods releated to copper interconnects for compound semiconductors |
US9002443B2 (en) * | 2013-03-15 | 2015-04-07 | Medtronic, Inc. | System and method for avoiding undersensing of ventricular fibrillation |
US10464836B2 (en) | 2013-10-10 | 2019-11-05 | Medtronic, Inc. | Hermetic conductive feedthroughs for a semiconductor wafer |
ES2661718T3 (es) | 2014-01-10 | 2018-04-03 | Cardiac Pacemakers, Inc. | Métodos y sistemas para mejorar la comunicación entre dispositivos médicos |
CN106068141B (zh) | 2014-01-10 | 2019-05-14 | 心脏起搏器股份公司 | 用于检测心脏心律失常的系统和方法 |
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US9968794B2 (en) | 2014-12-24 | 2018-05-15 | Medtronic, Inc. | Implantable medical device system including feedthrough assembly and method of forming same |
US9865533B2 (en) | 2014-12-24 | 2018-01-09 | Medtronic, Inc. | Feedthrough assemblies |
US10136535B2 (en) | 2014-12-24 | 2018-11-20 | Medtronic, Inc. | Hermetically-sealed packages including feedthrough assemblies |
CN107206242B (zh) | 2015-02-06 | 2020-10-30 | 心脏起搏器股份公司 | 用于电刺激治疗的安全递送的系统和方法 |
US9669230B2 (en) | 2015-02-06 | 2017-06-06 | Cardiac Pacemakers, Inc. | Systems and methods for treating cardiac arrhythmias |
US10046167B2 (en) | 2015-02-09 | 2018-08-14 | Cardiac Pacemakers, Inc. | Implantable medical device with radiopaque ID tag |
JP6341190B2 (ja) * | 2015-02-16 | 2018-06-13 | 株式会社デンソー | 半導体装置の製造方法 |
EP3265172B1 (en) | 2015-03-04 | 2018-12-19 | Cardiac Pacemakers, Inc. | Systems for treating cardiac arrhythmias |
US10050700B2 (en) | 2015-03-18 | 2018-08-14 | Cardiac Pacemakers, Inc. | Communications in a medical device system with temporal optimization |
WO2016149262A1 (en) | 2015-03-18 | 2016-09-22 | Cardiac Pacemakers, Inc. | Communications in a medical device system with link quality assessment |
US9853743B2 (en) | 2015-08-20 | 2017-12-26 | Cardiac Pacemakers, Inc. | Systems and methods for communication between medical devices |
EP3337559B1 (en) | 2015-08-20 | 2019-10-16 | Cardiac Pacemakers, Inc. | Systems and methods for communication between medical devices |
US9968787B2 (en) | 2015-08-27 | 2018-05-15 | Cardiac Pacemakers, Inc. | Spatial configuration of a motion sensor in an implantable medical device |
US9956414B2 (en) | 2015-08-27 | 2018-05-01 | Cardiac Pacemakers, Inc. | Temporal configuration of a motion sensor in an implantable medical device |
US10226631B2 (en) | 2015-08-28 | 2019-03-12 | Cardiac Pacemakers, Inc. | Systems and methods for infarct detection |
US10159842B2 (en) | 2015-08-28 | 2018-12-25 | Cardiac Pacemakers, Inc. | System and method for detecting tamponade |
EP3341076B1 (en) | 2015-08-28 | 2022-05-11 | Cardiac Pacemakers, Inc. | Systems and methods for behaviorally responsive signal detection and therapy delivery |
WO2017044389A1 (en) | 2015-09-11 | 2017-03-16 | Cardiac Pacemakers, Inc. | Arrhythmia detection and confirmation |
WO2017062806A1 (en) | 2015-10-08 | 2017-04-13 | Cardiac Pacemakers, Inc. | Devices and methods for adjusting pacing rates in an implantable medical device |
US9832867B2 (en) | 2015-11-23 | 2017-11-28 | Medtronic, Inc. | Embedded metallic structures in glass |
CN108472490B (zh) | 2015-12-17 | 2022-06-28 | 心脏起搏器股份公司 | 医疗设备系统中的传导通信 |
US10098589B2 (en) | 2015-12-21 | 2018-10-16 | Medtronic, Inc. | Sealed package and method of forming same |
US10905886B2 (en) | 2015-12-28 | 2021-02-02 | Cardiac Pacemakers, Inc. | Implantable medical device for deployment across the atrioventricular septum |
US10583303B2 (en) | 2016-01-19 | 2020-03-10 | Cardiac Pacemakers, Inc. | Devices and methods for wirelessly recharging a rechargeable battery of an implantable medical device |
WO2017136548A1 (en) | 2016-02-04 | 2017-08-10 | Cardiac Pacemakers, Inc. | Delivery system with force sensor for leadless cardiac device |
EP3436142A1 (en) | 2016-03-31 | 2019-02-06 | Cardiac Pacemakers, Inc. | Implantable medical device with rechargeable battery |
US10668294B2 (en) | 2016-05-10 | 2020-06-02 | Cardiac Pacemakers, Inc. | Leadless cardiac pacemaker configured for over the wire delivery |
US10328272B2 (en) | 2016-05-10 | 2019-06-25 | Cardiac Pacemakers, Inc. | Retrievability for implantable medical devices |
JP6764956B2 (ja) | 2016-06-27 | 2020-10-07 | カーディアック ペースメイカーズ, インコーポレイテッド | 再同期ペーシング管理に皮下で感知されたp波を使用する心臓治療法システム |
US11207527B2 (en) | 2016-07-06 | 2021-12-28 | Cardiac Pacemakers, Inc. | Method and system for determining an atrial contraction timing fiducial in a leadless cardiac pacemaker system |
US10426962B2 (en) | 2016-07-07 | 2019-10-01 | Cardiac Pacemakers, Inc. | Leadless pacemaker using pressure measurements for pacing capture verification |
US10688304B2 (en) | 2016-07-20 | 2020-06-23 | Cardiac Pacemakers, Inc. | Method and system for utilizing an atrial contraction timing fiducial in a leadless cardiac pacemaker system |
EP3500342B1 (en) | 2016-08-19 | 2020-05-13 | Cardiac Pacemakers, Inc. | Trans-septal implantable medical device |
US10870008B2 (en) | 2016-08-24 | 2020-12-22 | Cardiac Pacemakers, Inc. | Cardiac resynchronization using fusion promotion for timing management |
CN109640809B (zh) | 2016-08-24 | 2021-08-17 | 心脏起搏器股份公司 | 使用p波到起搏定时的集成式多装置心脏再同步治疗 |
US10166389B2 (en) | 2016-09-13 | 2019-01-01 | Cochlear Limited | Single-wire electrode array |
WO2018057626A1 (en) | 2016-09-21 | 2018-03-29 | Cardiac Pacemakers, Inc. | Implantable cardiac monitor |
US10758737B2 (en) | 2016-09-21 | 2020-09-01 | Cardiac Pacemakers, Inc. | Using sensor data from an intracardially implanted medical device to influence operation of an extracardially implantable cardioverter |
EP3515553B1 (en) | 2016-09-21 | 2020-08-26 | Cardiac Pacemakers, Inc. | Leadless stimulation device with a housing that houses internal components of the leadless stimulation device and functions as the battery case and a terminal of an internal battery |
US10765871B2 (en) | 2016-10-27 | 2020-09-08 | Cardiac Pacemakers, Inc. | Implantable medical device with pressure sensor |
WO2018081133A1 (en) | 2016-10-27 | 2018-05-03 | Cardiac Pacemakers, Inc. | Implantable medical device having a sense channel with performance adjustment |
CN109890457B (zh) | 2016-10-27 | 2023-07-04 | 心脏起搏器股份公司 | 单独的设备在管理心脏起搏器的起搏脉冲能量时的使用 |
US10413733B2 (en) | 2016-10-27 | 2019-09-17 | Cardiac Pacemakers, Inc. | Implantable medical device with gyroscope |
WO2018081225A1 (en) | 2016-10-27 | 2018-05-03 | Cardiac Pacemakers, Inc. | Implantable medical device delivery system with integrated sensor |
US10463305B2 (en) | 2016-10-27 | 2019-11-05 | Cardiac Pacemakers, Inc. | Multi-device cardiac resynchronization therapy with timing enhancements |
WO2018081721A1 (en) | 2016-10-31 | 2018-05-03 | Cardiac Pacemakers, Inc | Systems for activity level pacing |
WO2018081713A1 (en) | 2016-10-31 | 2018-05-03 | Cardiac Pacemakers, Inc | Systems for activity level pacing |
US10583301B2 (en) | 2016-11-08 | 2020-03-10 | Cardiac Pacemakers, Inc. | Implantable medical device for atrial deployment |
CN109952129B (zh) | 2016-11-09 | 2024-02-20 | 心脏起搏器股份公司 | 为心脏起搏设备设定心脏起搏脉冲参数的系统、设备和方法 |
US10881869B2 (en) | 2016-11-21 | 2021-01-05 | Cardiac Pacemakers, Inc. | Wireless re-charge of an implantable medical device |
CN109963618B (zh) | 2016-11-21 | 2023-07-04 | 心脏起搏器股份公司 | 具有多模式通信的无引线心脏起搏器 |
US10639486B2 (en) | 2016-11-21 | 2020-05-05 | Cardiac Pacemakers, Inc. | Implantable medical device with recharge coil |
US10894163B2 (en) | 2016-11-21 | 2021-01-19 | Cardiac Pacemakers, Inc. | LCP based predictive timing for cardiac resynchronization |
US11147979B2 (en) | 2016-11-21 | 2021-10-19 | Cardiac Pacemakers, Inc. | Implantable medical device with a magnetically permeable housing and an inductive coil disposed about the housing |
US11207532B2 (en) | 2017-01-04 | 2021-12-28 | Cardiac Pacemakers, Inc. | Dynamic sensing updates using postural input in a multiple device cardiac rhythm management system |
EP3573708B1 (en) | 2017-01-26 | 2021-03-10 | Cardiac Pacemakers, Inc. | Leadless implantable device with detachable fixation |
WO2018140623A1 (en) | 2017-01-26 | 2018-08-02 | Cardiac Pacemakers, Inc. | Leadless device with overmolded components |
AU2018213326B2 (en) | 2017-01-26 | 2020-09-10 | Cardiac Pacemakers, Inc. | Intra-body device communication with redundant message transmission |
US10737092B2 (en) | 2017-03-30 | 2020-08-11 | Cardiac Pacemakers, Inc. | Delivery devices and methods for leadless cardiac devices |
EP3606605B1 (en) | 2017-04-03 | 2023-12-20 | Cardiac Pacemakers, Inc. | Cardiac pacemaker with pacing pulse energy adjustment based on sensed heart rate |
US10905872B2 (en) | 2017-04-03 | 2021-02-02 | Cardiac Pacemakers, Inc. | Implantable medical device with a movable electrode biased toward an extended position |
US20180322316A1 (en) * | 2017-05-08 | 2018-11-08 | A.K. Stamping Company, Inc. | Flat Solenoid Coil |
EP3668592B1 (en) | 2017-08-18 | 2021-11-17 | Cardiac Pacemakers, Inc. | Implantable medical device with pressure sensor |
WO2019036568A1 (en) | 2017-08-18 | 2019-02-21 | Cardiac Pacemakers, Inc. | IMPLANTABLE MEDICAL DEVICE COMPRISING A FLOW CONCENTRATOR AND A RECEPTION COIL PROVIDED AROUND THE FLOW CONCENTRATOR |
WO2019060302A1 (en) | 2017-09-20 | 2019-03-28 | Cardiac Pacemakers, Inc. | IMPLANTABLE MEDICAL DEVICE WITH MULTIPLE OPERATING MODES |
US11185703B2 (en) | 2017-11-07 | 2021-11-30 | Cardiac Pacemakers, Inc. | Leadless cardiac pacemaker for bundle of his pacing |
WO2019108837A1 (en) | 2017-12-01 | 2019-06-06 | Cardiac Pacemakers, Inc. | Methods and systems for detecting atrial contraction timing fiducials within a search window from a ventricularly implanted leadless cardiac pacemaker |
WO2019108482A1 (en) | 2017-12-01 | 2019-06-06 | Cardiac Pacemakers, Inc. | Methods and systems for detecting atrial contraction timing fiducials and determining a cardiac interval from a ventricularly implanted leadless cardiac pacemaker |
WO2019108830A1 (en) | 2017-12-01 | 2019-06-06 | Cardiac Pacemakers, Inc. | Leadless cardiac pacemaker with reversionary behavior |
US11260216B2 (en) | 2017-12-01 | 2022-03-01 | Cardiac Pacemakers, Inc. | Methods and systems for detecting atrial contraction timing fiducials during ventricular filling from a ventricularly implanted leadless cardiac pacemaker |
CN108175941B (zh) | 2017-12-29 | 2021-10-22 | 创领心律管理医疗器械(上海)有限公司 | 基于无心室起搏的双腔起搏模式的存储介质及医疗设备 |
US11529523B2 (en) | 2018-01-04 | 2022-12-20 | Cardiac Pacemakers, Inc. | Handheld bridge device for providing a communication bridge between an implanted medical device and a smartphone |
US10874861B2 (en) | 2018-01-04 | 2020-12-29 | Cardiac Pacemakers, Inc. | Dual chamber pacing without beat-to-beat communication |
US11235159B2 (en) | 2018-03-23 | 2022-02-01 | Medtronic, Inc. | VFA cardiac resynchronization therapy |
EP3768369A1 (en) | 2018-03-23 | 2021-01-27 | Medtronic, Inc. | Av synchronous vfa cardiac therapy |
EP3768160B1 (en) | 2018-03-23 | 2023-06-07 | Medtronic, Inc. | Vfa cardiac therapy for tachycardia |
WO2020065582A1 (en) | 2018-09-26 | 2020-04-02 | Medtronic, Inc. | Capture in ventricle-from-atrium cardiac therapy |
US11951313B2 (en) | 2018-11-17 | 2024-04-09 | Medtronic, Inc. | VFA delivery systems and methods |
US11679265B2 (en) | 2019-02-14 | 2023-06-20 | Medtronic, Inc. | Lead-in-lead systems and methods for cardiac therapy |
US11697025B2 (en) | 2019-03-29 | 2023-07-11 | Medtronic, Inc. | Cardiac conduction system capture |
US11213676B2 (en) | 2019-04-01 | 2022-01-04 | Medtronic, Inc. | Delivery systems for VfA cardiac therapy |
US11712188B2 (en) | 2019-05-07 | 2023-08-01 | Medtronic, Inc. | Posterior left bundle branch engagement |
US11324944B1 (en) * | 2019-07-23 | 2022-05-10 | Verily Life Sciences Llc | Flexible cable assembly for medical implantation |
US11305127B2 (en) | 2019-08-26 | 2022-04-19 | Medtronic Inc. | VfA delivery and implant region detection |
US11559241B2 (en) | 2019-10-01 | 2023-01-24 | Pacesetter, Inc. | Methods and systems for reducing false declarations of arrhythmias |
US11813466B2 (en) | 2020-01-27 | 2023-11-14 | Medtronic, Inc. | Atrioventricular nodal stimulation |
US11911168B2 (en) | 2020-04-03 | 2024-02-27 | Medtronic, Inc. | Cardiac conduction system therapy benefit determination |
US11813464B2 (en) | 2020-07-31 | 2023-11-14 | Medtronic, Inc. | Cardiac conduction system evaluation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050115811A1 (en) * | 2003-10-28 | 2005-06-02 | Rogier Receveur | MEMs switching circuit and method for an implantable medical device |
US20070232023A1 (en) * | 2003-02-07 | 2007-10-04 | Ziptronix, Inc. | Room temperature metal direct bonding |
US20080205027A1 (en) * | 2007-02-22 | 2008-08-28 | Stmicroelectronics (Crolles 2) Sas | Assembly of two parts of an integrated electronic circuit |
CN101313396A (zh) * | 2005-11-21 | 2008-11-26 | 三菱麻铁里亚尔株式会社 | 没有内藏大孔隙的Au-Sn合金凸块及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374382A (en) | 1981-01-16 | 1983-02-15 | Medtronic, Inc. | Marker channel telemetry system for a medical device |
US4564584A (en) | 1983-12-30 | 1986-01-14 | Ibm Corporation | Photoresist lift-off process for fabricating semiconductor devices |
US5117824A (en) | 1990-11-14 | 1992-06-02 | Medtronic, Inc. | Apparatus for monitoring electrical physiologic signals |
US5154341A (en) * | 1990-12-06 | 1992-10-13 | Motorola Inc. | Noncollapsing multisolder interconnection |
US5545186A (en) | 1995-03-30 | 1996-08-13 | Medtronic, Inc. | Prioritized rule based method and apparatus for diagnosis and treatment of arrhythmias |
EP0993842B1 (en) | 1996-05-14 | 2003-01-15 | Medtronic, Inc. | Prioritized rule based apparatus for diagnosis and treatment of arrhythmias |
US6051887A (en) * | 1998-08-28 | 2000-04-18 | Medtronic, Inc. | Semiconductor stacked device for implantable medical apparatus |
US6266567B1 (en) * | 1999-06-01 | 2001-07-24 | Ball Semiconductor, Inc. | Implantable epicardial electrode |
US20070203547A1 (en) * | 2005-12-15 | 2007-08-30 | Costello Benedict J | Medical device identification |
US7627376B2 (en) | 2006-01-30 | 2009-12-01 | Medtronic, Inc. | Intravascular medical device |
US7809443B2 (en) | 2006-01-31 | 2010-10-05 | Medtronic, Inc. | Electrical stimulation to alleviate chronic pelvic pain |
US7591185B1 (en) | 2008-04-23 | 2009-09-22 | Medtronic, Inc. | Pressure sensor configurations for implantable medical electrical leads |
US8672917B2 (en) | 2009-01-05 | 2014-03-18 | Medtronic, Inc. | Pressure monitoring to control delivery of therapeutic agent |
WO2010115194A1 (en) * | 2009-04-03 | 2010-10-07 | Intrapace, Inc. | Feedback systems and methods for communicating diagnostic and/or treatment signals to enhance obesity treatments |
US20100305628A1 (en) | 2009-05-29 | 2010-12-02 | Medtronic, Inc. | Elongate battery for implantable medical device |
-
2011
- 2011-04-28 CN CN201180032510.1A patent/CN102986013B/zh active Active
- 2011-04-28 US US13/096,982 patent/US8433402B2/en active Active
- 2011-04-28 EP EP11720639.1A patent/EP2564417B1/en active Active
- 2011-04-28 MY MYPI2012004728 patent/MY152833A/en unknown
- 2011-04-28 US US13/096,968 patent/US20110270099A1/en not_active Abandoned
- 2011-04-28 WO PCT/US2011/034399 patent/WO2011139862A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070232023A1 (en) * | 2003-02-07 | 2007-10-04 | Ziptronix, Inc. | Room temperature metal direct bonding |
US20050115811A1 (en) * | 2003-10-28 | 2005-06-02 | Rogier Receveur | MEMs switching circuit and method for an implantable medical device |
CN101313396A (zh) * | 2005-11-21 | 2008-11-26 | 三菱麻铁里亚尔株式会社 | 没有内藏大孔隙的Au-Sn合金凸块及其制造方法 |
US20080205027A1 (en) * | 2007-02-22 | 2008-08-28 | Stmicroelectronics (Crolles 2) Sas | Assembly of two parts of an integrated electronic circuit |
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MY152833A (en) | 2014-11-28 |
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