CN102983921B - Automatic simulation method and system for time division multiplexing (TDM) link based on field programmable gate array (FPGA) - Google Patents
Automatic simulation method and system for time division multiplexing (TDM) link based on field programmable gate array (FPGA) Download PDFInfo
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Abstract
The invention provides an automatic simulation method and a system for a TDM link based on the FPGA. The method includes: S1, constructing a main exchange FPGA chip, a plurality of branch exchange FPGA chips and a plurality of simulation devices, wherein the main exchange FPGA chip comprises a control unit and is controlled by the control unit, the plurality of branch exchange FPGA chips are connected with the main exchange FPGA chip, the plurality of simulation devices are connected with E1 interface chips of the branch exchange FPGA chips, and the E1 interface chips are connected to an external tested E1 link; S2, determining a link ID to be simulated and simulation actions, and the control unit sending a corresponding control instruction to the exchange FPGA chips; and S3, selecting the E1 link to be simulated according to the control instruction and performing simulation of corresponding simulation actions based on the selected E1 link. According to the method and the system, the simulation test to the TDM link is achieved through the simulation device completely, the process is completed automatically, artificial participation is avoided, the test efficiency is greatly improved, and the coverage rate of the tests is expanded.
Description
Technical field
The present invention relates to network communication field technology, relate in particular to a kind of exchange of TDM link, link failure automatization simulation method and corresponding analogue system based on FPGA.
Background technology
At present, the circuit switching equipment based on TDM technology that communications equipment vendor produces both at home and abroad, in order to verify function and the robustness of its equipment, conventionally need under lab carry out the various tests such as circuit connection, switching, to carry out different networking tests, wherein, testing scheme generally includes the abnormal ability of checkout equipment treatment circuit.
In prior art, the switch groups net mode in testing scheme or analog circuit anomalous mode, be generally by tester, manually to plug E1 line to realize.Yet the mode of manual simulation's fault can not be accomplished whole day continual test in 24 hours, and, manual switching networking, in the situation that network size is larger, because interface is very many, easily because manual operation is improper, go wrong, and after going wrong, malfunction elimination is very difficult; What is more important, manual simulation's fault does not have repeatability, and circuit can not accurately be controlled break period.
Based on the problems referred to above, be necessary very much to provide a kind of equipment automatization testing scheme.
Summary of the invention
The technical problem of solution required for the present invention is to provide a kind of TDM link automatization simulation method based on FPGA, and whole simulation test process automatically completes, and improves testing efficiency and accuracy.
Correspondingly, the present invention also provides a kind of TDM link automated modeling system based on FPGA.
For solving the problems of the technologies described above, the technical solution used in the present invention is:
A TDM link automatization simulation method based on FPGA, it comprises the steps:
Minute exchange fpga chip that S1, a structure one main exchange fpga chip that comprises control unit, is connected with described control unit and controlled by described control unit, one or more and described main exchange fpga chip are connected and some analogue means that exchanges the E1 interface chip of fpga chip for described minute that is connected in, wherein, described E1 interface chip is connected in outside tested E1 link;
S2, determine link ID and the simulated action of required simulation, and to main exchange fpga chip, send corresponding control command by described control unit;
S3, according to described control command, the E1 link of selected required simulation, and carry out the simulation of corresponding simulated action based on selected E1 link.
As the further improvement of the inventive method, described simulated action comprises link failure simulation, link down simulation, the unstable simulation of link, the simulation of different link switching.
As the further improvement of the inventive method, described step S3 comprises:
According to control command, the script of selected required simulation is two E1 links independently mutually, wherein, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, an E1 interface chip on every E1 link;
Selected two E1 link interconnects are become to a link.
As the further improvement of the inventive method, when carrying out " link down simulation ", the instruction that sends " disconnecting link " by control unit is to main exchange fpga chip; When carrying out " the unstable simulation of link ", by control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip.
Correspondingly, a kind of TDM link automated modeling system based on FPGA provided by the invention, it comprises: a control unit, be connected with described control unit and minute exchange fpga chip and some E1 interface chips that is connected in described minute exchange fpga chip that a main exchange fpga chip of being controlled by described control unit, one or more and described main exchange fpga chip are connected, wherein, described E1 interface chip is connected in outside tested E1 link; Described control unit is used for determining link ID and the simulated action of required simulation, and to main exchange fpga chip, sends corresponding control command by described control unit; Described main exchange fpga chip, according to described control command, is selected the E1 link of required simulation, and is carried out the simulation of corresponding simulated action based on selected E1 link.
As the further improvement of system of the present invention, described simulated action comprises link failure simulation, link down simulation, the unstable simulation of link, the simulation of different link switching.
As the further improvement of system of the present invention, this system also specifically for:
According to control command, the script of selected required simulation is two E1 links independently mutually, wherein, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, an E1 interface chip on every E1 link;
Selected two E1 link interconnects are become to a link.
As the further improvement of system of the present invention, in native system, when carrying out " link down simulation ", the instruction that sends " disconnecting link " by control unit is to main exchange fpga chip; When carrying out " the unstable simulation of link ", by control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip.
According to above technical scheme, can find out, because the present invention realizes the simulation test to TDM link by analogue means completely, its process full automation completes, avoid artificial participation, greatly improved testing efficiency, the coverage rate of extend testing, in addition, use present device to carry out networking switching, can in Millisecond, complete the switching of network topology, and based on predefined a plurality of network topologies, switch arbitrarily easily, use present device analog circuit fault, interrupt precision and can reach Millisecond, measuring accuracy and speed all significantly promote.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the specific embodiment of the invention or prior art, to the accompanying drawing of required use in the specific embodiment of the invention or existing description be briefly described below, apparently, following accompanying drawing is only a part of accompanying drawing of the present invention, for those of ordinary skills, do not making under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the unit connection diagram of the TDM link automated modeling system based on FPGA in the specific embodiment of the invention;
Fig. 2 shows the mode of an embodiment of the present invention link simulation;
Fig. 3 is the flow chart of the TDM link automatization simulation method based on FPGA in the specific embodiment of the invention.
Embodiment
Below with reference to embodiment shown in the drawings, describe the present invention.But these execution modes do not limit the present invention, based on various embodiments of the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under the prerequisite of creative work, all should be included in protection scope of the present invention.
Shown in ginseng Fig. 1, in the specific embodiment of the invention, the described TDM link automated modeling system 100 based on FPGA comprises that control unit 1(can be various forms of CPU, MCU etc.), a main exchange fpga chip 2, one or more minutes exchange fpga chips 3, and several to adopt model with the E1 interface chip 4(the present invention that is connected of above-mentioned minute exchange fpga chip 3 be the interface chip of DS26324).Wherein, control unit 1 with whole system is played to master control effect; Main exchange fpga chip 2 is responsible for 512 E1 links altogether of whole system to carry out circuit-switching function; Divide exchange fpga chip 3 to be responsible for converging all E1 link channel on this subsystem; DS26324 E1 interface chip 4 is responsible for externally providing E1 interface, interconnected with external equipment.Native system provides extended capability flexibly, and in certain embodiments of the invention, within above-mentioned minute, exchange FPGA subsystem can expand or reduce with entire system scale demand.
Wherein, system control unit 1 is connected with main exchange fpga chip 2 by control bus, and in this bus, the control command of main transmission CPU1, controls main exchange fpga chip 2 and carry out corresponding link simulated action according to the indication of control unit 1; And minute main being responsible for of exchange fpga chip 3 converged the data of DS26324 E1 interface chip 4 below by data/address bus, and data are processed by giving main exchange fpga chip 2 on data/address bus; DS26324 E1 interface chip is mainly processed E1 physical interface signal.
In the present invention, described control unit 1 is for determining link ID and the simulated action of required simulation, and to main exchange fpga chip 2, sends corresponding control command by described control unit 1; Described main exchange fpga chip 2, according to described control command, is selected the E1 link of required simulation, and is carried out the simulation of corresponding simulated action based on selected E1 link.Wherein, described simulated action can comprise link failure simulation, link down simulation, the unstable simulation of link, different link switching simulations etc.
Shown in ginseng Fig. 2, in an embodiment of the present invention, first, control unit 1 based on said system sends corresponding control command (instruction comprises the ID of target link), so main exchange fpga chip is just according to control command, the script of the selected required simulation of automation is two E1 links (as shown in phantom in FIG.) independently mutually, wherein, on every E1 link, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, one E1 interface chip, after this selected two E1 link interconnects are become to a link, this has also just implemented the basis that topology is built, realized the function of any two E1 link establishments interconnection.
In another embodiment of the present invention, as need analog link fault, control unit sends corresponding instruction, its particular link is disconnected, to realize the simulated action of " link down simulation ";
In another embodiment of the present invention, as need analog link unstable (be link disconnect and Fast reconnect), control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip, to realize the simulated action of " the unstable simulation of link ";
In another embodiment of the present invention, as need are simulated the quick switching between different links, control unit sends corresponding instruction, current simulated link is disconnected, sending corresponding " switching command ", another two links are connected with each other, to realize the simulation of the quick switching between different links.
It is worth mentioning that, the mentioned exchange fpga chip of the present invention can adopt the chip that possesses tdm data exchange capacity, can be including, but not limited to asic chip, fpga chip etc.
Certainly, in other execution modes of the present invention, also comprise other forms of analog form, only need to by control unit, send corresponding instruction according to analog form can realize.
Shown in ginseng Fig. 3, in the specific embodiment of the invention, a kind of TDM link automatization simulation method based on FPGA, it comprises the steps:
S1, structure one comprise minute exchange fpga chip and the some analogue means that exchanges the E1 interface chip of fpga chip for described minute that is connected in that control unit, a main exchange fpga chip of being controlled by described control unit, one or more and described main exchange fpga chip are connected, wherein, described E1 interface chip is connected in outside tested E1 link;
S2, determine link ID and the simulated action of required simulation, and to main exchange fpga chip, send corresponding control command by described control unit;
S3, according to described control command, the E1 link of selected required simulation, and carry out the simulation of corresponding simulated action based on selected E1 link.In some execution mode of the present invention, described simulated action comprises link failure simulation, link down simulation, the unstable simulation of link, the simulation of different link switching.
In addition,, in some execution mode of the present invention, described step S3 comprises:
According to control command, the script of selected required simulation is two E1 links independently mutually, wherein, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, an E1 interface chip on every E1 link; Selected two E1 link interconnects are become to a link.
In some execution mode of the present invention, when carrying out " link down simulation ", the instruction that sends " disconnecting link " by control unit is to main exchange fpga chip; When carrying out " the unstable simulation of link ", by control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip.
It should be noted that, the concrete function mode of the embodiment of the relevant TDM link automatization simulation method based on FPGA provided by the invention, concrete technical characterictic, function, effect etc., the embodiment of the relevant TDM link automated modeling system based on FPGA may refer to the above description, is no longer repeated this inventor.
In sum, because the present invention realizes the simulation test to TDM link by analogue means completely, its process full automation completes, avoid artificial participation, greatly improved testing efficiency, the coverage rate of extend testing, in addition, use present device to carry out networking switching, can in Millisecond, complete the switching of network topology, and based on predefined a plurality of network topologies, switch arbitrarily easily, use present device analog circuit fault, interrupt precision and can reach Millisecond, measuring accuracy and speed all significantly promote.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, technical scheme in each execution mode also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Listed a series of detailed description is above only illustrating for feasibility execution mode of the present invention; they are not in order to limit the scope of the invention, all disengaging within equivalent execution mode that skill spirit of the present invention does or change all should be included in protection scope of the present invention.
Claims (8)
1. the TDM link automatization simulation method based on FPGA, is characterized in that, it comprises the steps:
Minute exchange fpga chip that S1, a structure one main exchange fpga chip that comprises control unit, is connected with described control unit and controlled by described control unit, one or more and described main exchange fpga chip are connected and some analogue means that exchanges the E1 interface chip of fpga chip for described minute that is connected in, wherein, described E1 interface chip is connected in outside tested E1 link;
S2, determine link ID and the simulated action of required simulation, and to main exchange fpga chip, send corresponding control command by described control unit;
S3, according to described control command, the E1 link of selected required simulation, and carry out the simulation of corresponding simulated action based on selected E1 link.
2. method according to claim 1, is characterized in that, described simulated action comprises link down simulation, the unstable simulation of link, the simulation of different link switching.
3. method according to claim 2, is characterized in that, described step S3 comprises:
According to control command, the script of selected required simulation is two E1 links independently mutually, wherein, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, an E1 interface chip on every E1 link;
Selected two E1 link interconnects are become to a link.
4. method according to claim 3, is characterized in that, when carrying out " link down simulation ", the instruction that sends " disconnecting link " by control unit is to main exchange fpga chip; When carrying out " the unstable simulation of link ", by control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip.
5. the TDM link automated modeling system based on FPGA, it is characterized in that, it comprises: a control unit, be connected with described control unit and minute exchange fpga chip and some E1 interface chips that is connected in described minute exchange fpga chip that a main exchange fpga chip of being controlled by described control unit, one or more and described main exchange fpga chip are connected, wherein, described E1 interface chip is connected in outside tested E1 link; Described control unit is used for determining link ID and the simulated action of required simulation, and to main exchange fpga chip, sends corresponding control command by described control unit; Described main exchange fpga chip, according to described control command, is selected the E1 link of required simulation, and is carried out the simulation of corresponding simulated action based on selected E1 link.
6. system according to claim 5, is characterized in that, described simulated action comprises link down simulation, the unstable simulation of link, the simulation of different link switching.
7. system according to claim 6, is characterized in that, this system also specifically for:
According to control command, the script of selected required simulation is two E1 links independently mutually, wherein, comprise a corresponding main exchange fpga chip, one minute exchange fpga chip, an E1 interface chip on every E1 link;
Selected two E1 link interconnects are become to a link.
8. system according to claim 7, is characterized in that, in native system, when carrying out " link down simulation ", the instruction that sends " disconnecting link " by control unit is to main exchange fpga chip; When carrying out " the unstable simulation of link ", by control unit at certain intervals the time instruction that sends respectively "off" and " reconnecting " give main exchange fpga chip.
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| KR20050052897A (en) * | 2003-12-01 | 2005-06-07 | 엘지전자 주식회사 | Swiching system and method capable of supporting convergence service through interworking various network |
| CN101299685A (en) * | 2008-03-18 | 2008-11-05 | 华为技术有限公司 | Method and system for testing switching network as well as test initiation module |
| CN102006199A (en) * | 2009-08-28 | 2011-04-06 | 中兴通讯股份有限公司 | Time division multiplexing (TDM) switching module testing device, method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050052897A (en) * | 2003-12-01 | 2005-06-07 | 엘지전자 주식회사 | Swiching system and method capable of supporting convergence service through interworking various network |
| CN101299685A (en) * | 2008-03-18 | 2008-11-05 | 华为技术有限公司 | Method and system for testing switching network as well as test initiation module |
| CN102006199A (en) * | 2009-08-28 | 2011-04-06 | 中兴通讯股份有限公司 | Time division multiplexing (TDM) switching module testing device, method and system |
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