CN102983845A

CN102983845A - Anti-interference reset circuit

Info

Publication number: CN102983845A
Application number: CN2012104759977A
Authority: CN
Inventors: 谢卫国
Original assignee: JIANGSU GELITE ELECTRONICS CO Ltd
Current assignee: JIANGSU GELITE ELECTRONICS CO Ltd
Priority date: 2012-11-22
Filing date: 2012-11-22
Publication date: 2013-03-20

Abstract

The invention discloses an anti-interference reset circuit and relates to the design field of integrated circuits. The anti-interference reset circuit comprises a P-channel metal oxide semiconductor (PMOS) pipe with a source connected with a power supply and a drain connected with a capacitor with one end connected with the ground. A connecting point of the PMOS pipe and a capacitor is connected with the input end of an amplifying circuit formed by connecting inverters in series. The output end of the amplifying circuit is connected with an external circuit, and a grid of the PMOS pipe is connected with a connecting point of the inverters. By means of the characteristics of the PMOS pipe, the PMOS pipe is closed after a reset process is finished, power fluctuation does not affect electric quantity of the capacitor, and a purpose of improving anti-interference performance is achieved. The anti-interference reset circuit is simple in structure and convenient to implement and does not affect the cost of a chip.

Description

A kind of anti-interference reset circuit

Technical field

The present invention relates to the integrated circuit (IC) design field, be specifically related to a kind of reset circuit.

Background technology

In the design of integrated circuit, the anti-interference problem of chip can not be ignored, and when chip drove larger drive circuit, driving to affect power generation; The function of reset circuit is to guarantee that chip can normal initialization, in the voltage that the utilizes electric capacity principle of not suddenling change, power source charges is realized in the reset circuit of function of initializing by the P-MOS pipe, because the P-MOS pipe is in conducting state, if power-supply fluctuation is larger, or the fluctuation time is longer, can make internal circuit produce mistake and reset, and causes the function of chip chaotic.

Summary of the invention

The problem to be solved in the present invention provides a kind of anti-interference reset circuit, can solve prior art and manage conducting because of P-MOS, the problem that causes the internal circuit mistake to reset in the power-supply fluctuation situation.

The present invention is achieved through the following technical solutions:

A kind of anti-interference reset circuit, comprise the PMOS pipe that source electrode is connected with power supply, drains and be connected with the capacitor of an end ground connection, described PMOS pipe is connected the connect input of amplifying circuit of formation of tie point and inverter and is connected with capacitor, the output of described amplifying circuit connects external circuit, and the grid of described PMOS pipe is connected in the tie point of inverter and inverter.

The present invention's advantage compared with prior art is:

One, utilizes the characteristic of PMOS pipe, after reseting procedure finishes, close the PMOS pipe, make the fluctuation of power supply not affect the electric weight of electric capacity, reach the purpose that improves anti-interference;

Two, simple in structure, it is convenient to implement, and does not affect the cost of chip.

Description of drawings

Fig. 1 is the circuit structure diagram of the reset circuit of prior art.

Fig. 2 is the circuit structure diagram of anti-interference reset circuit of the present invention.

Embodiment

Reset circuit as shown in Figure 1, comprise the PMOS pipe 1 that source electrode is connected with power supply 6, drains and be connected with the capacitor 2 of an end ground connection, described PMOS pipe 1 tie point of being connected with capacitor is connected with the input of the amplifying circuit that inverter 3,4,5 series connection consist of, the output 7 of described amplifying circuit connects external circuit, the grounded-grid of described PMOS pipe 1.

Anti-interference reset circuit as shown in Figure 2, difference compared to Figure 1 is: the grid of PMOS pipe 1 is connected in the tie point of inverter 4 and inverter 5; When chip is switched on, the voltage at capacitor 2 two ends is 0, manage 1 conducting and capacitor 2 is charged make chip enter reset mode through two

inverters

3,4 control PMOS, after reseting procedure finished, voltage was VDD on the capacitor 2, cut off the PMOS pipe through 3,4 inverters, voltage VDD on the capacitor 2 keeps, even the voltage of power supply 6 has fluctuation, also can the voltage on the capacitor 2 not exerted an influence, the situation that chip also just can wrongly not reset reaches the purpose that improves anti-interference.

Claims

1. anti-interference reset circuit, comprise the PMOS pipe (1) that source electrode is connected with power supply (6), drains and be connected with the capacitor (2) of an end ground connection, described PMOS pipe (1) is connected 2 with capacitor) the connect input of amplifying circuit of formation of tie point and inverter (3,4,5) be connected, the output of described amplifying circuit (7) connects external circuit, it is characterized in that: the grid of described PMOS pipe (1) is connected in the tie point of inverter (4) and inverter (5).