A kind of high voltage stabilizer with feedback circuit
Technical field
The present invention relates to SIC (semiconductor integrated circuit) field, particularly relate to a kind of high voltage stabilizer of belt current compensation.
Background technology
At present, the high voltage stabilizer of use has two kinds of solutions conventionally, and a kind of is the voltage-regulating circuit that uses high voltage PMOS and high pressure NMOS to do, but because the use meeting of high tension apparatus obviously increases cost of manufacture;
Another kind is to use general voltage clamping circuit, and its shortcoming is that driving force is limited, and driving force when increasing power consumption can increase rapidly.So, need one simple in structure, driving force is large, the high voltage stabilizing structure of low-power consumption.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of high voltage stabilizer simple in structure, is applied to SIC (semiconductor integrated circuit) and manufactures field, can reduce mu balanced circuit power consumption, improves mu balanced circuit driving force.
For solving the problems of the technologies described above, high-voltage stabilizing circuit of the present invention, comprising:
One one end of external power source VDD contact resistance R1 and the drain electrode of high pressure NMOS pipe M4, the other end of resistance R 1 connects the source electrode of PMOS pipe M1;
The grid of PMOS pipe M1 connects its drain electrode, and its drain electrode connects the drain electrode of NMOS pipe M2, and its substrate connects its source electrode;
The grid of NMOS pipe M2 connects its drain electrode, and its source electrode connects the drain electrode of NMOS pipe M3, and its substrate connects ground;
The grid of NMOS pipe M3 connects its drain electrode, and its source electrode connects the emitter of bipolar junction transistor D1, and its substrate connects ground;
Its grid of high pressure NMOS pipe M4 connects the NMOS pipe source electrode of M1 and one end of resistance R 2, and its source electrode connects internal electric source, and its substrate connects ground;
The other end of resistance R 2 connects the NMOS pipe grid of M5 and one end of resistance R 3, and the other end of resistance R 3 connects ground;
Its drain electrode of NMOS pipe M5 connects the source electrode of NMOS pipe M1, and its source electrode connects the emitter of bipolar junction transistor D2, and its substrate connects ground;
Its base stage separately of bipolar junction transistor D1 and bipolar junction transistor D2 connects ground after being connected its collector separately.
The Standard resistance range of described resistance R 1 is 20K to 50K.
The voltage range of described external power source VDD is VDD≤28V.
The voltage of external power source VDD input, by the acting in conjunction of resistance R 1, PMOS pipe M1, NMOS pipe M2, NMOS pipe M3 and bipolar junction transistor D1, produce voltage VCLAMP, can reduce the power consumption of mu balanced circuit by choosing resistance at 20k to the resistance R 1 between 50k.
The electric current that definition power supply flows through resistance R 1 is I0, and flowing through PMOS pipe M1, NMOS pipe M2, NMOS pipe M3 and bipolar junction transistor D1 is I1 to the electric current on ground, and the NMOS that flows through pipe M5, bipolar junction transistor D2 are I2 to the electric current on ground.I0=I1+I2。In the time that VDD changes, I2 and I0 increase simultaneously or diminish simultaneously, by the compensating action of I2, I1 are not changed with the variation of VDD, and to maintain voltage constant for VCLAMP like this.
Wherein, bipolar junction transistor D2 can use other load to substitute, such as diode, resistance or NMOS pipe.
High voltage stabilizer of the present invention, is applied to SIC (semiconductor integrated circuit) and manufactures field, can reduce mu balanced circuit power consumption, improves mu balanced circuit driving force.
Brief description of the drawings
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the electrical block diagram of one embodiment of the invention
Fig. 2 is VCLAMP-VDD family curve, while showing Vsp=5V, and the family curve relation of VCLAMP-VDD.
Description of reference numerals
VDD is external power source
VOUT is internal electric source
R1, R2, R3 are resistance
M1 is PMOS pipe
M2, M3, M5 are NMOS pipes
M4 is high pressure NMOS pipe
D1, D2 are bipolar junction transistors.
Embodiment
As shown in Figure 1, one embodiment of the invention, comprising:
One one end of external power source VDD contact resistance R1 and the drain electrode of high pressure NMOS pipe M4, the other end of resistance R 1 connects the source electrode of PMOS pipe M1;
The grid of PMOS pipe M1 connects its drain electrode, and its drain electrode connects the drain electrode of NMOS pipe M2, and its substrate connects its source electrode;
The grid of NMOS pipe M2 connects its drain electrode, and its source electrode connects the drain electrode of NMOS pipe M3, and its substrate connects ground;
The grid of NMOS pipe M3 connects its drain electrode, and its source electrode connects the emitter of bipolar junction transistor D1, and its substrate connects ground;
Its grid of high pressure NMOS pipe M4 connects the NMOS pipe source electrode of M1 and one end of resistance R 2, and its source electrode connects internal electric source, and its substrate connects ground;
The other end of resistance R 2 connects the NMOS pipe grid of M5 and one end of resistance R 3, and the other end of resistance R 3 connects ground;
Its drain electrode of NMOS pipe M5 connects the source electrode of NMOS pipe M1, and its source electrode connects the emitter of bipolar junction transistor D2, and its substrate connects ground;
Its base stage separately of bipolar junction transistor D1 and bipolar junction transistor D2 connects ground after being connected its collector separately.
The high voltage stabilizer of the present embodiment is applied in the power-supply system of Hall switch sensor, can meet the input range of external power source vdd voltage from 3.5V to 28V, and mu balanced circuit electric current maximum is no more than 1mA, can drive the load of 4mA.
As shown in Figure 2, the voltage characteristic figure of VCLAMP-VDD, while showing Vsp=5V, the family curve relation of VCLAMP-VDD.
If what the input voltage of external power source VDD was less than a setting needs changing voltage Vsp (Vsp equals the operating voltage of internal circuit), VCLAMP voltage can equal VDD, plays Following effect;
If the input voltage of external power source VDD is more than or equal to Vsp, VCLAMP can be approximately equal to Vsp, does not change with VDD, plays pressure stabilization function, and in the time of VDD≤28V, VCLAMP is not higher than 6.5V.Resistance R 2, NMOS pipe M5 and a backfeed loop of bipolar junction transistor D3 composition, in the time that VCLAMP uprises, the grid voltage of NMOS pipe M5 raises, and the electric current of NMOS pipe M5 is increased, the electric current of the resistance R of flowing through 1 can flow into NMOS pipe M5, makes the electric current of PMOS pipe M1 constant.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.