CN102956482A - Manufacturing method of semiconductor devices - Google Patents
Manufacturing method of semiconductor devices Download PDFInfo
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- CN102956482A CN102956482A CN2011102392723A CN201110239272A CN102956482A CN 102956482 A CN102956482 A CN 102956482A CN 2011102392723 A CN2011102392723 A CN 2011102392723A CN 201110239272 A CN201110239272 A CN 201110239272A CN 102956482 A CN102956482 A CN 102956482A
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Abstract
The invention provides a manufacturing method of semiconductor devices. The manufacturing method includes providing a transistor structure comprising a buried oxide layer formed on a silicon substrate, fin-shaped trenches formed on the buried oxide layer, a grid material layer formed on the fin-shaped trenches and the buried oxide layer and an oxide layer formed on the grid material layer; forming an APF (advanced patterning film ) layer on the oxide layer; forming an organic material layer on the APF layer; forming a capping layer on the organic material layer; and forming a bottom anti-reflection coating layer and photoresist on the capping layer sequentially and patterning the grid material layer. Since the organic material layer formed by the aid of the APF layer according to a spin coating technology is used as a pattern transfer layer in a patterning process of polycrystalline silicon grids of FinFet, surfaces of wafers can be flattened, and patterning effect is guaranteed.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of graphic method for the FinFet polysilicon gate.
Background technology
Existing complementary metal oxide semiconductors (CMOS) (CMOS) transistor is two-dimentional, and along with constantly dwindling of channel dimensions, the problem relevant with short-channel effect more and more is difficult to overcome.Therefore, chip manufacturer is developing the transistor of the three-dimensional with higher effect, fin formula field effect transistor (FinFet) for example, and it can adapt to the scaled requirement of device size better.In FinFet, the fin-shaped channel (Fin) that stands upright on the silicon-on-insulator (SOI) has replaced the planar channeling in the traditional cmos, because the shoulder height that causes of Fin, causes that polysilicon gate graphically had a larger challenge.The shoulder height of described polysilicon gate will affect the process window of photoetching.
Existing FinFet polysilicon gate pattern technology adopts APF(Advanced Patterning Film usually) as hard mask layer, this is because APF has good physical property, and high etching selectivity and low line edge roughness (LER) can be provided.But APF is by conformal CVD process deposits, and its air spots is smooth, be still on the surface of APF by the dielectric antireflective coatings (DARC) of CVD process deposits afterwards uneven, thereby increase the difficulty of photoetching.If adopt the method for spin coating organic material layer to replace the deposition of DARC can make flattening wafer surface, but the physical property of this organic material layer that applies by spin coating proceeding is relatively poor, when formation has the structure of high-aspect-ratio, easily collapse, affect the effect of gate patterns.
Therefore, need to propose a kind of method, can guarantee the smooth of crystal column surface, do not affect again the effect of gate patterns.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: transistor arrangement is provided, and described transistor arrangement comprises the buried oxide layer that is formed on the silicon substrate, be formed on fin-shaped channel on the described buried oxide layer, be formed on the gate material layers on described fin-shaped channel and the buried oxide layer and be formed on oxide skin(coating) on the described gate material layers; Form the APF layer at described oxide skin(coating); Form organic material layer at described APF layer; Form cover layer at described organic material layer; On described cover layer, form successively bottom antireflective coating and photoresist, described gate material layers is carried out graphical treatment.
Further, the figure transfer layer that described gate material layers is carried out graphical treatment comprises described APF layer and organic material layer.
Further, adopt conformal CVD depositing operation to form described APF layer.
Further, adopt spin coating proceeding to form described organic material layer.
Further, the thickness of described organic material layer depends on the height of described fin-shaped channel and the smooth degree on described APF layer surface.
Further, adopt spin coating proceeding to form described cover layer.
Further, described cover layer be low temperature oxide layer or with the material layer that is rich in silicon of described organic material layer compatibility.
Further, the described material layer that is rich in silicon is that silicon content is the bottom antireflective coating of 15-40%.
Further, described APF layer is amorphous carbon layer.
According to the present invention, utilize the APF layer and adopt the organic material layer of spin coating proceeding formation as the figure transfer layer of the graphical process of FinFet polysilicon gate, can make crystal column surface smooth, guarantee patterned effect.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In the accompanying drawing:
Figure 1A-Fig. 1 D is the schematic cross sectional view of each step of the graphic method that is used for the FinFet polysilicon gate that proposes of the present invention;
Fig. 2 is the flow chart of the graphic method that is used for the FinFet polysilicon gate that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that the graphic method that is used for the FinFet polysilicon gate that explaination the present invention proposes in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, the detailed step of the graphic method that is used for the FinFet polysilicon gate that the present invention proposes is described with reference to Figure 1A-Fig. 1 D and Fig. 2.
With reference to Figure 1A-Fig. 1 D, wherein show the schematic cross sectional view of each step of the graphic method that is used for the FinFet polysilicon gate that the present invention proposes.
At first, shown in Figure 1A, transistor arrangement 100 is provided, and described transistor arrangement 100 comprises the buried oxide layer 101 that is formed on the silicon substrate, be formed on fin-shaped channel (Fin) 102 on the described buried oxide layer 101, be formed on the gate material layers 103 on described fin-shaped channel and the buried oxide layer and be formed on oxide skin(coating) 104 on the described gate material layers 103.Silicon substrate among Fig. 1 under the not shown described buried oxide layer 101, described silicon substrate and the buried oxide layer on it consist of silicon-on-insulator (SOI) structure.The method that forms described transistor arrangement 100 is had the knack of by those skilled in the art, for outstanding emphasis of the present invention, is no longer given unnecessary details at this.
Then, as shown in Figure 1B, form APF layer 105 at described oxide skin(coating) 104, the method that forms described APF layer 105 is conformal CVD depositing operation well known in the art.Described advanced patterned layer (APF) specifically can be amorphous carbon layer.Because the shoulder height that described fin-shaped channel causes, the surface of described APF layer 105 is uneven.
Then, shown in Fig. 1 C, form organic material layer 106 at described APF layer 105, adopt spin coating proceeding (spin on) to form described organic material layer 106, to guarantee the smooth of crystal column surface.The thickness of described organic material layer 106 depends on the height of described fin-shaped channel and the smooth degree on described APF layer surface.
Then, shown in Fig. 1 D, form a cover layer 107 at described organic material layer 106, as the mask layer of the described APF layer 105 of subsequent etch and organic material layer 106.The material of described organic material layer 107 can be low temperature oxide, and its formation temperature is lower than 300 ℃; Also can be silicon content be the bottom antireflective coating (Si-BARC) of 15-40% and other can with the material that is rich in silicon of described organic material layer compatibility.Adopt spin coating proceeding to form described cover layer 107.
Next, on described cover layer 107, form successively bottom antireflective coating (BARC) and photoresist 108, described gate material layers 103 is carried out graphical treatment.
So far, according to an exemplary embodiment of the present invention whole processing steps of method enforcement have been finished, according to the present invention, utilize APF and adopt the organic material layer of spin coating proceeding formation as the figure transfer layer of the graphical process of FinFet polysilicon gate, can make crystal column surface smooth, guarantee patterned effect.
With reference to Fig. 2, wherein show the flow chart of the graphic method that is used for the FinFet polysilicon gate of the present invention's proposition, be used for schematically illustrating the flow process of whole manufacturing process.
In step 201, transistor arrangement is provided, comprises the buried oxide layer that is formed on the silicon substrate, be formed on fin-shaped channel on the described buried oxide layer, be formed on the gate material layers on described fin-shaped channel and the buried oxide layer and be formed on oxide skin(coating) on the described gate material layers;
In step 202, form the APF layer at described oxide skin(coating);
In step 203, form organic material layer at described APF layer;
In step 204, form cover layer at described organic material layer;
In step 205, on described cover layer, form successively bottom antireflective coating and photoresist, described gate material layers is carried out graphical treatment.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. the manufacture method of a semiconductor device comprises:
Transistor arrangement is provided, and described transistor arrangement comprises the buried oxide layer that is formed on the silicon substrate, be formed on fin-shaped channel on the described buried oxide layer, be formed on the gate material layers on described fin-shaped channel and the buried oxide layer and be formed on oxide skin(coating) on the described gate material layers;
Form the APF layer at described oxide skin(coating);
Form organic material layer at described APF layer;
Form cover layer at described organic material layer;
On described cover layer, form successively bottom antireflective coating and photoresist, described gate material layers is carried out graphical treatment.
2. method according to claim 1 is characterized in that, the figure transfer layer that described gate material layers is carried out graphical treatment comprises described APF layer and organic material layer.
3. method according to claim 1 is characterized in that, adopts conformal CVD depositing operation to form described APF layer.
4. method according to claim 1 is characterized in that, adopts spin coating proceeding to form described organic material layer.
5. method according to claim 1 is characterized in that, the thickness of described organic material layer depends on the height of described fin-shaped channel and the smooth degree on described APF layer surface.
6. method according to claim 1 is characterized in that, adopts spin coating proceeding to form described cover layer.
7. according to claim 1 or 6 described methods, it is characterized in that, described cover layer be low temperature oxide layer or with the material layer that is rich in silicon of described organic material layer compatibility.
8. method according to claim 7 is characterized in that, the described material layer that is rich in silicon is that silicon content is the bottom antireflective coating of 15-40%.
9. method according to claim 1 is characterized in that, described APF layer is amorphous carbon layer.
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| CN201110239272.3A CN102956482B (en) | 2011-08-19 | 2011-08-19 | A kind of manufacture method of semiconductor device |
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| CN201110239272.3A CN102956482B (en) | 2011-08-19 | 2011-08-19 | A kind of manufacture method of semiconductor device |
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| CN102956482B CN102956482B (en) | 2016-03-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106960905A (en) * | 2016-01-08 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641845A (en) * | 2003-12-08 | 2005-07-20 | 国际商业机器公司 | Method for forming finfet field effect transistor |
| EP1646080A1 (en) * | 2004-10-07 | 2006-04-12 | Interuniversitair Microelektronica Centrum ( Imec) | Etching of structures with high topography |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
| CN101364537A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for grid and semiconductor device, construction for manufacturing grid |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641845A (en) * | 2003-12-08 | 2005-07-20 | 国际商业机器公司 | Method for forming finfet field effect transistor |
| EP1646080A1 (en) * | 2004-10-07 | 2006-04-12 | Interuniversitair Microelektronica Centrum ( Imec) | Etching of structures with high topography |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
| CN101364537A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for grid and semiconductor device, construction for manufacturing grid |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106960905A (en) * | 2016-01-08 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
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