CN102946252A - Method and corresponding system for denoising horizon signals during sampling time of analog-digital converter (ADC) - Google Patents
Method and corresponding system for denoising horizon signals during sampling time of analog-digital converter (ADC) Download PDFInfo
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- CN102946252A CN102946252A CN2012104946117A CN201210494611A CN102946252A CN 102946252 A CN102946252 A CN 102946252A CN 2012104946117 A CN2012104946117 A CN 2012104946117A CN 201210494611 A CN201210494611 A CN 201210494611A CN 102946252 A CN102946252 A CN 102946252A
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Abstract
The invention provides a method and a corresponding system for denoising horizon signals during sampling time of an ADC. When synchronous sampling control signals of voltage currents are valid, and an ADC of a sampling system performs conversion and controls operating modes of digital circuits in the sampling system to be converted into a pause or idle state; and when the sampling system completes the conversion, operating modes of digital circuits in the sampling system are restored to a normal state. According to the method and the corresponding system for denoising horizon signals during sampling time of the ADC, noises at the horizon can be accurately reduced during the sampling time of the ADC, and accordingly, the sampling accuracy is improved; the scheme is simple to achieve, and no extra hardware circuit is needed to be added; and the practicality is high, and the method and the corresponding system can be applied to various ADC sampling occasions.
Description
Technical field
The present invention relates to the industrial measurement and control field, more specifically, relate to a kind of method and system of the reduction ADC sampling instant ground level signal noise of in the analog quantity sampling process of protecting electrical power system observing and controlling kind equipment, using.
Background technology
Protecting electrical power system observing and controlling kind equipment is to break down or during irregular operating when the electric component in the electric power system, makes quickly and accurately circuit breaker trip or sends the automatics of signal.And the signals such as the electric current and voltage of electric component, temperature and switching value are the major parameters of judging its operating state.Protection observing and controlling kind equipment by these signals are sampled and computing after, according to result of calculation, the state of real-time judge electric component, and provide corresponding control behavior according to its state.
The correct and prerequisite of reliably working of protection observing and controlling kind equipment to the accurate collection of the analog signals such as the electric current and voltage of electric component, temperature.The ADC(analog-digital converter is sent the analog signal after conditioning in analogue collection module or unit), be converted to digital signal, deliver to again the digital circuits such as logical device (FPGA or CPLD) or processor (CPU, DSP etc.) and calculate and judge.Because intrasystem digital circuit is when work, the ground noise that produces on its ground level loop can affect the sampling precision of analog quantity, in the prior art normal adopt simulation ground and digitally separate, the technical method such as single-point (or multiple spot) ground connection to be to reduce digital circuit to the impact of analog circuit.But these existing technical methods can not reduce the impact that digital circuit ground level signal causes sampling especially effectively, and have increased the complexity of circuit structure.
Summary of the invention
For above-mentioned deficiency and the actual demand of prior art, the invention provides a kind of method and corresponding system of the ADC of reduction sampling instant ground level signal noise.Because voltage and current signal has the phase parameter requirement, need to carry out synchronized sampling to electric current and voltage.The technical program namely is to utilize the synchronized sampling control signal of electric current and voltage, within the sampling period to sampling system in the mode of operation of digital circuit make corresponding change, reduction ADC(analog-digital converter) noise of the ground level of sampling instant, the sampling precision of raising analog quantity.
The method of reduction ADC sampling instant ground level signal noise of the present invention is characterized in that, may further comprise the steps:
When the synchronized sampling control signal of electric current and voltage was effective, the analog-digital converter of sampling system began to carry out conversion, and control switches to the mode of operation of digital circuit in the sampling system and suspends or idle condition;
When analog-digital converter was finished conversion, the mode of operation of digital circuit was recovered normal condition in the control sampling system.
Preferably, the mode of operation of digital circuit is switched to suspend or idle condition comprises: stop described digital circuit with outside data interaction and/or the circuit unit of described digital circuit is quit work.
Preferably, by exported to the state switching signal of digital circuit by analog-digital converter, control the switching of described digital circuit mode of operation.
Preferably, effective by making digital circuit export the chip selection signal of analog-digital converter to when the mode of operation of digital circuit is recovered normal condition, the numeral output of reading analog-digital converter.
In order to carry out above method, the present invention also provides corresponding ADC sampling system, comprise digital circuit and analog-digital converter, it is characterized in that, described digital circuit is used for synchronized sampling control signal at electric current and voltage and controls described analog-digital converter when effective and begin to carry out conversion; Described analog-digital converter switches to time-out or idle condition for the mode of operation of controlling described digital circuit when beginning to carry out conversion, and controls the mode of operation recovery normal condition of described digital circuit when finishing conversion.
Preferably, described analog-digital converter switches to the mode of operation of digital circuit and suspends or idle condition comprises: stop described digital circuit with outside data interaction and/or the circuit unit of described digital circuit is quit work.
Preferably, described analog-digital converter is used for the switching state switching signal of control figure circuit working pattern to digital circuit output.
Preferably, described digital circuit is exported chip selection signal to analog-digital converter, and digital circuit when mode of operation is recovered normal condition by making described chip selection signal effective, read the numeral output of analog-digital converter.
Preferably, described digital circuit is fpga logic circuit, CPLD logical circuit, CPU or DSP.
Preferably, described ADC sampling system also comprises the analog signal conditioner circuit, is used for analog signals is carried out preliminary treatment.
Principle of the present invention is that the synchronized sampling control signal at electric current and voltage becomes when effective, start working until during converting at the internal conversion circuit of analog-digital converter, make the mode of operation of the digital circuit in this sampling system switch to temporary transient halted state or idle pulley, the ground level noise of digital circuit initiation is less like this, impact on analog-digital converter internal conversion circuit reduces, and has improved the precision of sampled value.After converting, the control figure circuit recovers normal operation.
Beneficial effect of the present invention be except can accurately reducing in sampling instant the noise of ground level, thereby improves outside the sampling precision, and also comprise: implementation is simple, need not to increase extra hardware circuit; And practical, can be widely used in the occasion that various ADC sample.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is the sampling system modular structure schematic diagram of the embodiment of the invention.
Fig. 2 is the sequential schematic diagram of the embodiment of the invention.
Embodiment
In order to make those skilled in the art person understand better technical scheme of the present invention, and above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with embodiment and embodiment accompanying drawing.
Fig. 1 is the sampling system modular structure schematic diagram of the embodiment of the invention.The figure shows the present invention by typical sampling module system is improved the ADC sampling system that obtains.Wherein, analog signal conditioner circuit 1 receives original analog signals and it is carried out the preliminary treatment such as Isolation, shaping, convergent-divergent, to make it to be more suitable for the input requirements of analog-digital converter (ADC) 2.Analog-digital converter 2 is carried out the conversions from the analog signals to the digital quantity signal, can adopt according to the actual requirements the ADC device of various dissimilar, different switching figure places and different output interface forms in the prior art.Then the processing that digital circuit 3 is carried out the digital quantity signal after the conversion carries out data interaction with external system.The hardware resource of realizing digital circuit 3 is various, such as the logical device that can adopt the frameworks such as FPGA, CPLD, or the processor chips such as CPU, DSP, adopt in the present embodiment the fpga logic device.Except the transmission of sampled data, at the also mutual control by the mutual realization sampling system inside between system synchronization sampled signal CVT, inner synchronous sampling signal CVT_ADC, transition status signal CVT_STATE, data exchange control signal DATA_CTRL, the chip selection signal/CS_ADC and mutual with external system between analog-digital converter 2 and the digital circuit 3.Inside by analog-digital converter 2 and digital circuit 3 cooperatively interacts, so that the internal conversion circuit of analog-digital converter 2 is started working until during converting, the mode of operation of digital circuit 3 switches to temporary transient halted state or idle pulley, the ground level noise of digital circuit 3 initiations is less like this, impact on analog-digital converter 2 internal conversion circuit reduces, and has improved the precision of sampled value.After converting, control figure circuit 3 recovers normal operation.Reduce the concrete steps of the method for ADC sampling instant ground level signal noise below with reference to sequential chart explanation the present invention of Fig. 2.
Fig. 2 shows the sequential chart of system in the procedure of carrying out reduction ADC sampling instant ground level signal noise of the present invention.In order to realize the synchronized sampling of electric current and voltage, generally all can provide corresponding synchronous control signal for sampling system.At t0 constantly, the system synchronization sampled signal CVT(rising edge of electric current and voltage sampling is effective) be sent to and be responsible for the digital circuit 3 that image data is processed, be the logical devices such as FPGA in the present embodiment.It is effective that FPGA generates the inside synchronous sampling signal CVT_ADC(rising edge or the trailing edge that are used for control simulation digital quantizer 2 synchronized samplings synchronously), the transition status signal CVT_STATE of analog-digital converter 2 correspondingly becomes high level, and analog-digital converter 2 internal conversion circuit are started working.At this moment, the corresponding data exchange control signal DATA_CTRL that FPGA is used for controlling with the external system exchanges data is set to low level, stops and the external system data interaction.In addition, also simultaneously the circuit unit of FPGA is quit work, suspend or idle condition thereby the mode of operation of FPGA is switched to.This state is maintained to t1 constantly.
At t1 constantly, transition status signal CVT_STATE becomes low level, shows that analog-digital converter 2 converts.At this moment, DATA_CTRL is set to high level, the work of FPGA and external system data interaction is recovered, the circuit unit that also makes it front out-of-work FPGA is simultaneously resumed work, thereby FPGA recovers normal condition.Because this moment conversion is finished, can constantly chip selection signal/the CS_ADC of analog-digital converter 2 be set to effectively (low level) at t1, the numeral that analog-digital converter 2 is converted is exported and is delivered to FPGA and process.
At t2 constantly, the data that convert are all delivered to FPGA, and chip selection signal/CS_ADC becomes high level.
At t3 constantly, a change-over period finishes substantially, and system synchronization sampled signal CVT and inner synchronous sampling signal CVT_ADC keep high level, prepare the conversion in next cycle.Receive that until FPGA next system synchronization sampled signal CVT(rising edge is effective) after, the operation in next cycle carried out.
As seen, in the period, analog-digital converter 2 carries out conversion work, and the whole digital circuits in the acquisition module is quit work in this period at t0-t1.Therefore, it is minimum that the noise that factor word circuit working produces on the signal ground plane in this time period has reduced to, is conducive to improve the precision of analog-digital converter 2 transformation results.
The above only is the specific embodiment of the present invention, and the present invention can also be applied in the miscellaneous equipment; Size in the above description and quantity all only are informative, and those skilled in the art can select suitable application size according to actual needs, and do not depart from the scope of the present invention.Protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses, and the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claim was defined.
Claims (10)
1. a method that reduces ADC sampling instant ground level signal noise is characterized in that, may further comprise the steps:
When the synchronized sampling control signal of electric current and voltage was effective, the analog-digital converter of sampling system began to carry out conversion, and control switches to the mode of operation of digital circuit in the sampling system and suspends or idle condition;
When analog-digital converter was finished conversion, the mode of operation of digital circuit was recovered normal condition in the control sampling system.
2. method according to claim 1 is characterized in that, the mode of operation of digital circuit is switched to suspend or idle condition comprises: stop described digital circuit with outside data interaction and/or the circuit unit of described digital circuit is quit work.
3. method according to claim 1 is characterized in that, by exported to the state switching signal of digital circuit by analog-digital converter, controls the switching of described digital circuit mode of operation.
4. method according to claim 1 is characterized in that, and is effective by making digital circuit export the chip selection signal of analog-digital converter to when the mode of operation of digital circuit is recovered normal condition, the numeral output of reading analog-digital converter.
5. an ADC sampling system comprises digital circuit and analog-digital converter, it is characterized in that,
Described digital circuit is used for synchronized sampling control signal at electric current and voltage and controls described analog-digital converter when effective and begin to carry out conversion;
Described analog-digital converter switches to time-out or idle condition for the mode of operation of controlling described digital circuit when beginning to carry out conversion, and controls the mode of operation recovery normal condition of described digital circuit when finishing conversion.
6. ADC sampling system according to claim 5; it is characterized in that, described analog-digital converter switches to the mode of operation of digital circuit and suspends or idle condition comprises: stop described digital circuit with outside data interaction and/or the circuit unit of described digital circuit is quit work.
7. ADC sampling system according to claim 5 is characterized in that, described analog-digital converter is used for the switching state switching signal of control figure circuit working pattern to digital circuit output.
8. ADC sampling system according to claim 5, it is characterized in that, described digital circuit is exported chip selection signal to analog-digital converter, and digital circuit when mode of operation is recovered normal condition by making described chip selection signal effective, read the numeral output of analog-digital converter.
9. ADC sampling system according to claim 5 is characterized in that, described digital circuit is fpga logic circuit, CPLD logical circuit, CPU or DSP.
10. ADC sampling system according to claim 5 is characterized in that, described ADC sampling system also comprises the analog signal conditioner circuit, is used for analog signals is carried out preliminary treatment.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105703774A (en) * | 2015-12-31 | 2016-06-22 | 峰岹科技（深圳）有限公司 | Sequential logic control method of SAR ADC |
| CN109845111A (en) * | 2016-11-29 | 2019-06-04 | 三垦电气株式会社 | A/d conversion device |
| CN113133091A (en) * | 2019-12-31 | 2021-07-16 | 华为技术有限公司 | Signal receiving method and terminal equipment |
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| CN101335524A (en) * | 2007-06-25 | 2008-12-31 | 上海市闵行中学 | Method for reducing electrical power noise in high-speed ADC application |
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| CN101335524A (en) * | 2007-06-25 | 2008-12-31 | 上海市闵行中学 | Method for reducing electrical power noise in high-speed ADC application |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105703774A (en) * | 2015-12-31 | 2016-06-22 | 峰岹科技（深圳）有限公司 | Sequential logic control method of SAR ADC |
| CN105703774B (en) * | 2015-12-31 | 2019-03-26 | 峰岹科技（深圳）有限公司 | The time series stereodata method of SAR ADC |
| CN109845111A (en) * | 2016-11-29 | 2019-06-04 | 三垦电气株式会社 | A/d conversion device |
| CN113133091A (en) * | 2019-12-31 | 2021-07-16 | 华为技术有限公司 | Signal receiving method and terminal equipment |
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