CN106443162A - Device and method for reducing power calculation errors - Google Patents
Device and method for reducing power calculation errors Download PDFInfo
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- CN106443162A CN106443162A CN201611149424.XA CN201611149424A CN106443162A CN 106443162 A CN106443162 A CN 106443162A CN 201611149424 A CN201611149424 A CN 201611149424A CN 106443162 A CN106443162 A CN 106443162A
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- channel
- sampling
- power calculation
- chip microcomputer
- reducing power
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/133—Arrangements for measuring electric power or power factor by using digital technique
Abstract
The invention discloses a sampling device and a sampling method for reducing power calculation errors. Electrical parameters are connected with single chips through high-speed analog switches, a voltage passageway and a corresponding current passageway are switched synchronously, and data of the voltage passageway and the corresponding current passageway are acquired synchronously. The device and the method for reducing power calculation errors have the advantages that by adopting two AD converters of the A/D single chips to work synchronously, working efficiency is increased, sampling time is shortened, executing efficiency of measuring software is increased, phase errors, between the synchronously sampled electrical parameters, caused by sampling can be ignored completely, and increasing of measuring precision is realized.
Description
Technical field
The present invention relates to electronic information field, relates generally to a kind of sampling apparatuses for reducing power calculation error and method.
Background technology
Measure and control device in power system such as microcomputer protective relay, electric intelligent instrument etc., in its electric measurement parameter
Three-phase power measurement be a requisite measurement parameter, and determine the factor of power measurement parameters precision mainly comprising adopting
Sample density, A/D conversion speed, sample mode and sampling transmitter one/secondary side phase offset, the phase offset of transmitter is solid
Fixed, can be compensated by software, in the case that sampling density, A/D conversion speed determine, reasonably optimizing sample mode is
The important means of one raising power measurement parameters precision, the shortcoming of existing sample mode is:As sample mode is order
Sampling, it is that needs are time consuming that A/D often changes a secondary data, but actually due to sample mode and the shadow of sample conversion time
Ring, it may appear that sampled time skew, this time difference can produce phase contrast, so as to cause power calculation Enlarging-Errors.
Therefore, prior art has yet to be improved and developed.
Content of the invention
A kind of in view of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide sampling for reducing power calculation error
Apparatus and method, it is intended to which the impact for solving the prior art method of sampling due to sample mode and sample conversion time is so as to cause work(
The problem that rate calculation error expands.
Technical scheme is as follows:
A kind of method of sampling for reducing power calculation error, wherein, comprises the following steps:
S1:Synchronism switching connection voltage channel and corresponding current channel;
S2:Synchronous acquisition voltage channel and the data of corresponding circuit path.
A kind of sampling apparatuses for reducing power calculation error, wherein, including:Channel Synchronous handover module and channel data are same
Step sampling module;
Channel Synchronous handover module:For synchronism switching voltage channel and current channel;
Channel data synchronized sampling module:It is connected with the Channel Synchronous handover module, for gathering the channel data.
The sampling apparatuses of described reduction power calculation error, wherein, described Channel Synchronous handover module includes:First
High-speed analog switch, the second high-speed analog switch;Described channel data synchronized sampling module includes:Single-chip microcomputer.
The sampling apparatuses of described reduction power calculation error, wherein, the single-chip microcomputer is double A/D single-chip microcomputer.
Beneficial effect:It is contemplated that shortening the sampling time, phase error is eliminated, certainty of measurement is improved, two panels AD is simultaneously
Conversion, its efficiency is 2 times of 1 AD, shortens the sampling time, improves the execution efficiency of Survey Software, and is synchronously adopted
Two electric parameters of sample are negligible completely due to the phase error that brings of sampling, so as to reach the mesh for improving certainty of measurement
's.
Description of the drawings
Fig. 1 is the schematic block circuit diagram of the present invention.
Fig. 2 is the schematic block circuit diagram of embodiment 2.
Fig. 3 is method of the present invention flow chart.
Fig. 4 is the Channel Synchronous switching truth table of the present invention.
Specific embodiment
The present invention provides a kind of sampling apparatuses for reducing power error and method, for making the purpose of the present invention, technical scheme
And effect is clearer, clear and definite, the present invention is described in more detail below, it will be appreciated that described herein is embodied as
Example is not intended to limit the present invention only in order to explain the present invention.
Embodiment 1
A kind of method of sampling for reducing power calculation error provided by the present invention, electric parameter is connected by high-speed analog switch
Single-chip microcomputer, synchronism switching connection voltage channel and corresponding current channel, synchronous acquisition voltage channel and corresponding
The data of circuit path, specifically, as shown in figure 3, comprise the following steps:
S1:Synchronism switching connection voltage channel and corresponding current channel;
S2:Synchronous acquisition voltage channel and the data of corresponding circuit path.
P1.0=0, P1.1=0, P1.2=0, P1.3=0 of single-chip microcomputer, in practical operation, when Channel Synchronous switch, are set,
While analog channel Ua and Ia is gated, Ua and Ia signal is made while the synchronization for reaching ADC0 and ADC1, Ub and Ib, Uc and Ic is cut
Change, referring to Fig. 4.
In practical operation, when channel data synchronized sampling, after analogue signal synchronism switching to converter input, lead to
Cross software and start ADC0 and ADC1 while conversion.
A kind of sampling apparatuses for reducing power calculation error, wherein, including:Channel Synchronous handover module, the passage is same
Step handover module includes the first high-speed analog switch, the second high-speed analog switch, when the first high-speed analog switch starts switching,
Second high-speed analog switch synchronism switching;
Preferably, the P1.3 of single-chip microcomputer is simultaneously connected to the INH1 and INH2 of high-speed analog switch, the P1.0 of single-chip microcomputer,
P1.1, P1.2 are simultaneously connected to A0, A1, A2 of two panels high-speed analog switch respectively, and voltage signal Ua, Ub, Uc are high by first
Fast analog switch accesses Chip Microcomputer A/D C0, as shown in figure 1, current signal Ia, Ib, Ic access list by the second high-speed analog switch
Ia has also been switched to ADC1 while switching Ua to ADC0 by piece machine ADC1.
Channel data synchronized sampling module includes single-chip microcomputer:When Chip Microcomputer A/D C0 starts sampling, Chip Microcomputer A/D C1 starts
Synchronized sampling.
In practical operation, timing sampling mode is sampled as, such as 24 point samplings, every 833 microseconds, all analog quantitys are adopted
Sample once, after having gathered at 24 points, the data of at this moment acquired complete 1 cycle, Ran Houjin for the power frequency component of 50HZ
Row data are calculated.
A kind of sampling apparatuses for reducing power calculation error, wherein, the single-chip microcomputer uses double A/D single-chip microcomputer, double
Change while A/D single-chip microcomputer two panels AD, its efficiency is 2 times of 1 AD, shortens the sampling time, improves Survey Software
Execution efficiency.
2 the invention will be further described by the following examples.
Embodiment 2
As shown in Fig. 2 the device includes 1 analog switch of converter+2 of single-chip microcomputer+2, the difference of the present invention is contrasted
It is to instead of the built-in AD of two panels of single-chip microcomputer with the external AD of two panels, external A/D converter price is higher, improves device and sets
Meter cost, the extraction of data/address bus, cause capacity of resisting disturbance and stability all to decrease relatively, and increased overall disappearing
Consumption.
It should be appreciated that the application of the present invention is not limited to above-mentioned citing, and for those of ordinary skills, can
To be improved according to the above description or convert, all these modifications and variations should all belong to the guarantor of claims of the present invention
Shield scope.
Claims (4)
1. a kind of reduce power calculation error the method for sampling, it is characterised in that comprise the following steps:
S1:Synchronism switching connection voltage channel and corresponding current channel;
S2:Synchronous acquisition voltage channel and the data of corresponding circuit path.
2. a kind of reduce power calculation error sampling apparatuses, it is characterised in that include:Channel Synchronous handover module and port number
According to synchronized sampling module;
Channel Synchronous handover module:For synchronism switching voltage channel and current channel;
Channel data synchronized sampling module:It is connected with the Channel Synchronous handover module, for channel data described in synchronous acquisition.
3. according to claim 2 reduce power calculation error sampling apparatuses, it is characterised in that described Channel Synchronous
Handover module includes:First high-speed analog switch, the second high-speed analog switch;Described channel data synchronized sampling module bag
Include:Single-chip microcomputer.
4. according to claim 3 reduce power calculation error sampling apparatuses, it is characterised in that the single-chip microcomputer is double
A/D single-chip microcomputer.
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CN201611149424.XA CN106443162A (en) | 2016-12-14 | 2016-12-14 | Device and method for reducing power calculation errors |
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CN201611149424.XA CN106443162A (en) | 2016-12-14 | 2016-12-14 | Device and method for reducing power calculation errors |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109358229A (en) * | 2018-09-28 | 2019-02-19 | 深圳市中电电力技术股份有限公司 | A kind of power adaptive calculation method, system and storage medium |
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