CN206258515U

CN206258515U - A kind of device for reducing power calculation error

Info

Publication number: CN206258515U
Application number: CN201621367496.7U
Authority: CN
Inventors: 毛志明
Original assignee: FOSHAN CREDIBLE ELECTRIC TECHNOLOGY Co Ltd
Current assignee: Guangdong Keruide Electric Technology Co., Ltd.
Priority date: 2016-12-14
Filing date: 2016-12-14
Publication date: 2017-06-16
Anticipated expiration: 2026-12-14

Abstract

The utility model discloses a kind of sampling apparatus for reducing power calculation error, including：Channel Synchronous handover module and channel data synchronized sampling module, Channel Synchronous handover module are connected with channel data synchronized sampling module, and Channel Synchronous handover module includes：First high-speed analog switch, the second high-speed analog switch；Channel data synchronized sampling module includes：Single-chip microcomputer, the present apparatus is changed simultaneously using two panels AD, its efficiency is 1 the 2 of AD times, shorten the sampling time, improve the execution efficiency of Survey Software, and by two electric parameters of synchronized sampling because the phase error that sample strip comes can be ignored completely, the purpose of certainty of measurement is improved so as to reach.

Description

A kind of device for reducing power calculation error

Technical field

The utility model is related to electronic information field, relates generally to a kind of sampling apparatus for reducing power calculation error.

Background technology

Measure and control device such as microcomputer protective relay, electric intelligent instrument etc. in power system, in its electric measurement parameter Three-phase power measurement be an essential measurement parameter, and determine the factor of power measurement parameters precision mainly comprising adopting Sample density, A/D conversion speeds, sample mode and sampling transmitter one/secondary side phase offset, the phase offset of transmitter is solid Fixed, can be compensated by software, in the case where sampling density, A/D conversion speeds determine, reasonably optimizing sample mode is One important means of raising power measurement parameters precision, the shortcoming of existing sample mode is：Because sample mode is order Sampling, it is that needs are time consuming that A/D often changes a secondary data, but actually due to sample mode and the shadow of sample conversion time Ring, it may appear that sampled time skew, this time difference can produce phase difference, so as to cause power calculation Enlarging-Errors.

Therefore, prior art has yet to be improved and developed.

Utility model content

In view of above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide a kind of reduction power calculation error Sampling apparatus and method, it is intended to solve the prior art method of sampling because the influence of sample mode and sample conversion time is so as to lead Cause the problem of power calculation Enlarging-Errors.

The technical solution of the utility model is as follows：

A kind of sampling apparatus for reducing power calculation error, wherein, including：Channel Synchronous handover module and channel data are same Step sampling module；

Channel Synchronous handover module：For synchronism switching voltage channel and current channel；

Channel data synchronized sampling module：It is connected with the Channel Synchronous handover module, for gathering the channel data.

The sampling apparatus of described reduction power calculation error, wherein, described Channel Synchronous handover module includes：First High-speed analog switch, the second high-speed analog switch；Described channel data synchronized sampling module includes：Single-chip microcomputer.

The sampling apparatus of described reduction power calculation error, wherein, the single-chip microcomputer is double A/D single-chip microcomputer.

Beneficial effect：The utility model is intended to shorten the sampling time, eliminates phase error, improves certainty of measurement, two panels AD Change simultaneously, its efficiency is 1 the 2 of AD times, shortens the sampling time, improves the execution efficiency of Survey Software, and same Two electric parameters of sampling are walked because the phase error that sample strip comes can be ignored completely, so as to reach raising certainty of measurement Purpose.

Brief description of the drawings

Fig. 1 is schematic block circuit diagram of the present utility model.

Fig. 2 is the schematic block circuit diagram of embodiment 2.

Fig. 3 is method flow diagram of the present utility model.

Fig. 4 is that Channel Synchronous of the present utility model switch truth table.

Specific embodiment

The utility model provides a kind of sampling apparatus for reducing power error, to make the purpose of this utility model, technical side Case and effect are clearer, clear and definite, the utility model are further described below, it will be appreciated that tool described herein Body embodiment is only used to explain the utility model, is not used to limit the utility model.

Embodiment 1

A kind of sampling apparatus for reducing power calculation error provided by the utility model, wherein, including：Channel Synchronous are cut Mold changing block and channel data synchronized sampling module, Channel Synchronous handover module include：First high-speed analog switch, the second high speed mould Intend switch；Channel data synchronized sampling module includes：Single-chip microcomputer, electric parameter connects single-chip microcomputer by high-speed analog switch, together Step switching connection voltage channel and corresponding current channel, synchronous acquisition voltage channel and corresponding circuit path Data, specifically, as shown in figure 3, comprising the following steps：

S1：Synchronism switching connects voltage channel and corresponding current channel；

S2：The data of synchronous acquisition voltage channel and corresponding circuit path.

In practical operation, when Channel Synchronous switch, P1.0=0, P1.1=0, P1.2=0, P1.3=0 of single-chip microcomputer are set, Analog channel Ua and Ia are gated simultaneously, and the synchronization for making Ua and Ia signals reach ADC0 and ADC1, Ub and Ib, Uc and Ic simultaneously is cut Change, referring to Fig. 4.

In practical operation, when channel data synchronized sampling, after analog signal synchronism switching to converter input, lead to Cross software and start ADC0 and ADC1 conversions simultaneously.

Preferably, the P1.3 of single-chip microcomputer is connected to INH1 and the INH2 interface of high-speed analog switch simultaneously, single-chip microcomputer P1.0, P1.1, P1.2 are connected to A0, A1, A2 of two panels high-speed analog switch simultaneously respectively, and voltage signal Ua, Ub, Uc are by the One high-speed analog switch accesses Chip Microcomputer A/D C0, as shown in figure 1, current signal Ia, Ib, Ic are connect by the second high-speed analog switch Enter Chip Microcomputer A/D C1 and Ia has also been switched to ADC1 while switching Ua to ADC0.

In practical operation, timing sampling mode is sampled as, such as 24 point samplings are adopted every 833 microseconds to all analog quantitys Sample once, after having gathered at 24 points, the data of at this moment acquired complete 1 cycle, Ran Houjin for the power frequency component of 50HZ Row data are calculated.

In practical operation, single-chip microcomputer is changed to be double A/D single-chip microcomputer while double A/D single-chip microcomputer two panels AD, and its efficiency is 1 the 2 of AD times, the sampling time is shortened, improve the execution efficiency of Survey Software.

2 the utility model is described in further detail by the following examples.

Embodiment 2

As shown in Fig. 2 the device includes 1 analog switch of converter+2 of single-chip microcomputer+2, the utility model is contrasted Difference be the built-in AD of two panels that single-chip microcomputer is instead of with the external AD of two panels, external A/D converter price is higher, improve Device design cost, the extraction of data/address bus causes antijamming capability and stability all to decrease relatively, and increased Overall consumption.

It should be appreciated that application of the present utility model is not limited to above-mentioned citing, those of ordinary skill in the art are come Say, can according to the above description be improved or converted, all these modifications and variations should all belong to the appended power of the utility model The protection domain that profit is required.

Claims

1. it is a kind of reduce power calculation error sampling apparatus, it is characterised in that including：Channel Synchronous handover module and port number According to synchronized sampling module；

Channel data synchronized sampling module：It is connected with the Channel Synchronous handover module, for channel data described in synchronous acquisition.

2. it is according to claim 1 reduce power calculation error sampling apparatus, it is characterised in that described Channel Synchronous Handover module includes：First high-speed analog switch, the second high-speed analog switch；Described channel data synchronized sampling module bag Include：Single-chip microcomputer.

3. it is according to claim 2 reduce power calculation error sampling apparatus, it is characterised in that the single-chip microcomputer is double A/D single-chip microcomputers.