CN102945856A - Reverse conducting IGBT (insulated gate bipolar transistor) structure and preparation method thereof - Google Patents
Reverse conducting IGBT (insulated gate bipolar transistor) structure and preparation method thereof Download PDFInfo
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- CN102945856A CN102945856A CN2012104248666A CN201210424866A CN102945856A CN 102945856 A CN102945856 A CN 102945856A CN 2012104248666 A CN2012104248666 A CN 2012104248666A CN 201210424866 A CN201210424866 A CN 201210424866A CN 102945856 A CN102945856 A CN 102945856A
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Abstract
The invention relates to a reverse conducting IGBT (insulated gate bipolar transistor) structure and a preparation method of the reverse conducting IGBT structure. The reverse conducting IGBT structure comprises a semiconductor liner, a liner front surface structure and a liner back surface structure, wherein the liner front surface structure and an existing IGBT structure are the same; the liner back surface structure comprises a third p-type area, a fourth p-type area, an aluminum metal layer, a vanadium metal layer, a nickel metal layer and a silver metal layer; the third p-type area and the fourth p-type area are located at the bottom of the semiconductor liner and are separated by the semiconductor liner; the aluminum metal layer, the vanadium metal layer, the nickel metal layer and the silver metal layer are sequentially deposited at the bottom of the semiconductor liner; the processing method of the liner front surface structure of the reverse conducting IGBT structure and a preparation method of a common reverse conducting IGBT structure are the same, ion implantation is carried out for only once during the back surface processing, and the original titanium metal is replaced by the vanadium metal. The reverse conducting IGBT structure is good in conduction characteristic, small in snapback effect and total area, high in packaging reliability and low in packaging cost; and the preparation method is simple and the processing cost is low.
Description
Technical field
The present invention relates to a kind ofly contrary lead IGBT structure and preparation method thereof, belong to field of semiconductor.
Background technology
IGBT(Insulated Gate Bipolar Transistor) insulated gate bipolar transistor, by the compound full-control type voltage driven type power semiconductor that BJT (double pole triode) and MOS (insulating gate type field effect tube) form, have the advantage of low conduction voltage drop two aspects of the high input impedance of MOSFET and GTR concurrently.
IGBT usually is combined use with diode, the effect of diode is the effect of playing a kind of afterflow in the IGBT shutoff, is used for the energy of dump load, to guarantee the safe handling of I GBT.IGBT inverter structure commonly used has two kinds at present: a kind of is that IGBT and the fly-wheel diode inverse parallel that separates used.Its shortcoming has: 1 two the chip area summation is large, cost is higher; 2 areas cause greatly packaging cost to promote; Realize interconnectedly between the 3 encapsulation process chips with the aluminium wire bonding, number of chips determines the bonding point quantity of aluminium wire, and the risk of reliability failures is increased.Another kind is existingly to lead IGBT by integrated contrary of IGBT and fly-wheel diode, and its advantage is: discrete device more originally relatively, area reduces greatly, packaging cost dwindles, and package reliability improves; Shortcoming is: because the problem of back of the body end technique and design causes the device on-state voltage drop higher, and have " snapback " effect in turn on process, on state characteristic is poor, and its characteristic is not as good as the situation of discrete device.
Existingly contrary lead the IGBT structure as shown in Figure 1, comprise Semiconductor substrate 100, substrate face structure and substrate back structure, described substrate face structure is positioned at the front of Semiconductor substrate, and the substrate back structure is positioned at the back side of Semiconductor substrate; Described substrate face structure comprises the first p-type district 101, the second p-type district 102, a n+ district 103 and the 2nd n+ district 104, described the first p-type district 101 and the second p-type district 102 are positioned at the end face of Semiconductor substrate 100, and kept apart by Semiconductor substrate 100 parts, a described n+ district 103 is positioned at 101, the two n+ districts 104, the first p-type district and is positioned at the second p-type district 102; Described substrate back structure comprises the 3rd p-type district 105, the 3rd n+ district 107 and the 4th p-type district 106 aluminum metal layers 108, vanadium gold layer 109, nickel metal layer 110 and silver metal layer 111, described the 3rd p-type district 105, the 3rd n+ district 107 and the 4th p-type district 106 are positioned at the bottom of Semiconductor substrate 100, and the 3rd p-type district 105, the 3rd n+ district 107 and the 4th p-type district 106 alternative arrangements, and its lower surface is on the same level, described the 3rd p-type district 105, the 3rd n+ district 107 and 106 bottoms, the 4th p-type district are deposited with aluminum metal layer 108, titanium coating 109 successively, nickel metal layer 110 and silver metal layer 111.
Its preparation method is: at first, process 1 in the front of substrate, mixing heat growth SIO2 film on the n silicon substrate 100 of phosphorus, 2, mask, etching, B Implanted and propelling form guard ring, 3, B Implanted, annealing form P-N knot, 4, mask, etching is injected phosphorus and propelling and is reduced JFET resistance, 5, gate oxidation, 6, depositing polysilicon, 7, mask, etching, B Implanted and propelling form the first p-type district 101 and the second p-type district 102,8, mask, etching is injected phosphorus and is advanced formation the one n+ district 103 and the 2nd n+ district 104,9, silester and boron-phosphorosilicate glass deposit, 10, mask, etching forms electrode contact, 11, deposit aluminium, 12, mask, etching aluminium, 13, deposit SiO2 and Si3N4,14, mask, etching forms passivation protection; Secondly, the back side at substrate processes, 1, back of the body end corrosion, 2, inject phosphorus and advance and form the 3rd n+ district 107,3, mask, etching, B Implanted and advance to form the 3rd p district 105 and the 4th p district 106,4, deposit aluminum metal layer 108 successively, titanium coating 109, nickel metal layer 110, silver metal layer 111 forms contact layer.
Existing contrary the 3rd n+ district 107 that leads in the IGBT structure is for reducing the on-state voltage drop of this structure, but the existence in the 3rd n+ district 107 aggravates existing contrary " snapback " effect of leading I GBT structure, causes this against the on state characteristic variation of leading the IGBT structure.Make in addition this contrary back side processing technology complexity of leading the IGBT structure, need twice Implantation, processing cost is high.
Summary of the invention
Technical problem to be solved by this invention is the deficiency that exists for prior art, a kind of contrary IGBT structure and preparation method thereof of leading is provided, this structure gross area is little, package reliability is high, packaging cost is low,, electrical characteristics are reliable, on-state voltage drop is low, alleviated " snapback " effect, has identical function with separating chips; Its complicated process of preparation is low, and processing cost is low.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of contrary IGBT structure of leading, comprise Semiconductor substrate, substrate face structure and substrate back structure, described substrate face structure is positioned at the front of Semiconductor substrate, and the substrate back structure is positioned at the back side of Semiconductor substrate; Described substrate face structure comprises the first p-type district, the second p-type district, a n+ district and the 2nd n+ district, described the first p-type district and the second p-type district are positioned at the end face of Semiconductor substrate, and partly kept apart by Semiconductor substrate, a described n+ district is positioned at the first p-type district, and the 2nd n+ district is positioned at the second p-type district; Described substrate back structure comprises the 3rd p-type district, the 4th p-type district, aluminum metal layer, vanadium gold floor, nickel metal layer and silver metal floor, described the 3rd p-type district and the 4th p-type district are positioned at the bottom of Semiconductor substrate, and partly kept apart by Semiconductor substrate, described Semiconductor substrate bottom is deposited with aluminum metal layer, vanadium metal layer, nickel metal layer and silver metal layer successively.
On the basis of technique scheme, the present invention can also do following improvement.
Further, described Semiconductor substrate is to mix the n silicon substrate of phosphorus.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of contrary preparation method who leads the IGBT structure, and concrete steps are as follows:
Step 1: carry out conventional machining in the Semiconductor substrate front: 1, mixing heat growth SIO2 film on the n silicon substrate of phosphorus, 2, mask, etching, B Implanted and propelling form guard ring, 3, B Implanted, annealing form the P-N knot, 4, mask, etching is injected phosphorus and propelling and is reduced JFET resistance, 5, gate oxidation, 6, depositing polysilicon, 7, mask, etching, B Implanted and propelling form the first p-type district and the second p-type district, 8, mask, etching is injected phosphorus and is advanced formation the one n+ district and the 2nd n+ district, 9, silester and boron-phosphorosilicate glass deposit, 10, mask, etching forms electrode contact, 11, deposit aluminium, 12, mask, etching aluminium, 13, deposit SiO2 and Si3N4,14, mask, etching forms passivation protection;
Step 2: process at the Semiconductor substrate back side, concrete steps are as follows:
Step 2.1: corrode at the Semiconductor substrate back side;
Step 2.2: mask is carried out in the Semiconductor substrate bottom after corrosion, etching processing, and B Implanted and propelling form the 3rd p-type district and the 4th p-type district;
Step 2.3: in the bottom of the Semiconductor substrate after above-mentioned processing successively deposit aluminum metal layer, the vanadium metal layer, nickel metal layer, the silver metal layer forms contact layer.
Further, after corroded at the Semiconductor substrate back side in the described step 2.1, the reservation substrate thickness was 150-190um.
Further, the boron implantation dosage is 3e14 in the described step 2.2, and required Implantation Energy is 80kev.
Further, the thickness of aluminum metal layer, vanadium metal layer, nickel metal layer, silver metal layer is followed successively by 80nm, 100nm, 300nm, 1000nm in the described step 2.3.
The invention has the beneficial effects as follows: to send out described contrary leads the IGBT structure and have that the conventional contrary gross area of leading the IGBT structure is little, package reliability is high for this, the advantage that packaging cost is low, simultaneously by adopting the deposit vanadium metal to replace original deposit titanium to strengthen bonding strength between the metal level, thereby on-state voltage drop and the reliability of device have been improved, in addition, the employing primary ions is injected, replace the 3rd n+ district of injecting with original n district (part of Semiconductor substrate), alleviated " snapback " effect; And its preparation method has reduced the complexity of back of the body end manufacture craft, saves primary ions and injects, and has reduced processing cost.
Description of drawings
Fig. 1 is the conventional contrary IGBT structural representation of leading;
Fig. 2 is the contrary IGBT structural representation of leading of the present invention;
Fig. 3 is preparation contrary method flow diagram of leading the IGBT structure of the present invention;
Fig. 4 is the method flow diagram of the substrate back of preparation described in Fig. 3 structure;
Fig. 5 is IGBT and the fly-wheel diode inverse parallel structure, conventional against leading IGBT structure and contrary " snapback " effect curve figure that leads the IGBT structure of the present invention of existing separation.
In the accompanying drawing, the list of parts of each label representative is as follows:
100, Semiconductor substrate, the 101, first p-type district, the 102, second p-type district, 103, a n+ district, 104, the 2nd n+ district, the 105, the 3rd p-type district, the 106, the 4th p-type district, 107, the 3rd n+ district, 108, aluminum metal layer, 109, titanium coating, 110, nickel metal layer, 111, silver metal layer, 112, the vanadium metal layer.
Embodiment
Below in conjunction with accompanying drawing principle of the present invention and feature are described, institute gives an actual example and only is used for explaining the present invention, is not be used to limiting scope of the present invention.
As shown in Figure 2, a kind of contrary IGBT structure of leading of the present invention, comprise Semiconductor substrate 100, substrate face structure and substrate back structure, described substrate face structure is positioned at the front of Semiconductor substrate 100, and the substrate back structure is positioned at the back side of Semiconductor substrate 100; Described substrate face structure comprises the first p-type district 101, the second p-type district 102, a n+ district 103 and the 2nd n+ district 104, described the first p-type district 101 and the second p-type district 102 are positioned at the end face of Semiconductor substrate 100, and kept apart by Semiconductor substrate 100 parts, a described n+ district 103 is positioned at 101, the two n+ districts 104, the first p-type district and is positioned at the second p-type 102 districts; Described substrate back structure comprises the 3rd p-type district 105, the 4th p-type district 106, aluminum metal layer 108, vanadium gold floor 112, nickel metal layer 110 and silver metal floor 111, described the 3rd p-type district 105 and the 4th p-type district 106 are positioned at the bottom of Semiconductor substrate 100, and kept apart by Semiconductor substrate 100 parts, described Semiconductor substrate 100 bottoms are deposited with aluminum metal layer 108 successively, vanadium metal layer 112, nickel metal layer 110 and silver metal layer 111.
Fig. 3, shown in Figure 4, a kind of contrary preparation method who leads the IGBT structure, concrete steps are as follows:
Step 1: carry out conventional machining in Semiconductor substrate 110 fronts: 1, mixing heat growth SIO2 film on the n silicon substrate of phosphorus, 2, mask, etching, B Implanted and propelling form guard ring, 3, B Implanted, annealing form the P-N knot, 4, mask, etching is injected phosphorus and propelling and is reduced JFET resistance, 5, gate oxidation, 6, depositing polysilicon, 7, mask, etching, B Implanted and propelling form the first p-type district 101 and the second p-type district 102,8, mask, etching is injected phosphorus and is advanced formation the one n+ district 103 and the 2nd n+ district 104,9, silester and boron-phosphorosilicate glass deposit, 10, mask, etching forms electrode contact, 11, deposit aluminium, 12, mask, etching aluminium, 13, deposit SiO2 and Si3N4,14, mask, etching forms passivation protection;
Step 2: process at Semiconductor substrate 100 back sides, concrete steps are as follows:
Step 2.1: corrode at Semiconductor substrate 100 back sides;
Step 2.2: mask is carried out in Semiconductor substrate 100 bottoms after corrosion, etching processing, and B Implanted and propelling form the 3rd p-type district 105 and the 4th p-type district 106;
Step 2.3: in Semiconductor substrate 100 bottoms after above-mentioned processing successively deposit aluminum metal layer 108, vanadium metal layer 112, nickel metal layer 110, silver metal layer 111 forms contact layer.
Wherein, after corroded at the Semiconductor substrate back side in the described step 2.1, the reservation substrate thickness was 150-190um.
Wherein, the boron implantation dosage is 3e14 in the described step 2.2, and required Implantation Energy is 80kev.
Wherein, the thickness of aluminum metal layer, vanadium metal layer, nickel metal layer, silver metal layer is followed successively by 80nm, 100nm, 300nm, 1000nm in the described step 2.3.
A kind of contrary IGBT structure of leading of the present invention is conventionally contraryly led the IGBT structure and is compared with existing, and the substrate face structure is identical, and its structure has been saved original the 3rd n+ district 107, and in the metal level of accumulation with 109 layers of titaniums with 112 replacement of vanadium metal layer.Wherein, employing vanadium metal layer 112 replacement titanium coating 109 have strengthened the degree of adhesion between the metal level, effectively improved contrary on-state voltage drop and the reliability of leading the IGBT structure, saved simultaneously original the 3rd n+ district 107 and effectively alleviated contrary " snapback " effect of leading the IGBT structure.
This contrary method substrate face structure processing technology of leading the IGBT structure of preparation of the present invention is identical with existing conventional substrate face processing technology, substrate back structure processing technology is saved primary ions and is injected on the basis of original technique, namely do not inject phosphorus and form the 3rd n+ district 107, to replace the nickel metal with vanadium metal at the accumulation metal level simultaneously, vanadium metal can play the contrary function of IGBT structure on-state voltage drop of leading of original the 3rd n+ district 107 reductions like this, can alleviate contrary " snapback " effect of leading the IGBT structure simultaneously.
IGBT and the fly-wheel diode inverse parallel structure, conventional against lead IGBT structure and of the present invention contrary " snapback " effect curve figure that lead IGBT structure of Fig. 5 for separating, by finding out among the figure, the IGBT that separates and " snapback " effect of diode structure are more satisfactory, the conventional contrary IGBT structure of leading is than then " snapback " effect aggravation of isolating construction, and the contrary IGBT structure of leading of the present invention has been alleviated conventional contrary " snapback " effect of leading the IGBT structure.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. contrary lead the IGBT structure for one kind, it is characterized in that, comprise Semiconductor substrate, substrate face structure and substrate back structure, described substrate face structure is positioned at the front of Semiconductor substrate, and the substrate back structure is positioned at the back side of Semiconductor substrate; Described substrate face structure comprises the first p-type district, the second p-type district, a n+ district and the 2nd n+ district, described the first p-type district and the second p-type district are positioned at the end face of Semiconductor substrate, and partly kept apart by Semiconductor substrate, a described n+ district is positioned at the first p-type district, and the 2nd n+ district is positioned at the second p-type district; Described substrate back structure comprises the 3rd p-type district, the 4th p-type district, aluminum metal layer, vanadium gold floor, nickel metal layer and silver metal floor, described the 3rd p-type district and the 4th p-type district are positioned at the bottom of Semiconductor substrate, and partly kept apart by Semiconductor substrate, described Semiconductor substrate bottom is deposited with aluminum metal layer, vanadium metal layer, nickel metal layer and silver metal layer successively.
2. describedly according to claim 1 a kind ofly contrary lead the IGBT structure, it is characterized in that, described Semiconductor substrate is to mix the n silicon substrate of phosphorus.
3. one kind prepares the described contrary method of leading the IGBT structure of claim 1, it is characterized in that, concrete steps are as follows:
Step 1: carry out conventional machining in the Semiconductor substrate front;
Step 2: process at the Semiconductor substrate back side, concrete steps are as follows:
Step 2.1: corrode at the Semiconductor substrate back side;
Step 2.2: mask is carried out in the Semiconductor substrate bottom after corrosion, etching processing, and B Implanted and propelling form the 3rd p-type district and the 4th p-type district;
Step 2.3: in the bottom of the Semiconductor substrate after above-mentioned processing successively deposit aluminum metal layer, the vanadium metal layer, nickel metal layer, the silver metal layer forms contact layer.
4. describedly according to claim 3 a kind ofly contrary lead the IGBT structure, it is characterized in that, after corroded at the Semiconductor substrate back side in the described step 2.1, the reservation substrate thickness was 150-190um.
5. describedly according to claim 3 a kind ofly contrary lead the IGBT structure, it is characterized in that, the boron implantation dosage is 3e14 in the described step 2.2, and required Implantation Energy is 80kev.
6. describedly according to claim 3 a kind ofly contrary lead the IGBT structure, it is characterized in that, the thickness of aluminum metal layer, vanadium metal layer, nickel metal layer, silver metal layer is followed successively by 80nm, 100nm, 300nm, 1000nm in the described step 2.3.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544273A (en) * | 2023-07-07 | 2023-08-04 | 深圳平创半导体有限公司 | Reverse conducting-junction gate bipolar transistor device and manufacturing method thereof |
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|---|---|---|---|---|
| US5485022A (en) * | 1993-07-12 | 1996-01-16 | Kabushiki Kaisha Toshiba | High switching speed IGBT |
| US6562705B1 (en) * | 1999-10-26 | 2003-05-13 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing semiconductor element |
| US20050227461A1 (en) * | 2000-05-05 | 2005-10-13 | International Rectifier Corporation | Semiconductor device having increased switching speed |
| CN102683404A (en) * | 2012-05-22 | 2012-09-19 | 上海宏力半导体制造有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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2012
- 2012-10-30 CN CN2012104248666A patent/CN102945856A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5485022A (en) * | 1993-07-12 | 1996-01-16 | Kabushiki Kaisha Toshiba | High switching speed IGBT |
| US6562705B1 (en) * | 1999-10-26 | 2003-05-13 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing semiconductor element |
| US20050227461A1 (en) * | 2000-05-05 | 2005-10-13 | International Rectifier Corporation | Semiconductor device having increased switching speed |
| CN102683404A (en) * | 2012-05-22 | 2012-09-19 | 上海宏力半导体制造有限公司 | Insulated gate bipolar transistor and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544273A (en) * | 2023-07-07 | 2023-08-04 | 深圳平创半导体有限公司 | Reverse conducting-junction gate bipolar transistor device and manufacturing method thereof |
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Application publication date: 20130227 |