CN102945849A - Semiconductor capacitor structure and manufacture method thereof - Google Patents
Semiconductor capacitor structure and manufacture method thereof Download PDFInfo
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- CN102945849A CN102945849A CN2012105071625A CN201210507162A CN102945849A CN 102945849 A CN102945849 A CN 102945849A CN 2012105071625 A CN2012105071625 A CN 2012105071625A CN 201210507162 A CN201210507162 A CN 201210507162A CN 102945849 A CN102945849 A CN 102945849A
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Abstract
The invention provides a semiconductor capacitor structure and a manufacture method thereof. The semiconductor capacitor structure comprises a plurality of semiconductor capacitors, wherein each semiconductor capacitor comprises a semiconductor substrate, a first medium layer, a first polycrystalline silicon layer, a second medium layer, and a second polycrystalline silicon layer, wherein the first medium layer is located at the surface of the semiconductor substrate, the first polycrystalline silicon layer is located at the surface of the first medium layer, the second medium layer is located at the surface of the first polycrystalline silicon layer, the second polycrystalline silicon layer is located at the surfaces of the second medium layer and the first medium layer; one portion of the second medium layers in the semiconductor capacitors have the first thicknesses, the other portion of the second medium layers in the semiconductor capacitors have the second thicknesses, and the first thicknesses are larger than the second thicknesses.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of semiconductor capacitor structure and manufacture method thereof.
Background technology
In existing common nonvolatile memory production technology, need to use the polysilicon of multilayer different process step.Polycrystalline silicon-on-insulator-polysilicon (PIP, the Poly-Insulator-Poly) capacitor that develops thus and polysilicon-polysilicon silicon-substrate (PPS, Poly-Poly-Substrate) capacitor are also extensively used as capacitor element.
Fig. 1 is the structural representation of existing PIP capacitor, comprises Semiconductor substrate 100, and described Semiconductor substrate 100 surfaces are formed with fleet plough groove isolation structure 110; Be positioned at the first medium layer 120 on described fleet plough groove isolation structure 110 surfaces; Be positioned at first polysilicon layer 130 on described first medium layer 120 surface; Be positioned at the second medium layer 140 on described the first polysilicon layer 130 surfaces, and second medium layer 140 covers the sidewall of a side of the first polysilicon layer 130; Be positioned at second polysilicon layer 150 on described second medium layer 140 and first medium layer 120 surface, and described the second polysilicon layer 150 covers the sidewall that second medium layer 140 is positioned at first medium layer 120 surface, the first polysilicon layer 130 part surfaces of an end relative with capped the first polysilicon layer 130 sidewalls are exposed, and the surface of described exposure is formed with the first conductive plunger 170 that is electrically connected with the first polysilicon layer 130, and described the second polysilicon layer 150 surfaces also have the second conductive plunger 180 that is electrically connected with the second polysilicon layer 150.
Fig. 2 is the structural representation of existing PPS capacitor, comprises Semiconductor substrate 200, and described Semiconductor substrate 200 surfaces are formed with dopant well 290, and the fleet plough groove isolation structure 210 that is positioned at described dopant well 290 both sides; Be positioned at the first medium layer 220 on described dopant well 290 surfaces; Be positioned at first polysilicon layer 230 on described first medium layer 220 surface; Be positioned at the second medium layer 240 on described the first polysilicon layer 230 surfaces, described second medium layer 240 covers a sidewall of the first polysilicon layer 230; Be positioned at second polysilicon layer 250 on described second medium layer 240 and first medium layer 220 surface, and described the second polysilicon layer 250 covers the sidewall that second medium layer 240 is positioned at first medium layer 220 surface, the first polysilicon layer 230 part surfaces of an end relative with capped the first polysilicon layer 230 sidewalls are exposed, and the surface of described exposure is formed with the first conductive plunger 270 that is electrically connected with the first polysilicon layer 230, and described the second polysilicon layer 250 surfaces also have the second conductive plunger 280 that is electrically connected with the second polysilicon layer 250.Be the formation method that has disclosed above-mentioned PPS capacitor in the Chinese patent application of CN101937878A and the Chinese patent application that publication number is CN102214702A at publication number.
But, for semiconductor capacitor structure illustrated in figures 1 and 2, if need the capacitor of large capacitance, then must increase the area of above-mentioned PIP/PPS semiconductor capacitor structure.Thus, for the capacitor application of large capacitance, need to expend larger device area.
Summary of the invention
Technical problem to be solved by this invention is for having defects in the prior art, a kind of semiconductor capacitor structure and the manufacture method thereof that can save device area being provided.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of semiconductor capacitor structure, it comprises: a plurality of semiconductor capacitors, wherein each semiconductor capacitor includes: Semiconductor substrate; Be positioned at the first medium layer of described semiconductor substrate surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface; Wherein, the second medium layer of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
Preferably, described semiconductor substrate surface is formed with fleet plough groove isolation structure, and the first medium layer is positioned at described fleet plough groove isolation structure top; Perhaps semiconductor substrate surface does not have fleet plough groove isolation structure, and the first medium layer is positioned at described substrate top.
Preferably, the second medium layer covers the sidewall of a side of the first polysilicon layer; Described the second polysilicon layer covers the sidewall that the second medium layer is positioned at first medium layer surface, the first polysilicon layer part surface of an end relative with capped the first polysilicon layer sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger that is electrically connected with the first polysilicon layer, and described the second polysilicon layer surface also has the second conductive plunger that is electrically connected with the second polysilicon layer;
Wherein, for the semiconductor capacitor structure that is positioned at the substrate top, described substrate surface also has the 3rd conductive plunger that is electrically connected with substrate layer, and the electric capacity that substrate, first medium layer, the first polysilicon layer form is electrically connected and is unified into larger capacitance structure with the electric capacity that the first polysilicon layer, second medium layer, the second polysilicon layer form.
According to a second aspect of the invention, provide a kind of semiconductor capacitor structure manufacture method, it arranges a plurality of semiconductor capacitors simultaneously in being included in chip, and wherein each semiconductor capacitor includes: Semiconductor substrate; Be positioned at the first medium layer of described surface of shallow trench isolation structure or substrate surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface; Wherein, so that the second medium layer of the part in described a plurality of semiconductor capacitor has the first thickness, and so that the second medium layer of the another part in described a plurality of semiconductor capacitor has the second thickness, and described the first thickness is greater than described the second thickness.
Preferably, in having the step of MOS transistor grid oxic horizon of different-thickness, formation forms respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness.
According to a third aspect of the invention we, provide a kind of semiconductor capacitor structure, it comprises: a plurality of semiconductor capacitors, and wherein each semiconductor capacitor includes: Semiconductor substrate, described semiconductor substrate surface is formed with dopant well; Be positioned at the first medium layer on described dopant well surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface; Wherein, the second medium layer of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
Preferably, described semiconductor substrate surface is formed with fleet plough groove isolation structure; Fleet plough groove isolation structure or as the part of described semiconductor capacitor structure as and the isolation of substrate, perhaps be applied to different voltage conditions between the described semiconductor capacitor structure on the substrate as the isolation that differs from one another between the electromotive force dopant well.
Preferably, described second medium layer covers a sidewall of the first polysilicon layer; Described the second polysilicon layer covers the sidewall that the second medium layer is positioned at first medium layer surface, the first polysilicon layer part surface of an end relative with capped the first polysilicon layer sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger that is electrically connected with the first polysilicon layer, and described the second polysilicon layer 250 surfaces also have the second conductive plunger that is electrically connected with the second polysilicon layer 250.
According to a forth aspect of the invention, a kind of semiconductor capacitor structure manufacture method is provided, it is characterized in that being included in and arrange simultaneously a plurality of semiconductor capacitors in the chip, wherein each semiconductor capacitor includes: Semiconductor substrate, and described semiconductor substrate surface is formed with dopant well; Be positioned at the first medium layer on described dopant well surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface; Wherein, so that the second medium layer of the part in described a plurality of semiconductor capacitor has the first thickness, and so that the second medium layer of the another part in described a plurality of semiconductor capacitor has the second thickness, and described the first thickness is greater than described the second thickness.
Preferably, in having the step of MOS transistor grid oxic horizon of different-thickness, formation forms respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness.
According to the present invention by in the semiconductor capacitor structure manufacture process, in chip, arranging simultaneously the semiconductor capacitor with different first medium layer thicknesses, thus, semiconductor capacitor with first medium layer of the first thicker thickness can be used for more high voltage applications, and for the semiconductor capacitor of the first medium layer with second thinner thickness, can realize larger capacitance by less area, a kind of semiconductor capacitor structure that can save device area is provided thus.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the structural representation according to the PIP capacitor of prior art.
Fig. 2 schematically shows the structural representation according to the PPS capacitor of prior art.
Fig. 3 schematically shows the schematic diagram according to the semiconductor capacitor structure of first embodiment of the invention.
Fig. 4 schematically shows the schematic diagram according to the semiconductor capacitor structure of second embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
For PIP capacitor shown in Figure 1 and PPS capacitor shown in Figure 2, its for for example be high-voltage applications, first medium layer 220 shown in Figure 1 and first medium layer 220 shown in Figure 2 must be thicker in can bear high voltage thus, but for some the concrete application in the chip, its voltage that in fact applies is generally less than designed applied voltage (for example less than 5.5V or less).
Therefore, the present inventor advantageously proposes, can in the semiconductor capacitor structure manufacture process, in chip, arrange simultaneously the semiconductor capacitor with different first medium layer thicknesses, thus, semiconductor capacitor with thicker first medium layer can be used for more high voltage applications, and for the semiconductor capacitor with thinner first medium layer, can realize larger capacitance by less area, a kind of semiconductor capacitor structure that can save device area is provided thus.
The＜the first embodiment 〉
Fig. 3 schematically shows the schematic diagram according to the semiconductor capacitor structure of first embodiment of the invention.
As shown in Figure 3, semiconductor capacitor structure according to first embodiment of the invention, it comprises a plurality of semiconductor capacitors, and wherein each semiconductor capacitor includes: Semiconductor substrate 100, and described Semiconductor substrate 100 surfaces preferably are formed with fleet plough groove isolation structure 110,11; Be positioned at the first medium layer 120,12 on described fleet plough groove isolation structure 110,11 surfaces; Be positioned at first polysilicon layer 130,13 on described first medium layer 120,12 surfaces; Be positioned at the second medium layer 140,14 on described the first polysilicon layer 130,13 surfaces, and second medium layer 140,14 covers the sidewall of the first polysilicon layer 130, a side of 13; Be positioned at described second medium layer 140,14 and first medium layer 120, second polysilicon layer 150 on 12 surfaces, 15, and described the second polysilicon layer 150,15 cover second medium layer 140,14 are positioned at first medium layer 120, the sidewall on 12 surfaces, with capped the first polysilicon layer 130, the first polysilicon layer 130 of the end that 13 sidewalls are relative, 13 part surfaces are exposed, and the surface of described exposure is formed with and the first polysilicon layer 130,13 the first conductive plungers 170 that are electrically connected, 17, described the second polysilicon layer 150,15 surfaces also have and the second polysilicon layer 150,15 the second conductive plungers 180 that are electrically connected, 18.
Wherein, replacedly, semiconductor substrate surface may not have fleet plough groove isolation structure, and the first medium layer is positioned at described substrate top.At this moment, for the semiconductor capacitor structure that is located immediately at the substrate top, described substrate surface also has the 3rd conductive plunger (not specifically illustrating this situation in the accompanying drawing) that is electrically connected with substrate layer, and the electric capacity that substrate, first medium layer, the first polysilicon layer form is electrically connected and is unified into larger capacitance structure with the electric capacity that the first polysilicon layer, second medium layer, the second polysilicon layer form.
Wherein, the second medium layer 140 of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer 14 of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
For example, second medium layer 140,14 is the conductor oxidate layer.
Thus, by in the semiconductor capacitor structure manufacture process, in chip, arranging simultaneously the semiconductor capacitor with different first medium layer thicknesses, thus, the semiconductor capacitor of second medium layer 140 that can thicker with having (the first thickness) is used for more high voltage applications, and the semiconductor capacitor of the second medium layer 14 of thinner for having (the second thickness), can realize larger capacitance by less area, a kind of semiconductor capacitor structure that can save device area is provided thus.
And, in corresponding semiconductor capacitor structure manufacture method, the first thickness, the second thickness can utilize respectively the dielectric layer of the different-thickness in the chip production process steps (for example, to form respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness in formation has the step of MOS transistor grid oxic horizon of different-thickness; In other words, the step that formation is had the second medium layer of the first thickness and have a second medium layer of the second thickness is integrated in the step that forms the MOS transistor grid oxic horizon with different-thickness, thereby can not increase extra step and cost), produce simultaneously the purpose that is applicable to high voltage more and saves the semiconductor capacitor structure that is applicable to low voltage of device area thereby realize not increasing additional technology cost.But, if disregard cost, certainly can also utilize other mode to form the second medium layer with first thickness and the second medium layer with second thickness.
The＜the second embodiment 〉
Fig. 4 schematically shows the schematic diagram according to the semiconductor capacitor structure of second embodiment of the invention.
As shown in Figure 4, semiconductor capacitor structure according to first embodiment of the invention, it comprises a plurality of semiconductor capacitors, wherein each semiconductor capacitor includes: Semiconductor substrate 200, described Semiconductor substrate 200 surfaces preferably are formed with dopant well 290,29, and the fleet plough groove isolation structure 210,21 (groove isolation construction 210, the 21st, preferred) that is positioned at described dopant well 290,29 both sides; Be positioned at the first medium layer 220,22 on described dopant well 290,29 surfaces; Be positioned at first polysilicon layer 230,23 on described first medium layer 220,22 surfaces; Be positioned at the second medium layer 240,24 on described the first polysilicon layer 230,23 surfaces, described second medium layer 240,24 covers the first polysilicon layer 230, a sidewall of 23; Be positioned at described second medium layer 240,24 and first medium layer 220, second polysilicon layer 250 on 22 surfaces, 25, and described the second polysilicon layer 250,25 cover second medium layer 240,24 are positioned at first medium layer 220, the sidewall on 22 surfaces, with capped the first polysilicon layer 230, the first polysilicon layer 230 of the end that 23 sidewalls are relative, 23 part surfaces are exposed, and the surface of described exposure is formed with and the first polysilicon layer 230,23 the first conductive plungers 270 that are electrically connected, 27, described the second polysilicon layer 250 surfaces also have the second conductive plunger 280 that is electrically connected with the second polysilicon layer 250,27.
Wherein, the second medium layer 240 of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer 24 of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
For example, second medium layer 240,24 is the conductor oxidate layer.
Wherein, fleet plough groove isolation structure 210,21 or as the part of described semiconductor capacitor structure as and the isolation of substrate, perhaps be applied to different voltage conditions between the described semiconductor capacitor structure on the substrate as the isolation that differs from one another between the electromotive force dopant well.
Thus, by in the semiconductor capacitor structure manufacture process, in chip, arranging simultaneously the semiconductor capacitor with different first medium layer thicknesses, thus, the semiconductor capacitor of second medium layer 240 that can thicker with having (the first thickness) is used for more high voltage applications, and the semiconductor capacitor of the second medium layer 24 of thinner for having (the second thickness), can realize larger capacitance by less area, a kind of semiconductor capacitor structure that can save device area is provided thus.
And, in corresponding semiconductor capacitor structure manufacture method, the first thickness, the second thickness can utilize respectively the dielectric layer of the different-thickness in the chip production process steps (for example, to form respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness in formation has the step of MOS transistor grid oxic horizon of different-thickness; In other words, the step that formation is had the second medium layer of the first thickness and have a second medium layer of the second thickness is integrated in the step that forms the MOS transistor grid oxic horizon with different-thickness, thereby can not increase extra step and cost), produce simultaneously the purpose that is applicable to high voltage more and saves the semiconductor capacitor structure that is applicable to low voltage of device area thereby realize not increasing additional technology cost.But, if disregard cost, certainly can also utilize other mode to form the second medium layer with first thickness and the second medium layer with second thickness.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. semiconductor capacitor structure is characterized in that comprising: a plurality of semiconductor capacitors, and wherein each semiconductor capacitor includes:
Semiconductor substrate;
Be positioned at the first medium layer of described semiconductor substrate surface;
Be positioned at first polysilicon layer on described first medium layer surface;
Be positioned at the second medium layer on described the first polysilicon layer surface;
Be positioned at second polysilicon layer on described second medium layer and first medium layer surface;
Wherein, the second medium layer of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
2. semiconductor capacitor structure according to claim 1 is characterized in that, described semiconductor substrate surface is formed with fleet plough groove isolation structure, and the first medium layer is positioned at described fleet plough groove isolation structure top; Perhaps semiconductor substrate surface does not have fleet plough groove isolation structure, and the first medium layer is positioned at described substrate top.
3. semiconductor capacitor structure according to claim 1 and 2 is characterized in that, the second medium layer covers the sidewall of a side of the first polysilicon layer; Described the second polysilicon layer covers the sidewall that the second medium layer is positioned at first medium layer surface, the first polysilicon layer part surface of an end relative with capped the first polysilicon layer sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger that is electrically connected with the first polysilicon layer, and described the second polysilicon layer surface also has the second conductive plunger that is electrically connected with the second polysilicon layer;
Wherein, for the semiconductor capacitor structure that is positioned at the substrate top, described substrate surface also has the 3rd conductive plunger that is electrically connected with substrate layer, and the electric capacity that substrate, first medium layer, the first polysilicon layer form is electrically connected and is unified into larger capacitance structure with the electric capacity that the first polysilicon layer, second medium layer, the second polysilicon layer form.
4. a semiconductor capacitor structure manufacture method is characterized in that being included in and arranges simultaneously a plurality of semiconductor capacitors in the chip, and wherein each semiconductor capacitor includes: Semiconductor substrate; Be positioned at the first medium layer of described surface of shallow trench isolation structure or substrate surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface;
Wherein, so that the second medium layer of the part in described a plurality of semiconductor capacitor has the first thickness, and so that the second medium layer of the another part in described a plurality of semiconductor capacitor has the second thickness, and described the first thickness is greater than described the second thickness.
5. semiconductor capacitor structure manufacture method according to claim 4, it is characterized in that, in formation has the step of MOS transistor grid oxic horizon of different-thickness, form respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness.
6. semiconductor capacitor structure is characterized in that comprising: a plurality of semiconductor capacitors, and wherein each semiconductor capacitor includes:
Semiconductor substrate, described semiconductor substrate surface is formed with dopant well;
Be positioned at the first medium layer on described dopant well surface;
Be positioned at first polysilicon layer on described first medium layer surface;
Be positioned at the second medium layer on described the first polysilicon layer surface;
Be positioned at second polysilicon layer on described second medium layer and first medium layer surface;
Wherein, the second medium layer of the part in described a plurality of semiconductor capacitors has the first thickness, and the second medium layer of the another part in described a plurality of semiconductor capacitors has the second thickness, and described the first thickness is greater than described the second thickness.
7. semiconductor capacitor structure according to claim 6 is characterized in that, described semiconductor substrate surface is formed with fleet plough groove isolation structure; Fleet plough groove isolation structure or as the part of described semiconductor capacitor structure as and the isolation of substrate, perhaps be applied to different voltage conditions between the described semiconductor capacitor structure on the substrate as the isolation that differs from one another between the electromotive force dopant well.
8. according to claim 6 or 7 described semiconductor capacitor structures, it is characterized in that described second medium layer covers a sidewall of the first polysilicon layer; Described the second polysilicon layer covers the sidewall that the second medium layer is positioned at first medium layer surface, the first polysilicon layer part surface of an end relative with capped the first polysilicon layer sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger that is electrically connected with the first polysilicon layer, and described the second polysilicon layer surface also has the second conductive plunger that is electrically connected with the second polysilicon layer.
9. a semiconductor capacitor structure manufacture method is characterized in that being included in and arranges simultaneously a plurality of semiconductor capacitors in the chip, and wherein each semiconductor capacitor includes: Semiconductor substrate, and described semiconductor substrate surface is formed with dopant well; Be positioned at the first medium layer on described dopant well surface; Be positioned at first polysilicon layer on described first medium layer surface; Be positioned at the second medium layer on described the first polysilicon layer surface; Be positioned at second polysilicon layer on described second medium layer and first medium layer surface;
Wherein, so that the second medium layer of the part in described a plurality of semiconductor capacitor has the first thickness, and so that the second medium layer of the another part in described a plurality of semiconductor capacitor has the second thickness, and described the first thickness is greater than described the second thickness.
10. semiconductor capacitor structure manufacture method according to claim 9, it is characterized in that, in formation has the step of MOS transistor grid oxic horizon of different-thickness, form respectively the second medium layer that has the second medium layer of the first thickness and have the second thickness.
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| CN110047818A (en) * | 2019-03-26 | 2019-07-23 | 电子科技大学 | A kind of ferroelectric capacitor structure that multilayer is overlapping |
| CN113078142A (en) * | 2021-03-23 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and testing method for electrostatic protection |
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| CN102214702A (en) * | 2011-05-23 | 2011-10-12 | 上海宏力半导体制造有限公司 | Semiconductor capacitor structure and formation method thereof |
| CN102290981A (en) * | 2011-05-23 | 2011-12-21 | 上海宏力半导体制造有限公司 | Charge pump circuit and flash memory adopting same |
| CN102437016A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Integration method for realizing capacitors with two different insulating layer thicknesses |
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| US6674118B2 (en) * | 1999-07-06 | 2004-01-06 | Taiwan Semiconductor Manufacturing Company | PIP capacitor for split-gate flash process |
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| CN110047818A (en) * | 2019-03-26 | 2019-07-23 | 电子科技大学 | A kind of ferroelectric capacitor structure that multilayer is overlapping |
| CN110047818B (en) * | 2019-03-26 | 2021-03-16 | 电子科技大学 | Multilayer overlapping ferroelectric capacitor structure |
| CN113078142A (en) * | 2021-03-23 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and testing method for electrostatic protection |
| CN113078142B (en) * | 2021-03-23 | 2022-05-31 | 长鑫存储技术有限公司 | Semiconductor structure and testing method for electrostatic protection |
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