CN102945792A - Improving method of adverse effect on oxide etch-back of groove side wall - Google Patents
Improving method of adverse effect on oxide etch-back of groove side wall Download PDFInfo
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- CN102945792A CN102945792A CN2012105076281A CN201210507628A CN102945792A CN 102945792 A CN102945792 A CN 102945792A CN 2012105076281 A CN2012105076281 A CN 2012105076281A CN 201210507628 A CN201210507628 A CN 201210507628A CN 102945792 A CN102945792 A CN 102945792A
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Abstract
The invention relates to an improving method of adverse effect on oxide etch-back of groove side wall. The improving method of the adverse effect on the oxide etch-back of the groove side wall caused by different deposition thicknesses of the top and the bottom of a groove comprises the following steps of: step 1, forming a structure which is provided with the groove and is required in the production process of a chip; step 2, depositing oxide on the structure obtained in the step 1; step 3, carrying out first injection by virtue of neutral atoms in a direction forming a first slant angle with a vertical direction; step 4, carrying out second injection by virtue of the neutral atoms in the direction forming a second slant angle with the vertical direction; and step 5, carrying out etch-back on the oxide subjected to the injection. According to the improving method of the adverse effect on the oxide etch-back of the groove side wall caused by different deposition thicknesses of the top and the bottom of etch-back groove, the adverse effect on the etch-back of the groove side wall oxide caused by different deposition thicknesses of the top and the bottom of etch-back groove can be simply and effectively improved and overcome.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to that a kind of groove top is different from the bottom portion of groove deposit thickness to cause dysgenic improvement method to groove side wall oxide etch-back.
Background technology
In semiconductor fabrication, especially in the manufacture process of autoregistration nonvolatile memory, often run into semiconductor structure and need to form oxide side wall to realize the situation of isolation.The oxide side wall of for example isolating source line polysilicon strip and floating boom is exactly in the silicon nitride groove deposition oxide and eat-backs to form side wall construction.
For example, Fig. 1 schematically shows the sectional view that is positioned at isolated area after a kind of nonvolatile memory source line forms.As shown in Figure 1, the structure after nonvolatile memory source line forms comprises: be arranged in the nitration case with groove 40 20 on the oxide 10, and be arranged in the side wall oxide 31 on groove 40 sidewalls.
In order to form side wall oxide 31, as shown in Figure 3, at first form nitration case 20 figures.
Such as Fig. 4 silicon oxide layer deposited 30 on the architecture basics of Fig. 3.
Such as Fig. 7 oxide 30 is carried out etching, and stay the oxide side walls of semiconductor structure 30 sidepieces.
Enough in order to guarantee this thickness, can only when before area of isolation grinding, grind less some oxides.But, caused like this two kinds of possibility structures: perhaps dwindle area of isolation grinding window and guarantee enough area of isolation oxide thickness; Perhaps lose the oxide thickness of area of isolation, lose thus yield.
Summary of the invention
Technical problem to be solved by this invention is for there being defects in the prior art, provide a kind of can be in the situation that do not dwindle area of isolation and grind window and guarantee that the groove top of enough area of isolation oxide thickness is different from the bottom portion of groove deposit thickness groove side wall oxide etch-back is caused dysgenic improvement method.
In order to realize above-mentioned technical purpose, according to the present invention, provide that a kind of groove top is different from the bottom portion of groove deposit thickness to cause dysgenic improvement method to groove side wall oxide etch-back, it comprises: first step is used to form the reeded structure of the tool that needs in the chip production process; Second step is used for deposition oxide on the resulting structure of first step; Third step is used for injecting to utilize neutral atom to carry out the first time in vertical direction with the direction at the first inclination angle; The 4th step is used for injecting to utilize neutral atom to carry out the second time in vertical direction with the direction at the second inclination angle; The 5th step is used for eat-backing having carried out the oxide that injects.
According to the present invention, provide also that a kind of groove top is different from the bottom portion of groove deposit thickness to cause dysgenic improvement method to groove side wall oxide etch-back, it is characterized in that comprising: first step is used for the reeded silicon nitride structure of tool that autoregistration nonvolatile memory manufacture process forms; Second step is used for deposition oxide on the resulting structure of first step, with floating boom and the source line polysilicon of isolation autoregistration nonvolatile memory; Third step is used for injecting to utilize neutral atom to carry out the first time in vertical direction with the direction at the first inclination angle; The 4th step is injected to utilize neutral atom to carry out the second time in vertical direction with the direction at the second inclination angle; The 5th step is used for eat-backing having carried out the oxide that injects.
Preferably, in described third step, thickness according to the oxide of the thickness of the oxide of the size of groove, groove structure upper surface, the thickness of oxide on the groove structure sidewall and bottom portion of groove is selected the first inclination angle, so that neutral atom does not inject the oxide of bottom portion of groove.
Preferably, in described third step, described neutral atom is heavier atom, for example ar atmo.
Preferably, in the 4th step, thickness according to the oxide of the thickness of the oxide of the size of groove, groove structure upper surface, the thickness of oxide on the groove structure sidewall and bottom portion of groove is selected the second inclination angle, so that neutral atom does not inject the oxide of bottom portion of groove.
Preferably, in the 4th step, described neutral atom is heavier atom, for example ar atmo.
Preferably, the direction at the direction at the first inclination angle and the second inclination angle is in same plane, and is arranged symmetrically with respect to vertical direction.
Groove side wall oxide etch-back is caused in the dysgenic improvement method groove top according to the present invention is different from the bottom portion of groove deposit thickness, because the oxide of groove structure upper surface obtains the injection of neutral atom, the etching speed of the oxide after neutral atom injects is greater than the oxide of the bottom portion of groove of the injection that does not obtain neutral atom thus, thus can be effectively the etching speed of oxide by increasing the groove structure upper surface come the deficiency of the thickness of the oxide bottom the compensation groove; Thus can be owing to the bottom oxide light that is etched first lose the thickness of the oxide in the isolation channel originally, perhaps, reduce the thickness of the interior oxide of light loses because bottom oxide is etched first script isolation channel.
Therefore, groove top according to the present invention is different from the bottom portion of groove deposit thickness causes dysgenic improvement method to cause harmful effect to carry out simple and effective improvement and overcome to groove side wall oxide etch-back to groove top is different with the bottom portion of groove deposit thickness to groove side wall oxide etch-back.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the sectional view that is positioned at isolated area after a kind of nonvolatile memory source line forms.
Fig. 2 schematically shows according to the groove top of the embodiment of the invention flow charts that groove side wall oxide etch-back caused dysgenic improvement method different from the bottom portion of groove deposit thickness.
Fig. 3 schematically shows according to the groove top of the embodiment of the invention schematic diagrames that groove side wall oxide etch-back caused the first step of dysgenic improvement method different from the bottom portion of groove deposit thickness.
Fig. 4 schematically shows according to the groove top of the embodiment of the invention schematic diagrames that groove side wall oxide etch-back caused the second step of dysgenic improvement method different from the bottom portion of groove deposit thickness.
Fig. 5 schematically shows according to the groove top of the embodiment of the invention schematic diagrames that groove side wall oxide etch-back caused the third step of dysgenic improvement method different from the bottom portion of groove deposit thickness.
Fig. 6 schematically shows according to the groove top of the embodiment of the invention schematic diagrames that groove side wall oxide etch-back caused four step of dysgenic improvement method different from the bottom portion of groove deposit thickness.
Fig. 7 schematically shows according to the groove top of the embodiment of the invention schematic diagrames that groove side wall oxide etch-back caused five step of dysgenic improvement method different from the bottom portion of groove deposit thickness.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
During owing to deposit film on groove structure, will inevitably cause the difference of groove top (surface), sidewall, bottom thickness.This thickness difference can cause adverse effect to eat-backing of this film.Thus, the invention provides that a kind of groove top is different from the bottom portion of groove deposit thickness to cause dysgenic improvement method to groove side wall oxide etch-back.
Fig. 2 schematically shows according to the groove top of the embodiment of the invention flow charts that groove side wall oxide etch-back caused dysgenic improvement method different from the bottom portion of groove deposit thickness.
Specifically, as shown in Figure 2, cause dysgenic improvement method to comprise according to the groove top of the embodiment of the invention is different from the bottom portion of groove deposit thickness to groove side wall oxide etch-back:
First step S1, for the reeded structure of tool that needs in formation chip production process, for example at the area of isolation 10 of silicon chip (not shown) (for example, area of isolation 10 is isolated areas of shallow channel isolation area or other type) the upper semiconductor structure 20 (for example polysilicon) with groove 40 that forms, form thus the groove structure that is formed by groove 40 and semiconductor structure 20, as shown in Figure 3.
Second step S2 is used for deposition oxide 30 on the resulting structure of first step S1; Usually can pass through boiler tube technique grow oxide 30 (for example silica), at this moment, compare with the oxide 30 of semiconductor structure 20 upper surfaces, the oxide 30 on the oxide 30 on groove 40 bottoms and the sidewall of semiconductor structure 20 is thinner, as shown in Figure 4.
More particularly, for example, the eat-backing in the situation about improving of side wall in the production process of the circuit such as autoregistration nonvolatile memory, oxide 30 is the oxide layers of isolating floating boom and source line polysilicon.
Third step S3 is used for injecting to utilize neutral atom to carry out the first time in vertical direction with the direction at the first inclination angle; For example neutral atom can be heavier atom, for example ar atmo; Preferably, in third step S3, thickness according to the oxide 30 of the thickness of the oxide 30 of the size of groove 40, semiconductor structure 20 upper surfaces, the thickness of oxide 30 on semiconductor structure 20 sidewalls and groove 40 bottoms is selected the first inclination angle, so that neutral atom does not inject the oxide 30 of groove 40 bottoms, as shown in Figure 5.
The 4th step S4 is used for injecting to utilize neutral atom to carry out the second time in vertical direction with the direction at the second inclination angle; For example neutral atom can be heavier atom, for example ar atmo; Preferably, in the 4th step S4, thickness according to the oxide 30 of the thickness of the oxide 30 of the size of groove 40, semiconductor structure 20 upper surfaces, the thickness of oxide 30 on semiconductor structure 20 sidewalls and groove 40 bottoms is selected the second inclination angle, so that neutral atom does not inject the oxide 30 of groove 40 bottoms, as shown in Figure 6.
Preferably, the direction at the direction at the first inclination angle and the second inclination angle is in same plane, and is arranged symmetrically with respect to vertical direction.
The 5th step S5, be used for eat-backing having carried out the oxide 30 that injects for the first time and inject for the second time, wherein the oxide 30 of semiconductor structure 20 upper surfaces and the oxide 30 of groove 40 bottoms are eat-back fully, and stay side wall oxide 31, as shown in Figure 7.
Groove side wall oxide etch-back is caused in the dysgenic improvement method groove top according to the above embodiment of the present invention is different from the bottom portion of groove deposit thickness, because the oxide 30 of semiconductor structure 20 upper surfaces obtains the injection of neutral atom, the etching speed of the oxide after neutral atom injects is greater than the oxide 30 of groove 40 bottoms of the injection that does not obtain neutral atom thus, thus can be effectively the etching speed of oxide 30 by increase semiconductor structure 20 upper surfaces come the deficiency of thickness of the oxide 30 of compensation groove 40 bottoms; Thus can be owing to the bottom oxide light that is etched first lose the thickness of the oxide in the isolation channel originally, perhaps, reduce the thickness of the interior oxide of light loses because bottom oxide is etched first script isolation channel.
Therefore, cause dysgenic improvement method to cause harmful effect to carry out simple and effective improvement and overcome to groove side wall oxide etch-back to groove top is different with the bottom portion of groove deposit thickness according to the groove top of the embodiment of the invention is different from the bottom portion of groove deposit thickness to groove side wall oxide etch-back.
More particularly, in concrete the application, the present invention can be used in the autoregistration nonvolatile memory production process eat-backing of side wall and improves.If take in order to the oxide layer of isolating floating boom and source line polysilicon as example, poor adverse effect to above-mentioned etching in order to the oxide layer of isolating floating boom and source line polysilicon of the groove top, the bottom thickness that form at FGSN (SIN) of this patent oxide that overcome deposition so: the etched time of top can be said the time that bottom etching is finished that is short to greatly.Solved the overetched problem in bottom that causes for finishing the top etching.Owing to " crossing etching " solution of problem; Greatly reduced the consumption of this etching to silica in the isolated area.Thereby increased the process window (processwindow) of isolated area cmp.
Need to prove, above-described embodiment shows carries out the example of injecting and injecting for the second time for the first time, injects but may only carry out once, rather than carries out symmetrically twice injection.But it is preferred carrying out the example of injecting for the first time and injecting for the second time, and reason is and can forms symmetrical sidewall by carrying out to inject for the first time and inject for the second time.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. a groove top is different from the bottom portion of groove deposit thickness causes dysgenic improvement method to groove side wall oxide etch-back, it is characterized in that comprising:
First step is used to form the reeded structure of the tool that needs in the chip production process;
Second step is used for deposition oxide on the resulting structure of first step;
Third step is used for injecting to utilize neutral atom to carry out the first time in vertical direction with the direction at the first inclination angle;
The 4th step is injected to utilize neutral atom to carry out the second time in vertical direction with the direction at the second inclination angle;
The 5th step is used for eat-backing having carried out the oxide that injects.
2. a groove top is different from the bottom portion of groove deposit thickness causes dysgenic improvement method to groove side wall oxide etch-back, it is characterized in that comprising:
First step is used for the reeded silicon nitride structure of tool that autoregistration nonvolatile memory manufacture process forms;
Second step is used for deposition oxide on the resulting structure of first step, with floating boom and the source line polysilicon of isolation autoregistration nonvolatile memory;
Third step is used for injecting to utilize neutral atom to carry out the first time in vertical direction with the direction at the first inclination angle;
The 4th step is injected to utilize neutral atom to carry out the second time in vertical direction with the direction at the second inclination angle;
The 5th step is used for eat-backing having carried out the oxide that injects.
3. improvement method according to claim 1 and 2, it is characterized in that, in described third step, thickness according to the oxide of the thickness of the oxide of the size of groove, groove structure upper surface, the thickness of oxide on the groove structure sidewall and bottom portion of groove is selected the first inclination angle, so that neutral atom does not inject the oxide of bottom portion of groove.
4. improvement method according to claim 1 and 2 is characterized in that, in described third step, described neutral atom is heavier atom, for example ar atmo.
5. improvement method according to claim 1 and 2, it is characterized in that, in the 4th step, thickness according to the oxide of the thickness of the oxide of the size of groove, groove structure upper surface, the thickness of oxide on the groove structure sidewall and bottom portion of groove is selected the second inclination angle, so that neutral atom does not inject the oxide of bottom portion of groove.
6. improvement method according to claim 1 and 2 is characterized in that, in the 4th step, described neutral atom is heavier atom, for example ar atmo.
7. improvement method according to claim 1 and 2 is characterized in that, the direction at the direction at the first inclination angle and the second inclination angle is in same plane, and is arranged symmetrically with respect to vertical direction.
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| US6096598A (en) * | 1998-10-29 | 2000-08-01 | International Business Machines Corporation | Method for forming pillar memory cells and device formed thereby |
| US6846744B1 (en) * | 2003-10-17 | 2005-01-25 | Nanya Technology Corp. | Method of fabricating a bottle shaped deep trench for trench capacitor DRAM devices |
| US20060166419A1 (en) * | 2005-01-21 | 2006-07-27 | Kazuo Shimoyama | Method for manufacturing semiconductor device |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN102610526A (en) * | 2012-03-23 | 2012-07-25 | 上海华力微电子有限公司 | Side wall etching method for reducing heat current carrier injection damage |
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2012
- 2012-11-30 CN CN2012105076281A patent/CN102945792A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6096598A (en) * | 1998-10-29 | 2000-08-01 | International Business Machines Corporation | Method for forming pillar memory cells and device formed thereby |
| US6846744B1 (en) * | 2003-10-17 | 2005-01-25 | Nanya Technology Corp. | Method of fabricating a bottle shaped deep trench for trench capacitor DRAM devices |
| US20060166419A1 (en) * | 2005-01-21 | 2006-07-27 | Kazuo Shimoyama | Method for manufacturing semiconductor device |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN102610526A (en) * | 2012-03-23 | 2012-07-25 | 上海华力微电子有限公司 | Side wall etching method for reducing heat current carrier injection damage |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140509 |
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Effective date of registration: 20140509 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20130227 |