CN102945214A - Method for optimizing interrupt processing task based on IO (Input-Output) delay time distribution - Google Patents
Method for optimizing interrupt processing task based on IO (Input-Output) delay time distribution Download PDFInfo
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Abstract
The invention provides a method for optimizing an interrupt processing task based on IO (Input-Output) delay time distribution. A computer system comprises a first processing unit and a second processing unit. The computer system is coupled with a storage device. The method comprises the steps of receiving a first IO request for accessing the storage device; recording the start time of the first IO request; recording the end time of the first IO request in response to an interrupt request from the storage device to indicate that the first IO request is worked out; calculating a first time difference between the end time of the first IO request and the start time of the first IO request; calculating distribution of the first time difference within a predetermined time period; and optimizing execution of the interrupt processing task associated with the IO request of the storage device based on the distribution of the first time difference.
Description
Technical field
The present invention relates to solid storage device (Solid Storage Device, SSD), more specifically, the present invention relates to the interruption that memory device sends to main frame.
Background technology
Similar with the mechanical type hard disk, solid storage device (SSD) also is large capacity, the non-volatile memory device for computer system.Solid storage device generally with flash memory (Flash) as storage medium.High performance solid storage device is used to high-performance computer.High-performance computer has a plurality of central processing units (CPU, Centrol Process Unit) usually, and each CPU can comprise a plurality of CPU nuclears.
In modern operating system, almost each interrupts processing operating and has been divided into two parts, i.e. interrupt service routine (ISR) and the latter half handling procedure (Bottom Half Handler); Interrupt in other words the first half (Top Half) and the latter half (Bottom Half) of processing; In some scenarios, be also referred to as first order interrupt handling routine (FLIH, First-Level Interrupt Handler) and second level interrupt handling routine (SLIH, Second-Level Interrupt Handlers).Difference between the two is: in the first half of interrupting processing, interruption is forbidden, speaking by the book is that to have an interruption (current interruption) (current C PU) on a CPU at least be forbidden, and in some cases, whole interruptions of possible current C PU all are under an embargo; And in the latter half of interrupting processing, the interruption in the system all allows, and new interruption can be seized the latter half handling procedure at any time.Be divided into two parts by interrupting processing, and allow the first half process function and only do the fastest minimum work--for example copy data to internal memory from the equipment buffer zone, go to carry out and leave the work of follow-up more time-consuming for the latter half handling procedure, effectively reduce the time of interrupt choking effect, thereby improved the interruption treatment effeciency of system.
In U.S. Patent application US2011/0087814A1, provide by interrupting compatibility mechanism to strengthen IO(Input Output in the multicomputer system) scheme of performance.Referring to Fig. 1, main frame 100 comprises CPU 101,102,103 and 104, on application program 111,112,113 and 114 CPU that operate in respectively separately.High-speed cache 121,122,123 and 124 is coupled with CPU 101,102,103 and 104 respectively, is used for storage and is respectively applied to application program 111,112,113 and 114 instruction and data.And the storer 131,132,133 and 134 with larger capacity is coupled to respectively high-speed cache 121,122,123 and 124.Host bus adaptor (HBA, Host Bus Adapter) 150 by IO APIC(Advanced Programmable Interr upt Controller, Advanced Programmable Interrupt Controllers APICs) hub 140 is coupled to main frame 100, and be configured to storage area network network (SAN, Storage Area, Network) 160 communications.SAN 160 is connected to a plurality of computer memory devices 170 such as hard disk.Interrupt compatibility mechanism and mean, when I/O APIC hub 140 receives interruption from HBA 150, determine which among a plurality of CPU of main frame 100 to come handling interrupt by.For example, record sends the CPU identifier of IO request, when receiving the interruption of asking corresponding to this IO, selects the CPU of handling interrupt based on the CPU identifier of record.
Some computing machines have NUMA(Non-Uniform Memory Access) or NUIO(Non-Uniform Input Output) structure.The scheme of interrupting for the IO device assignment in a plurality of nodes in the NUMA system is provided in U.S. Patent application US2005/0060460A1.Referring to Fig. 2, NUMA system 200 comprises by interconnection network node 201,211 coupled to each other, 221 and 231.Each node 201,211,221 and 231 can comprise processor and storer.The storer of given node is local with respect to the processor of this node, and the storer of other nodes is long-range with respect to this processor.System 200 comprises IO equipment 202,212 and 242, and is used for IO equipment 202,212 and 242 Interrupt Service Routine (ISR, Interrupt Service Routine) 203,213 and 223.System 200 also comprises interrupt distribution software 222, is used for Interrupt Service Routine 203,213 and 223 is distributed to IO equipment 202,212 and 242.The distribution of Interrupt Service Routine can be based on following factors: the node that equipment connects, be used for the node that the ISR of equipment is positioned at, and the processor of node.
Www.acpi.info/DOWNLOADS/ACPIspec50.pdfObtainable " Advanced Configuration and Power Interface Specification " (on Dec 6th, 2011) provides each NUMA domain information that obtains the NUMA system.
Yet the IO processing power of high-performance solid storage device significantly improves, and the quantity of IO request and the increase of data volume have caused burden for the processing of CPU.Thereby, need to be optimized the processing to interrupt request.
Summary of the invention
According to a first aspect of the invention, a kind of method of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processing units, and described memory device is by in described a plurality of processing units one of PCIE bus coupling, and described method comprises:
Obtain the identifier of described memory device;
According to the identifier of described memory device, determine the first processing unit that described memory device is coupled;
The first half of the interruption Processing tasks that is associated with described memory device is set to carry out at described the first processing unit;
The latter half of described interruption Processing tasks is set to carry out at the second processing unit;
Wherein said the first processing unit and described the second processing unit are shared cache memory.
According to a second aspect of the invention, a kind of method of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processor slots, be furnished with polycaryon processor on each processor slot, described polycaryon processor has a plurality of processor cores, described memory device is by in described a plurality of processor slots one of PCIE bus coupling, and described method comprises:
Obtain the identifier of described memory device;
According to the identifier of described memory device, determine the first processor slot that described memory device is coupled;
The first half of the interruption Processing tasks that is associated with described memory device is set to carry out at the first processor nuclear that is arranged in the polycaryon processor on the described first processor slot;
The latter half of described interruption Processing tasks is set to carry out at the second processor core that is arranged in the polycaryon processor on the described first processor slot;
Wherein said first processor nuclear is shared cache memory with described the second processor core.
The method that provides according to a second aspect of the invention further comprises, shows the coupled relation of described memory device and described first processor slot and/or described first processor nuclear.
According to a first aspect of the invention or the method that provides of second aspect, further comprise, show the coupled relation of described memory device and described the first processing unit.
The method that provides according to a second aspect of the invention, comprise that also the application program of accessing described memory device is set to carry out at the 3rd processor core that is arranged in the polycaryon processor on the described first processor slot, described first processor nuclear, described the second processor core and described the 3rd processor core are shared cache memory.
According to a first aspect of the invention or the method that provides of second aspect, also comprise passage (Lane) quantity of obtaining and showing described PCIE bus.
According to a first aspect of the invention or the method that provides of second aspect, also comprise the quantity of obtaining and showing the IO access with first time delay of described memory device, and the quantity of the IO access with second time delay of described memory device, be different from described the second time delay described the first time delay.
According to a first aspect of the invention or the method that provides of second aspect, also comprise obtain and show described memory device have first time delay scope the quantity of IO access, and described memory device have second time delay scope the quantity of IO access, described first time delay scope be different from described second time delay scope.
The method that provides according to a first aspect of the invention, the application program of the described memory device of access is set to carry out at the second processor.
The method that provides according to a first aspect of the invention, the application program of the described memory device of access is set to carry out at the 3rd processing unit the 3rd processing unit and described the first processing unit and the second processing unit shared cache.
According to a first aspect of the invention or the method that provides of second aspect, the first half of described interruption Processing tasks is embodied as work queue or kernel thread.
According to a first aspect of the invention or the method that provides of second aspect, the first half of described interruption Processing tasks is used for the save register state and removes interrupting, and the latter half of described interruption Processing tasks determines that according to the buffer status of preserving an IO asks to finish dealing with.
According to a third aspect of the invention we, a kind of method of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processing units and a plurality of PCIE slot, described memory device is coupled in described a plurality of processing unit one by the PCIE slot in described a plurality of PCIE slots, and described method comprises:
Identify the first processing unit that a described PCIE slot is coupled;
Determine that described memory device is coupled to described the first processing unit;
The first half of the interruption Processing tasks that is associated with described memory device is set to carry out at described the first processing unit;
The latter half of described interruption Processing tasks is set to carry out at the second processing unit;
Wherein said the first processing unit and described the second processing unit are shared cache memory.
According to a forth aspect of the invention, a kind of method of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processor slots and a plurality of PCIE slot, be furnished with polycaryon processor on each processor slot, described polycaryon processor has a plurality of processor cores, described memory device is coupled in described a plurality of processor slot one by the PCIE slot in described a plurality of PCIE slots, and described method comprises:
Identify the first processor slot that a described PCIE slot is coupled;
Determine that described memory device is coupled to described first processor slot;
The first half of the interruption Processing tasks that is associated with described memory device is set to carry out at the first processor nuclear that is arranged in the polycaryon processor on the described first processor slot;
The latter half of described interruption Processing tasks is set to carry out at the second processor core that is arranged in the polycaryon processor on the described first processor slot;
Wherein, described first processor nuclear is shared cache memory with described the second processor core.
According to a first aspect of the invention or the method for the third aspect, comprise that also the application program of accessing described memory device is set to carry out at described the first processing unit, described the second processing unit or the 3rd processing unit, described the first processing unit, described the second processing unit and described the 3rd processing unit are shared described cache memory.
According to a second aspect of the invention or the method for fourth aspect, comprise that also the application program of accessing described memory device is set to carry out at the 3rd processor core that is arranged in the polycaryon processor on the described first processor slot, described first processor nuclear, described the second processor core and described the 3rd processor core are shared cache memory.
According to a first aspect of the invention, the method for second aspect, the third aspect or fourth aspect, further comprise, described memory device is transferred to described cache memory with the data of described computer system request with dma mode.
According to a fifth aspect of the invention, a kind of device of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processing units, and described memory device is by in described a plurality of processing units one of PCIE bus coupling, and described device comprises:
Module for the identifier that obtains described memory device;
Be used for the identifier according to described memory device, determine the module of the first processing unit that described memory device is coupled;
The first half that is used for the interruption Processing tasks be associated with described memory device is set to the module carried out at described the first processing unit;
The latter half that is used for described interruption Processing tasks is set to the module carried out at the second processing unit;
Wherein said the first processing unit and described the second processing unit are shared cache memory.
According to a sixth aspect of the invention, a kind of device of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processor slots, be furnished with polycaryon processor on each processor slot, described polycaryon processor has a plurality of processor cores, described memory device is by in described a plurality of processor slots one of PCIE bus coupling, and described device comprises:
Module for the identifier that obtains described memory device;
Be used for the identifier according to described memory device, determine the module of the first processor slot that described memory device is coupled;
The first half for the interruption Processing tasks that is associated with described memory device is set to examine the module of carrying out at the first processor that is arranged in the polycaryon processor on the described first processor slot;
The latter half that is used for described interruption Processing tasks is set to the module carried out at the second processor core that is arranged in the polycaryon processor on the described first processor slot;
Wherein said first processor nuclear is shared cache memory with described the second processor core.
According to a seventh aspect of the invention, a kind of device of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processing units and a plurality of PCIE slot, described memory device is coupled in described a plurality of processing unit one by the PCIE slot in described a plurality of PCIE slots, and described device comprises:
Be used for identifying the module of the first processing unit that a described PCIE slot is coupled;
Be used for determining that described memory device is coupled to the module of described the first processing unit;
The first half that is used for the interruption Processing tasks be associated with described memory device is set to the module carried out at described the first processing unit;
The latter half that is used for described interruption Processing tasks is set to the module carried out at the second processing unit;
Wherein said the first processing unit and described the second processing unit are shared cache memory.
According to an eighth aspect of the invention, a kind of device of the interrupt request for the treatment of the memory device in the computer system is provided, described computer system comprises a plurality of processor slots and a plurality of PCIE slot, be furnished with polycaryon processor on each processor slot, described polycaryon processor has a plurality of processor cores, described memory device is coupled in described a plurality of processor slot one by the PCIE slot in described a plurality of PCIE slots, and described device comprises:
Be used for identifying the module of the first processor slot that a described PCIE slot is coupled;
Be used for determining that described memory device is coupled to the module of described first processor slot;
The first half for the interruption Processing tasks that is associated with described memory device is set to examine the module of carrying out at the first processor that is arranged in the polycaryon processor on the described first processor slot;
The latter half that is used for described interruption Processing tasks is set to the module carried out at the second processor core that is arranged in the polycaryon processor on the described first processor slot;
Wherein, described first processor nuclear is shared cache memory with described the second processor core.
According to a ninth aspect of the invention, provide a kind of method of the interrupt request for the treatment of the memory device in the computer system, described computer system comprises the first processing unit and the second processing unit, and described computer system is coupled with memory device; Described method comprises:
The interruption Processing tasks that is associated with the IO request of described memory device is set to carry out at described the first processing unit;
Receive the IO request that is used for accessing described memory device;
Record the start time of described IO request;
In response to receiving the interrupt request of finishing dealing with from the described IO request of the indication of described memory device, carry out described interruption Processing tasks, to record the concluding time of described IO request;
The very first time of calculating the concluding time of described IO request and the start time that a described IO asks is poor;
Calculate poor distribution of the described very first time in the predetermined time period; And
Based on the poor distribution of the described very first time, interrupt Processing tasks and be set to carry out at described the second processing unit.
Method according to a ninth aspect of the invention also comprises:
Receive the 2nd IO request that is used for accessing described memory device;
Record the start time of described the 2nd IO request;
In response to receiving the interrupt request of finishing dealing with from described the 2nd IO request of the indication of described memory device, carry out described interruption Processing tasks, to record the concluding time of described the 2nd IO request;
Calculate the concluding time of described the 2nd IO request and the second mistiming of the start time that described the 2nd IO asks;
Calculate the distribution of described the second mistiming in the predetermined time period; And
Based on the described very first time poor distribution and the distribution of described the second mistiming, interrupt Processing tasks and be set to carry out at one of described the first processing unit or described second processing unit.
Method according to a ninth aspect of the invention comprises that also the distribution that the described very first time is poor sends application program to.
Method according to a ninth aspect of the invention comprises that also distribution and/or the distribution of described the second mistiming that the described very first time is poor send application program to.
According to the tenth aspect of the invention, provide a kind of device of the interrupt request for the treatment of the memory device in the computer system, described computer system comprises the first processing unit and the second processing unit, and described computer system is coupled with memory device; Described device comprises:
The interruption Processing tasks that is used for being associated with the IO request of described memory device is set to the module carried out at described the first processing unit;
Be used for receiving the module for the IO request of accessing described memory device;
Module for the start time of recording described IO request;
Be used for the interrupt request of finishing dealing with from the described IO request of the indication of described memory device in response to receiving, carry out described interruption Processing tasks, with the module of concluding time of recording described IO request;
Be used for calculating the poor module of the very first time of the concluding time of described IO request and the start time that a described IO asks;
Be used for calculating the module of the distribution of described very first time difference in the predetermined time period; And
Be used for based on the poor distribution of the described very first time, interrupt Processing tasks and be set to the module carried out at described the second processing unit.
Device according to the tenth aspect of the invention also comprises:
Be used for receiving the module for the 2nd IO request of accessing described memory device;
Module for the start time of recording described the 2nd IO request;
Be used for the interrupt request of finishing dealing with from described the 2nd IO request of the indication of described memory device in response to receiving, carry out described interruption Processing tasks, with the module of concluding time of recording described the 2nd IO request;
The module of the second mistiming of the start time that the concluding time that is used for calculating described the 2nd IO request and described the 2nd IO ask;
Be used for calculating the module of the distribution of described the second mistiming in the predetermined time period; And
Be used for based on the described very first time poor distribution and the distribution of described the second mistiming, the interruption Processing tasks is set to the module in the execution of one of described the first processing unit or described second processing unit.
Description of drawings
When reading together with accompanying drawing, by the detailed description of reference back to the embodiment of illustrating property, will understand best the present invention and preferably use pattern and its further purpose and advantage, wherein accompanying drawing comprises:
Fig. 1 is the structured flowchart according to the storage system of prior art;
Fig. 2 is the structured flowchart according to the NUMA system of prior art;
Fig. 3 A is the structured flowchart of NUIO system of implementing the interruption optimization method of the embodiment of the invention;
Fig. 3 B is the process flow diagram that interrupts according to an embodiment of the invention optimization method;
Fig. 4 A is the structured flowchart of implementing the interruption optimization method NUIO system of another embodiment of the present invention;
Fig. 4 B is the process flow diagram of interruption optimization method according to another embodiment of the present invention; And
Fig. 5 is the process flow diagram of interruption optimization method according to still another embodiment of the invention.
Embodiment
Fig. 3 A is the structured flowchart of NUIO system of implementing the interruption optimization method of the embodiment of the invention.The computer system of embodiment as shown in Figure 3A has the NUIO structure, because memory device 321 is coupled to CPU 301, and memory device 322 is coupled to CPU302, so that CPU 301 is different from IO between the memory device 321 with the IO between CPU 322 and the memory device 321.CPU 301 and CPU 302 all are coupled to high-speed cache 311, and CPU 301 and CPU 302 shared caches 311.
Because memory device 321 is coupled to CPU 301, thus the interruption Processing tasks setting that will be associated with memory device 321 or be bundled in to carry out on the CPU 301 be favourable.That is, when memory device 321 produced interrupt request, interrupt request was forwarded to CPU 301, processed this interrupt request by CPU 301 by carrying out ISR.ISR is configured to process the first half of the interruption Processing tasks that is associated with memory device 321.For example, in ISR, inquiry is also preserved memory device 321 corresponding PCI/PCIE equipment and is deposited buffer status and remove interruption.The interruption Processing tasks setting that will be associated with memory device 322 similarly, or be bundled on the CPU 302 is carried out.
Referring to Fig. 3 B, Fig. 3 B is the process flow diagram that interrupts according to an embodiment of the invention optimization method.In step 360, obtain the identifier of memory device 321.For PCI/PCIE equipment, obtain the identifier of unique description memory device 321 by pci configuration space.Based on the identifier of memory device 321, in step 370, determine that memory device is coupled to the CPU 301 among CPU 301 and 302.In (SuSE) Linux OS, can obtain CPU 301 corresponding APICID by "/proc/cpuinfo ", then access the CPU 301 that the APIC table obtains to belong to memory device 321 identical NUMA territory.In (SuSE) Linux OS, can also by user's space "/sys/devices/pci＜pci-bus 〉/＜pci-dev/numa_node ", "/sys/devices/pci＜pci-bus 〉/＜pci-dev/local_cpus " or "/sys/devices/pci＜pci-bus 〉/＜pci-dev/local_cpulist " obtain to belong to memory device 321 CPU 301 in identical NUMA territory.Also can be in the driver of the memory device 321 of Linux, obtain and memory device 321 belongs to the CPU 301 in identical NUMA territory by " dev-numa_node ".In Windows operating system, also addressable APIC table, and acquisition and memory device 321 belong to the CPU 301 in identical NUMA territory.Can also by checking the circuit board at memory device 301 and memory device 321 places, determine the coupled relation of CPU 301 and memory device 321.Preferably, at the CPU 301 that this slot of mark is coupled on the slot of coupled storage equipment 321 that is used for of circuit board, and by configuration file, command line interface or graphic user interface the incidence relation of memory device 321 and CPU 301 is offered driver.
In step 380, the first half of the interruption Processing tasks that is associated with memory device 321 is set to carry out at CPU 301.The ISR that is used in memory device 321 carries out at CPU 301.In one embodiment, when memory device 321 produced interrupt request, interrupt request was forwarded to CPU 301.In ISR, inquiry is also preserved memory device 321 corresponding PCI/PCIE equipment and is deposited buffer status and remove interruption.Alternatively, in ISR, also copy data to DRAM storer and/or high-speed cache 311 from the buffer zone of memory device 321.In step 390, the latter half of the interruption Processing tasks that is associated with memory device 321 is set to carry out at CPU 302.Because CPU 301 and 302 shared caches 311, so that can be interrupted by high-speed cache 311 the latter half access of Processing tasks by the handled data of the first half of interrupting Processing tasks, thereby reduced swap data between DRAM storer and high-speed cache 311 and the expense that produces.And, also reduced the first half of handoff Processing tasks on CPU 301 and the latter half and the expense that produces.Especially, when memory device 321 frequent generation interrupt request, the first half of interrupting Processing tasks will frequently be carried out, and the latter half that will interrupt Processing tasks is arranged on execution on the CPU 302 that is different from CPU 301, also reduce the burden of CPU 301, and reduced the probability that the latter half of interrupting Processing tasks is frequently interrupted.In one embodiment, the latter half of interrupting Processing tasks is embodied as the work queue (Wordqueue) that (SuSE) Linux OS provides.In one embodiment, the latter half of interrupting Processing tasks is embodied as kernel thread, all supports kernel thread such as the operating system of Linux or Windows etc.For memory device 322, also can pass through step 360-390, carry out so that its first half of interrupting Processing tasks is arranged on the CPU 302, and its latter half of interrupting Processing tasks is arranged on execution on the CPU 301.The latter half that is used for the interruption Processing tasks of memory device 322 can also be arranged on the upper execution of other CPU that are different from CPU 301 and 302.
The user in a further embodiment, also memory device 321 and the coupled relation of CPU 301 preserved and offered application program, so that can obtain by application program the coupled relation of memory device 321 and CPU 301.And still further among the embodiment, according to the coupled relation of memory device 321 with CPU 301, the application program of accessing storage device 321 is set to carry out at CPU 301 or 302.
Fig. 4 A is the structured flowchart of NUIO system of implementing the interruption optimization method of the embodiment of the invention.The computer system of embodiment shown in Fig. 4 A has the NUIO structure, because memory device 431 is coupled to CPU slot 405, and memory device 441 is coupled to CPU slot 415, so that CPU slot 405 is different from IO between the memory device 431 with the IO between CPU slot 415 and the memory device 441.CPU 400 is arranged in the CPU slot 405, and CPU 410 is arranged in the CPU slot 415.CPU 400,410 can be multi-core CPU, and CPU 400 comprises CPU nuclear 401,402, and CPU 410 comprises CPU nuclear 411 and 412.In CPU 400, be furnished with the high-speed cache 403 of being shared by CPU nuclear 401,402, and in CPU 410, be furnished with the high-speed cache 413 of being shared by CPU nuclear 411,412.CPU nuclear 401,402,411 and 412 can dispose respectively the high-speed cache (not shown) of monopolizing.
Between CPU 400 and the CPU 410 by such as QPI(QuickPath Interconnect) or FSB(Front-Side Bus) high speed be connected 450 and be coupled.PCIE slot 435,445 is coupled to respectively CPU slot 405,415, and and then is coupled to respectively CPU 400,410.Be coupled with respectively memory device 431,441 on the PCIE slot 435,445.Memory device 431,441 can be solid storage device (SSD), also can be other memory devices with PCIE interface.Also will be such as DRAM(Dynamic Random Access Memory) primary memory 421,422 be coupled to respectively CPU 400 and 410, and thereby form the computer system of NUMA structure.And one of ordinary skill in the art will recognize, CPU 400 can access primary memory 421 and the memory device 431 that is coupled to CPU slot 405, and also can access primary memory 422 and the memory device 441 that is coupled to CPU slot 415.Similarly, CPU 410 can access primary memory 422 and the memory device 441 that is coupled to CPU slot 415, and also can access primary memory 421 and the memory device 431 that is coupled to CPU slot 405.
Because memory device 431 is coupled to CPU 400, thus the interruption Processing tasks setting that will be associated with memory device 431 or be bundled in to carry out on the CPU 400 be favourable.That is, when memory device 431 produced interrupt request, interrupt request was forwarded to CPU 400, processed this interrupt request by CPU 400 by carrying out ISR.ISR is configured to process the first half of the interruption Processing tasks that is associated with memory device 431.For example, in ISR, inquiry is also preserved memory device 431 corresponding PCI/PCIE equipment and is deposited buffer status and remove interruption.It is favourable that the interruption Processing tasks setting that will be associated with memory device 441 similarly, or be bundled in is carried out on the CPU 410.
Referring to Fig. 4 B, Fig. 4 B is the process flow diagram that interrupts according to an embodiment of the invention optimization method.In step 460, obtain the identifier of memory device 431.For PCI/PCIE equipment, obtain the identifier of unique description memory device 431 by pci configuration space.In step 470, determine that memory device 431 is coupled to the CPU slot 405 among CPU slot 405 and the CPU slot 415, and and then definite memory device 431 be coupled to CPU 400.Can obtain to belong to memory device 431 by access CPU 400 and the CPU nuclear 401,402 thereof in identical NUMA territory based on the APIC table of ACPI standard (Advanced Configuration and Power Interface Specification).Also can by checking the circuit board at PCIE slot 435 and CPU slot 405 places, determine the coupled relation between CPU slot 405 and the PCIE slot 435.Preferably, the CPU slot 405 that this slot of mark is coupled on the PCIE slot 435 of coupled storage equipment 431 that is used at circuit board, perhaps be coupled to the CPU 400 of CPU slot 405 and/or CPU nuclear 401,402, and the incidence relation of memory device 431 and CPU 400 and/or CPU nuclear 401,402 offered 431 application program of driver and/or accessing storage device by configuration file, command line interface or graphic user interface.Similarly, at the CPU slot 415 that this slot of mark is coupled on the PCIE slot 445 of coupled storage equipment 441 that is used for of circuit board, perhaps be coupled to CPU 410 and/or the CPU nuclear 411,412 of CPU slot 415.And the incidence relation of memory device 441 and CPU 410 and/or CPU nuclear 411,412 is offered 441 application program of driver and/or accessing storage device.
In step 480, the CPU nuclear 401 that the first half of the interruption Processing tasks that is associated with memory device 431 is set at CPU 400 is carried out.The ISR that is used in memory device 431 carries out at CPU nuclear 401.In one embodiment, when memory device 431 produced interrupt request, interrupt request was forwarded to CPU nuclear 401.In ISR, inquiry is also preserved memory device 431 corresponding PCI/PCIE equipment and is deposited buffer status and remove interruption.Alternatively, in ISR, also copy data to primary memory 421 and/or high-speed cache 403 from the buffer zone of memory device 431.
In step 490, the CPU nuclear 402 that the latter half of the interruption Processing tasks that is associated with memory device 431 is set at CPU 400 is carried out.In the latter half of interrupting Processing tasks, determine that according to the buffer status of the first half storage of interrupting Processing tasks which IO asks to finish, finish corresponding IO and upgrade statistical information.Because CPU nuclear 401,402 shared caches 403, so that can be interrupted by high-speed cache 403 the latter half access of Processing tasks by the handled data of the first half of interrupting Processing tasks, thereby the expense that has reduced swap data between primary memory 421 and high-speed cache 403 and produced has also reduced swap data between CPU 400 and CPU 410 and the expense that produces.And, also reduced the first half of handoff Processing tasks on CPU nuclear 401 and the latter half and the expense that produces.
For memory device 441, also can pass through step 460-490, be arranged on the first half of it being interrupted Processing tasks on the CPU nuclear 411 of CPU410 and carry out, and its latter half of interrupting Processing tasks is arranged on the CPU nuclear 412 of CPU 410 and carries out.One of ordinary skill in the art will recognize, when the load of CPU 410 is higher, also the latter half that is used for the interruption Processing tasks of memory device 441 can be arranged on the upper execution of CPU 400 or other CPU.
In another embodiment still, memory device 431 writes data in the high-speed cache 403 by the transmission of the DMA take high-speed cache 403 as the destination, and sends the interrupt request that the request of indication corresponding I/O is finished.CPU nuclear 401 is carried out the first half of interrupting Processing tasks, and inquiry and preservation memory device 431 corresponding PCI/PCIE equipment are deposited buffer status and removed and interrupt.And CPU nuclear 402 is carried out the latter half of interrupting Processing tasks, determines that according to the buffer status of the first half storage of interrupting Processing tasks which IO request finishes, and utilizes the data in the high-speed cache 403 to finish corresponding IO operation.The application program of sending the IO request also can also be set to carry out at CPU nuclear 402, perhaps be set to carrying out with other CPU nuclear (not shown) of CPU nuclear 401,402 shared caches 403, directly to transmit the data of coming with the IO request of passing through in the high-speed cache 403 from memory device 431.
One of ordinary skill in the art also will recognize, also the ISR that is used for memory device 431 can be carried out at CPU nuclear 402.And will be arranged on for the latter half of the interruption Processing tasks of memory device 431 on the CPU nuclear 401 and carry out.And still further among the embodiment, according to the coupled relation of memory device 431 with CPU 400, the application program of accessing storage device 431 is set to carry out at CPU nuclear 401 or 402.
In a further embodiment, the user also memory device 431 and the coupled relation of CPU slot 405 and/or CPU 400 and/or CPU nuclear 401,402 preserved and offered application program, so that can obtain by application program the coupled relation of memory device 431 and CPU slot 405 and/or CPU 400 and/or CPU nuclear 401,402.And similarly, application program is preserved and offered to memory device 441 and the coupled relation of CPU slot 415 and/or CPU 410 and/or CPU nuclear 411,412.
Fig. 5 is the process flow diagram of optimization method according to still another embodiment of the invention.Based on the distribution of the time delay of IO request, adjust and be used for carrying out CPU or the CPU nuclear that interrupts Processing tasks.Optimization method according to the embodiment of Fig. 5 is described below in conjunction with the NUIO system of Fig. 4 A.One of ordinary skill in the art will recognize, also can implement in conjunction with the NUIO system of Fig. 3 A the optimization method according to the embodiment of Fig. 5.
In step 501, the interruption Processing tasks that is associated with memory device 431 is set to carry out at CPU nuclear 401.This interrupts Processing tasks for the treatment of the IO request from memory device 431.The IO request is initiated by application program.In step 520, the driver that is used for memory device 431 receives the IO request for accessing storage device 431.In step 530, record the start time of this IO request.In step 540, after receiving the interrupt request of finishing dealing with from this IO request of indication of memory device 431 and processing this interrupt request, record the concluding time of this IO request.In step 550, calculate the mistiming of concluding time and start time, to obtain the time delay of this IO request.In this way, for a plurality of or each the IO request that is associated with memory device 431, all can obtain the time delay of its IO request.In step 560, calculate the distribution of the time delay of a plurality of IO requests of (for example, 0.5 second or 1 second) in a predetermined time period.For example, as shown in the table in one embodiment, ask 64.3% of total amount at the IO that the IO of 90-400 microsecond request accounted in the schedule time time delay, and ask 33.4% of total amount at the IO that the IO of 400-1.5 millisecond request accounted in the schedule time time delay.And the distribution of this time delay can be offered application program.
In step 570, the distribution based on the time delay of a plurality of IO request determines whether to need to optimize the execution of interrupting Processing tasks.In one embodiment, if the distribution of the time delay of a plurality of IO requests obviously is inferior to expection or predetermined distribution, the interruption Processing tasks that then is associated with memory device 431 in step 580 is set to examine (for example CPU nuclear 402,411 or 412) at the CPU that is different from CPU nuclear 401 and carries out.In one embodiment, if the time delay before the distribution of the time delay of a plurality of IO requests is inferior to distributes, the interruption Processing tasks that then is associated with memory device 431 in step 580 is set to examine (for example CPU nuclear 402,411 or 412) at the CPU that is different from CPU nuclear 401 and carries out.If judge the execution that does not need to optimize the interruption Processing tasks in step 570, then get back to step 520, to monitor and to calculate time delay and the distribution thereof of other IO request.
In one embodiment, provide IO delay measurements process.The interruption Processing tasks that will be associated with memory device 431 is separately positioned on the CPU nuclear 401,402,411 or 412, measures the distribution of the time delay of IO request separately.And the interruption Processing tasks that will be associated with memory device 431 is arranged on the better CPU nuclear of the time delay parameter of IO request.In another embodiment, time delay or its distribution that measures corresponding to the IO request of each CPU nuclear of outage Processing tasks offered application program, and then show the user.Make the user can select according to the needs of its application to carry out the CPU nuclear (preferably, CPU nuclear 402) of the interruption Processing tasks that is associated with memory device 431.
Related interruption Processing tasks in step 510 and/or 580 can be the latter half of interrupting the first half of Processing tasks and/or interrupting Processing tasks.As already mentioned, for the first half of interrupting Processing tasks, by the compatibility of interrupt request and CPU and/or CPU nuclear is set, be forwarded to specific CPU and/or CPU nuclear with the interrupt request with memory device 431, for example CPU nuclear 401.For the latter half of interrupting Processing tasks, schedule it to upper execution of specific CPU and/or CPU nuclear (for example CPU nuclear 402).
In a further embodiment, the time delay of the IO request when measuring memory device 431 disconnected Processing tasks is separately positioned on the CPU nuclear 401,402,411 or 412 therein distributes, the time delay of the IO request when also measuring memory device 441 disconnected Processing tasks being separately positioned on the CPU nuclear 401,402,411 or 412 therein distributes, and is used for scheduling association in the interruption Processing tasks of memory device 431 and/or is associated with the execution of interruption Processing tasks on a plurality of CPU and/or CPU nuclear of memory device 441.
Still further among the embodiment, also obtain the quantity of the passage (Lane) of coupled storage equipment 431,441 PCIE interface.The number of channels of PCIE interface means data transfer bandwidth.For the memory device with larger data transmission demand, it is favourable selecting to be coupled to the PCIE interface that has than major path quantity.Also the quantity of the passage (Lane) of coupled storage equipment 431,441 PCIE interface can be offered the user, so that the user can select whether to adjust the PCIE interface that memory device 431,441 is coupled, and/or select the CPU that carries out the interruption Processing tasks that is associated with memory device 431 to examine, and/or select to carry out the CPU nuclear of the application program that is associated with memory device 431.
Represented the description of this invention for the purpose that illustrates and describe, and be not intended to disclosed form limit or restriction the present invention.To one of ordinary skill in the art, many adjustment and variation are apparent.
Claims (10)
1. method for the treatment of the interrupt request of the memory device in the computer system, described computer system comprises the first processing unit and the second processing unit, described computer system is coupled with memory device; Described method comprises:
Receive the IO request that is used for accessing described memory device;
Record the start time of described IO request;
In response to receiving the interrupt request of finishing dealing with from the described IO request of the indication of described memory device, record the concluding time of described IO request;
The very first time of calculating the concluding time of described IO request and the start time that a described IO asks is poor;
Calculate poor distribution of the described very first time in the predetermined time period; And
Based on the poor distribution of the described very first time, optimize the execution of the interruption Processing tasks that is associated with the IO request of described memory device.
2. method according to claim 1, wherein said method also comprises, before receiving for the IO request of accessing described memory device, the interruption Processing tasks that is associated with the IO request of described memory device is set to carry out at described the first processing unit;
After receiving the interrupt request that described IO request is finished dealing with from the indication of described memory device, carry out described interruption Processing tasks; And
Based on the poor distribution of the described very first time, interrupt Processing tasks and be set to carry out at described the second processing unit.
3. method according to claim 1 and 2 also comprises:
Receive the 2nd IO request that is used for accessing described memory device;
Record the start time of described the 2nd IO request;
In response to receiving the interrupt request of finishing dealing with from described the 2nd IO request of the indication of described memory device, carry out described interruption Processing tasks, record the concluding time of described the 2nd IO request;
Calculate the concluding time of described the 2nd IO request and the second mistiming of the start time that described the 2nd IO asks;
Calculate the distribution of described the second mistiming in the predetermined time period; And
Based on the described very first time poor distribution and the distribution of described the second mistiming, interrupting Processing tasks is set to carry out at one of described the first processing unit or described second processing unit, wherein, the described very first time, poor distribution was asked corresponding to a plurality of described IO, and described the second mistiming distributes corresponding to a plurality of described the 2nd IO requests.
4. according to claim 1 and 2 method comprises that also the distribution that the described very first time is poor sends application program to.
5. according to claim 3 method comprises that also distribution and/or the distribution of described the second mistiming that the described very first time is poor send application program to.
6. device for the treatment of the interrupt request of the memory device in the computer system, described computer system comprises the first processing unit and the second processing unit, described computer system is coupled with memory device; Described device comprises:
Be used for receiving the module for the IO request of accessing described memory device;
Module for the start time of recording described IO request;
For in response to receiving the interrupt request of finishing dealing with from the described IO request of the indication of described memory device, record the module of the concluding time of described IO request;
Be used for calculating the poor module of the very first time of the concluding time of described IO request and the start time that a described IO asks;
Be used for calculating the module of the distribution of described very first time difference in the predetermined time period; And
Be used for based on the poor distribution of the described very first time, optimize the module of the execution of the interruption Processing tasks that is associated with the IO request of described memory device.
7. device according to claim 1 also comprises:
Be used for receive be used for accessing the IO request of described memory device before, the interruption Processing tasks that is associated with the IO request of described memory device is set to the module carried out at described the first processing unit;
Be used for after receiving the interrupt request that described IO request is finished dealing with from the indication of described memory device, carrying out the module of described interruption Processing tasks; And
Be used for based on the poor distribution of the described very first time, interrupt Processing tasks and be set to the module carried out at described the second processing unit.
8. also comprise according to claim 6 or 7 described devices:
Be used for receiving the module for the 2nd IO request of accessing described memory device;
Module for the start time of recording described the 2nd IO request;
For in response to receiving the interrupt request of finishing dealing with from described the 2nd IO request of the indication of described memory device, carry out described interruption Processing tasks, record the module of the concluding time of described the 2nd IO request;
The module of the second mistiming of the start time that the concluding time that is used for calculating described the 2nd IO request and described the 2nd IO ask; Be used for calculating the module of the distribution of described the second mistiming in the predetermined time period; And
Be used for based on the described very first time poor distribution and the distribution of described the second mistiming, the interruption Processing tasks is set to the module in the execution of one of described the first processing unit or described second processing unit, wherein, the described very first time, poor distribution was asked corresponding to a plurality of described IO, and described the second mistiming distributes corresponding to a plurality of described the 2nd IO requests.
9. method for the treatment of the interrupt request of the memory device in the computer system, described computer system is coupled with memory device; Described method comprises:
Receive the IO request that is used for accessing described memory device;
Record the start time of described IO request;
In response to receiving the interrupt request of finishing dealing with from the described IO request of the indication of described memory device, record the concluding time of described IO request;
The very first time of calculating the concluding time of described IO request and the start time that a described IO asks is poor;
Calculate poor distribution of the described very first time in the predetermined time period; And
The distribution that the described very first time is poor sends application program to.
10. device for the treatment of the interrupt request of the memory device in the computer system, described computer system is coupled with memory device; Described device comprises:
Be used for receiving the module for the IO request of accessing described memory device;
Module for the start time of recording described IO request;
For in response to receiving the interrupt request of finishing dealing with from the described IO request of the indication of described memory device, record the module of the concluding time of described IO request;
Be used for calculating the poor module of the very first time of the concluding time of described IO request and the start time that a described IO asks;
Be used for calculating the module of the distribution of described very first time difference in the predetermined time period; And
Be used for the module that the distribution that the described very first time is poor sends application program to.
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