KR20140058455A - Control apparatus of memory and control method thereof, and recording medium storing program for executing method of the same in computer - Google Patents

Abstract

A memory control apparatus for adaptively determining the order of execution of multiple memory access requests is disclosed. A memory access request buffer unit processes multiple memory access requests in an input order thereof, based on the input order and the bank and row information of memory addresses extracted from the memory access requests, but determines and stores a memory access request order such that memory access requests for the same bank and the same row are consecutively processed. A memory access request controller reads the memory access requests in the order determined by the memory access request buffer unit, distributes the memory access requests to banks, transmits, to a memory, the memory access requests distributed to the banks in order, and executes the memory access requests. A bank controller stores the memory access requests distributed to the banks in a buffer unit for each bank within a preset number, and controls an operational status for each bank. The memory access request controller checks whether the buffer unit for each bank is empty when distributing the memory access requests to the banks, and first transmits, to an empty buffer unit for each bank, even a memory access request which is in a back order in the memory access request buffer unit. According to the present invention, waiting times can be reduced by arranging multiple memory access requests, and power consumption can be reduced by making the best use of bandwidth.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, a control method, and a recording medium storing a program for causing a computer to execute the method.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, a control method, and a recording medium storing a program for executing the method in a computer, and more particularly, And a recording medium on which a program for causing the computer to execute the method is recorded.

The global smartphone and tablet PC craze has led to the development of a variety of application processors (APs), and system-on-chip (SOC) in many areas has a platform structure similar to the application processor. A feature of the system on chip (SOC) is that it has several processors or masters in it and they share one memory. In particular, a system that processes multimedia data such as video and music, and processes many data at high speed such as recognition and authentication, often has limited system performance due to memory access. In other words, if the memory does not provide sufficient bandwidth, it will experience performance degradation by waiting for data in the master, such as a processor or a hardware accelerator. If bandwidth is the only problem, it can be solved by using high-speed memory or by adding dedicated memory, but there are many new problems such as cost increase and system redesign. In addition, memory access requests for general instructions of a microprocessor are sensitive to latency, and memory access requests for multimedia data of multimedia accelerators or microprocessors are sensitive to bandwidth maintenance requirements. To solve this problem, it is necessary to make system-level control of memory access request. It is very inefficient for one processor to intercept and control commands of all masters. Another approach is to gather memory access instructions from the memory controller and adjust them to optimize system performance. In this case, it is necessary to transmit additional information to know the characteristics of each memory access command.

An ARM high-performance bus (AHB) is widely used as an interface protocol for data transfer inside a system on chip (SOC). The AHB specification allows up to 16 masters, but it is valid when the sum of the bandwidth required by each master is much smaller than the total bandwidth. If the sum of the required bandwidth of each master becomes similar to the bandwidth provided by the network, two masters will cause problems. The use of the interconnect matrix can greatly increase bandwidth, but it is of little help if communications are concentrated in shared memory. Another problem with AHB is that while one memory access communication occurs due to stop-and-wait communication, another master can not access the memory, and the memory controller processes the requested memory access one by one It is impossible to arbitrate the memory access. You can increase the number of slave interfaces to handle as many commands as there are interfaces at a time, but you have to use an interconnect matrix and limit the number of times you have to respond to that channel with that channel open. .

ARM's AXI complements the AHB's challenge to enable high-speed operation by supporting outstanding address and out-of-order completion communications in multi-master systems and allowing register slicing in the network. Therefore, it is possible to arbitrate the access request from the memory controller since another memory access request is possible before responding to one memory access request. Using this, it is possible to cope with the quality of service (QoS) request by decreasing the waiting cycle for memory access and increasing the effective bandwidth and adjusting the priority.

A specific example of the related art is disclosed in Korean Unexamined Patent Application Publication No. 10-2002-0040150, entitled System On Chip (SOC) technology, Device and the like together with the SDRAM to solve the difference between the data transmission width and the operating frequency between the related chips, thereby improving the data transmission efficiency. In other words, it does not take into account the order and method of handling multiple instructions that access SDRAM.

Korean Patent Publication No. 10-2001-0019127 entitled " External bus controller and method supporting burst transmission using MPC860 and SDIAM ", which is incorporated herein by reference, discloses a processor and SDRAM, and PCI There is disclosed an external bus controller that provides the maximum performance of an external bus and an external bus controller that provides the UPM of the MPC 860. This is also different from the present invention which efficiently processes multiple instructions that access SDRAM.

According to an aspect of the present invention, there is provided a memory control apparatus and method for minimizing waiting time and maximizing a bandwidth by minimizing an operation of reordering a plurality of memory access requests in a multi-command based memory control apparatus, .

According to an aspect of the present invention, there is provided a memory control apparatus for adaptively determining an execution order of a plurality of memory access requests, the memory control apparatus comprising: Memory access requests are processed in the order of input based on the bank and row information of the memory address extracted from the access request, and memory access request order is determined so that the memory access requests for the same row of the same bank are successively processed An access request buffer unit; A memory access request controller for reading a memory access request in the order determined by the memory access request buffer unit and distributing a memory access request for each bank and transferring the memory access requests distributed to the banks to the memory in order; And a bank controller for storing a memory access request distributed for each of the banks in a buffer unit for each bank within a preset number of times and controlling an operation state of each bank, The memory access request buffer unit determines whether or not the buffer unit for each bank is empty when distributing the request, and transfers memory access requests in order subsequent to the memory access request order determined by the memory access request buffer unit to the buffer unit for each empty bank.

According to another aspect of the present invention, there is provided a memory control method performed by a memory control device for adaptively determining an execution order of a plurality of memory access requests, The access request control unit sequentially reading a plurality of memory access requests from the memory access request buffer unit; (b) the memory access request control unit checking whether the first bank buffer unit is empty based on first bank information corresponding to a memory address extracted in an n-th memory access request; (c) if the first bank buffer unit is empty, transfers the n-th memory access request to the first bank buffer unit, and if the first bank buffer unit is not empty, Reading a memory access request in which the bank information of the address is the second bank; (d) checking whether the second bank buffer unit is empty, and if the second bank buffer unit is empty, transferring a memory access request in which the bank information of the memory address is a second bank to the second bank buffer unit; And (e) storing the order in which the memory access request is transferred to the buffer unit for each bank, and transferring the order of the bank control unit to the memory in order, wherein the step (e) A second memory access request stored in the buffer unit is transferred to a memory in accordance with the input order, and a second memory access request inputted in the next order of the first memory access request is transferred to the first memory Confirming that the access request and the memory address are the same row of the same bank; And (e2) if the second memory access request is the same row of the same bank as the first memory access request, successively delivering the second memory access command to the memory, Transferring a command generated in accordance with an input order to a plurality of memory access requests stored in the second bank buffer unit during a waiting cycle for opening a new row when the access request is another row of the same bank; .

According to the memory control device and the control method of the present invention, a plurality of memory access requests can be arranged to reduce waiting time and maximize the bandwidth. That is, it is possible to reduce the latency due to a new operation in memory access, increase bandwidth, and reduce power consumption by minimizing the operation of storing a command requesting a memory access in a storage unit and analyzing the command to newly open a bank row. It is also possible to process according to the priority of the memory access request.

1 is a block diagram showing the relationship between a memory control device and a memory according to the present invention;
2 is a block diagram showing a detailed configuration of a memory control device according to the present invention;
3 is a flowchart illustrating a memory control method according to the first embodiment of the present invention;
4 is a flowchart illustrating a memory control method according to a second embodiment of the present invention;
5 is a diagram showing a simulation environment using a memory control device according to the present invention;
6 is a view showing a data pattern for a simulation result write operation for a memory control device according to the present invention;
FIG. 7 is a graph showing simulation results for requests of write patterns 1, 2, and 3,
8 is a view showing a data pattern for a simulation result read operation for a memory control device according to the present invention;
9 is a graph showing simulation results for requests of read patterns 4, 5, and 6,
FIG. 10 is a diagram for comparing the difference of operation cycles according to a write-after-read and a post-write-after-write operation for the same row as simulation results of the memory control device according to the present invention;
11 is a graph comparing operation cycles for requests of data patterns 7 and 8,
12 is a diagram showing data patterns extracted from an FIR filter and an H.264 decoder,
13 is a graph comparing operation operation cycles for data patterns of the FIR filter and the H.264 decoder.

Hereinafter, preferred embodiments of a memory control device and a control method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a relationship between a memory control device 100 and a memory 110 according to the present invention, and FIG. 2 is a block diagram showing a detailed configuration of a memory control device 100 according to the present invention.

1 and 2, a memory control apparatus 100 according to the present invention includes a memory access request buffer unit 210, a memory access request control unit 220, a bank control unit 230, and a buffer unit 231 for each bank , 232, 233, 234).

The memory access request buffer unit 210 determines and stores a memory access request order based on input order of a plurality of memory access requests and memory addresses (bank and row information) extracted from the memory access requests. At this time, a memory access request sequence can be determined so that a plurality of memory access requests are processed in the input order, and memory access requests for the same bank and the same row are consecutively processed. That is, a register for registering a flag for determining the validity of data for each register and a function for calculating and storing the execution order is connected to the register file structure. Thus, when a memory access request is sorted, the data does not actually move and the execution order device value changes and the execution order changes.

The memory access request control unit 220 reads memory access requests in order from the memory access request buffer unit 210, distributes memory access requests for the respective banks, and sequentially distributes memory access requests distributed to the respective banks to the memory .

The memory access request control unit 220 determines whether the buffer units 231, 232, 233, and 234 for each bank are empty when allocating a memory access request for each bank, and stores the empty buffer units 231, 232, 233, 234 so that a memory access request can be transmitted first. For example, the first bank buffer unit 231, which is one of the bank-specific buffer units 231, 232, 233, and 234, stores 5 (for example, The memory access request for accessing the first bank can not be stored any more, and thus the memory access request for accessing the bank other than the first bank is searched. For example, if the first bank and the other bank are the second bank, the second bank buffer unit 232 also checks whether the memory access requests are filled in the predetermined number. If the second bank buffer unit 232 is empty, ) To access the second bank. At this time, the memory access request controller 220 stores in which bank the memory access request information is delivered, receives the memory access command from the bank controller 230, and selects the bank controller 230 according to the priority order when transferring the memory access request to the memory, Executes a memory access instruction.

If the memory address of the current memory access request is another row of the same bank as the memory access request read before the current memory access request, the memory access request control unit 220 And transmits a memory access request for accessing another bank to the bank controller 230 before the current memory access request. If a row is changed in the currently accessed bank, a wait cycle occurs. Therefore, an access request for the next bank is executed in the wait cycle during the access request to reduce the wait cycle.

That is, if the memory access request currently being processed accesses the address of the second line of the first bank and the memory access request read before the current access request for the memory accesses the address of the first line of the first bank, A memory access request for accessing a second bank, which is a bank different from the first bank, among the memory access requests corresponding to the order after the memory access request to be processed is retrieved, and a memory access request for accessing the second bank is called a current memory access request To the memory 110 during a waiting cycle occurring in the process. In this case, however, memory access requests must be stored in the buffer units 231, 232, 233, and 234 of the respective banks. If the buffers of all the other banks are empty, the first bank access request of the first bank is executed as it is. This has the effect of reducing the waiting cycle by executing the waiting instruction of the other bank every time the waiting cycle occurs. Therefore, it is advantageous for hardware implementation since it is unnecessary to perform a separate sorting operation and the sorting is naturally performed in the request allocation process for each bank. Accordingly, it is possible to reduce the operation load according to the memory access request ordering order of the memory access request buffer unit 210. In addition, the memory access request control unit 220 controls initialization, refresh (REFRESH), and power-down of the memory 110.

The bank controller 230 stores the memory access requests distributed by the banks in the buffer units 231, 232, 233, and 234 for each bank within a predetermined number of times, and controls the operation state for each bank. That is, the buffer units 231, 232, 233, and 234 for each bank store one or more memory access requests for each bank according to the address of the memory to be accessed. In response to the control signal of the memory access request control unit 220, A memory access command is sent to the memory 110 to adaptively determine the execution order of the multiple memory access requests. In this case, the memory access command may be sequentially stored in the memory 230 in accordance with the control signal of the bank controller 230 without the memory access request being stored in the buffer unit for each bank, (110).

3 is a flowchart illustrating a memory control method according to the first embodiment of the present invention.

Referring to FIG. 3, the memory access request control unit 220 sequentially reads a plurality of memory access requests from the memory access request buffer unit 210 (S310). The memory access request control unit 220 determines whether the buffer unit 231 of the first bank is empty based on the bank information (first bank) corresponding to the memory address extracted in the read memory access request (S320). If the buffer unit 231 of the first bank is empty (S320), the memory access request input to the buffer unit 231 of the first bank is transmitted (S330). On the other hand, if it is determined that the buffer unit 231 of the first bank is full (S320), the bank information of the memory address in the request inputted after the read-out memory access request has the bank (the second bank) The memory access request is retrieved and if the buffer unit 232 of the other bank (second bank) is empty, a memory access with the other bank (the second bank) to the buffer unit 232 of the other empty bank (the second bank) And transmits the request (S340). The order in which the memory access requests are transmitted to the buffer units 231 and 232 for each bank is stored and the commands of the bank controller 230 are sequentially transmitted to the memory as described above.

4 is a flowchart illustrating a memory control method according to a second embodiment of the present invention.

4, the memory access request control unit 220 transfers a plurality of memory access requests stored in the first bank buffer unit 231 to the memory 110 in accordance with the input order S410). The memory access request control unit 220 determines whether the next memory access request stored in the first bank buffer unit 231 is the same as the first memory access request (S420). If the same row is confirmed, the next memory access command is continuously transmitted to the memory 110 (S440). However, if it is not the same row as the check result, a PRECHARGE and an ACTIVE command to change the row occur and this command causes a waiting cycle. In operation S430, the memory access request stored in the second bank buffer unit 232 is transferred to the memory 110 in accordance with the input order.

The memory controller 100 according to the present invention is expected to have a great effect when applied to an SDRAM memory, and the performance is different according to the on-chip network. Fig. 5 shows a simulation environment using the memory control device 100. Fig. The memory access request generation unit 500 generates a request operation to be used for the simulation and requests the memory control apparatus 100 to confirm the request and drives the simulation model 510. The simulation model 510 used was Micron's MT48LC4M32B2 and CAS Latency (CL) was applied for 3 cycles, burst length 4, tRCD = 2, tRP = 3.

Figure 6 shows a data pattern for a write operation as a result of a simulation for a memory control device. We are writing data in ascending order of 1, 2, 3, 4 in each pattern. For example, pattern 1 performs a write operation in the order of bank 0-bank 1-bank 0-bank 1. 1 write operation means 4 burst write. Patterns 2 and 3 repeat the write operation of four bursts two times in sequence for three and four banks, respectively. The difference in operations 1, 2, and 3 is that they use 2, 3, and 4 banks, respectively. FIG. 7 is a graph showing simulation results for requests of write patterns 1, 2, and 3. FIG. If the patterns are the same, it can be seen that the operation cycle is the same. This is because, in the write operation, the completion of the data in the buffer (FIFO) storing the write data is seen. Therefore, if there is a vacant space in the buffer (FIFO) for storing the write data, the write operation can be continued and the operation cycle is the same.

8 shows a data pattern for a read operation as a result of a simulation for a memory control device. It is the same pattern as the writing operation except that it is changed from writing to reading. In the case of a write request, it is assumed that communication is completed when data is entered into a buffer (FIFO) storing write data. In the case of a read request, a read request is input and until the read data is output through the memory control device 100 It can be expected that the operation cycle will be different from the write operation.

FIG. 9 is a graph showing simulation results for requests of read patterns 4, 5, and 6. FIG. In the case of reading, it can be seen that the processing of multiple instructions and the processing of single instructions differ significantly in the operation cycle. The difference of the arithmetic cycle becomes larger as the number of requests increases. In the case of the multi-instruction-based control apparatus according to the present invention, if the read request is waiting in advance and the last instruction of the previous request is issued, , Since in the case of a single instruction-based control device, the next request is made immediately after the read data has been all exited to the memory control device interface, the memory control device is not doing any work until after the next request is reflected after the last command is issued . These waiting cycles are cumulative as the number of requests increases and the difference becomes larger. In the present invention, the difference between the pattern 5 and the pattern 6 is 8 cycles, which corresponds to the number of data differences 8 required in the patterns 5 and 6. Here, when the bank has three or more circulating structures, it can be seen that the active cycle (ACTIVE) and the waiting cycle by PRECHARGE become "0". If two banks are used, the access time for one bank is equal to or greater than the time for the other bank to be active (ACTIVE) or precharging (PRECHARGE). In pattern 6, it can be seen that the present invention has been completed using only a 30% computation cycle compared to a single instruction based control device.

FIG. 10 is a diagram comparing the difference in operation cycle between the write-after-read and the post-write-after-write operations for the same row. FIG. 11 is a graph comparing operation cycles for data patterns 7 and 8. FIG. Referring to FIG. 11, in the case of the pattern 7 having the write-after-read request, if the write data is stored in the write buffer (FIFO), the memory access request generator 500 can read the write data, It can be seen that the read request can be input to the memory control device so that no difference is seen between the present invention and the single instruction based control device. However, in the case of the pattern 8 in which a write-after-read request is made, the present invention is completed in the same cycle as the write-after-read operation, whereas the single-instruction-based control device can not write- Performance degradation can be seen. In pattern 8, the present invention completed the request with only about 58% computation cycles compared to a single instruction based control device.

12 is a diagram showing data patterns extracted from the FIR filter and the H.264 decoder, respectively. In order to analyze the performance difference in the real system, the performance difference between the data pattern of the FIR filter and the H.264 decoder is analyzed. As can be seen from the results of FIG. 13, it can be seen that the present invention completes the request for data patterns of the FIR filter and the H.264 decoder using only 52% and 40% . This shows that the memory control apparatus according to the present invention can greatly contribute to improvement of system performance in an actual application system.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (transmission via the Internet). In addition, the computer-readable recording medium may be distributed to a computer system connected to a wired / wireless communication network, and a computer-readable code may be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.

100: memory control device 110: memory
210: memory access request buffer unit 220: memory access request control unit
230: bank control unit 231: first bank buffer unit
232: second bank buffer unit 233: third bank buffer unit
234: Fourth bank buffer unit

Claims (8)

A memory control device for adaptively determining an execution order of a plurality of memory access requests,
A plurality of memory access requests are processed in the inputted order based on the input order of the plurality of memory access requests and the bank and row information of the memory addresses extracted from the memory access request, and memory access requests for the same row of the same bank are sequentially A memory access request buffer unit for determining and storing a memory access request sequence to be processed;
A memory access request controller for reading a memory access request in the order determined by the memory access request buffer unit and distributing a memory access request for each bank and transferring the memory access requests distributed to the banks to the memory in order; And
And a bank controller for storing the memory access requests allocated to the banks in the buffer units for the respective banks within a predetermined number of times and controlling the operation states for the respective banks,
The memory access request control unit checks whether the buffer unit for each bank is empty when allocating a memory access request for each bank, and if a memory access request in order after the memory access request order determined by the memory access request buffer unit is an empty bank And transfers the data to the separate buffer unit. The method according to claim 1,
When the memory access request is filled in the memory access request control unit for a predetermined number of times, the first bank buffer unit, which is one of the buffer units for each bank, searches for a memory access request for accessing another second bank, And a memory access request for accessing the second bank. The method according to claim 1,
Wherein the memory access request control unit determines that the memory access request for the current processing target memory access request is the same bank as the memory access request read before the current processing target memory access request, Wherein the memory access request for accessing the bank other than the bank corresponding to the sequence after the memory access request is transferred to the memory before the current access target memory access request. The method according to claim 1,
Wherein the memory access request control unit transfers a memory access request distributed for each bank to the buffer unit for each bank and transfers a memory access command to the memory according to a control signal of the bank control unit. 5. The method according to any one of claims 1 to 4,
Wherein the memory is an SDRAM. A memory control method performed by a memory control device adaptively determining an execution order of a plurality of memory access requests,
(a) the memory access request control unit sequentially reading a plurality of memory access requests from the memory access request buffer unit;
(b) the memory access request control unit checking whether the first bank buffer unit is empty based on first bank information corresponding to a memory address extracted in an n-th memory access request;
(c) if the first bank buffer unit is empty, transfers the n-th memory access request to the first bank buffer unit, and if the first bank buffer unit is not empty, Reading a memory access request in which the bank information of the address is the second bank;
(d) checking whether the second bank buffer unit is empty, and if the second bank buffer unit is empty, transferring a memory access request in which the bank information of the memory address is a second bank to the second bank buffer unit; And
(e) storing the order in which the memory access requests are transferred to the buffer units for the respective banks, and transferring the instructions of the bank control units to the memory in order,
The step (e)
(e1) a plurality of memory access requests stored in the buffer units of the respective banks are transferred to a memory in accordance with an input order, and a second memory access request, which is input in the next order of the first memory access request, Determining whether the access request is the same row of the same bank as the first memory access request and the memory address; And
(e2) if the second memory access request is the same row of the same bank as the first memory access request, the second memory access command is continuously transferred to the memory, and the second memory access request is transferred to the first memory access Transferring a command generated according to an input order to a plurality of memory access requests stored in the second bank buffer unit during a waiting cycle for opening a new row if the request is another row of the same bank; The memory control method comprising: The method according to claim 6,
Wherein the memory is an SDRAM. A computer-readable recording medium storing a program for causing a computer to execute the memory control method according to claim 6 or 7.

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