CN104965678A - Solid-state storage control method and apparatus and solid-state storage device - Google Patents
Solid-state storage control method and apparatus and solid-state storage device Download PDFInfo
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Abstract
The invention discloses a solid-state storage control method and apparatus and a solid-state storage device. The solid-state storage control method is applied to the solid-state storage control apparatus; the solid-state storage control apparatus comprises at least two processing modules; the solid-state storage device comprises the solid-state storage control apparatus; the solid-state storage control method comprises the steps of: receiving an operation command sent by an external host; selecting out an execution processing module from the at least two processing modules according to a preset rule by a predetermined arbitration processing module in the at least two processing modules; sending the operation command to the selected execution processing module; and executing the operation command by the execution processing module. With the adoption of the technical scheme, the problem that the performance of an existing dual-core or multi-core solid-state storage controller is equivalent to that of a single-core solid-state storage controller is solved.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of control method of solid-state storage, device and solid storage device.
Background technology
At present, in order to improve the performance of SSD (solid state hard disc, Solid State Drives), and mate the interface bandwidth and storage medium scale that day by day improve, Solid State Storage Controller is all double-core even polycaryon processor, especially solid-state non-volatile memory controller.
But the double-core that current most manufacturer declares or multinuclear are all independently double-core or multinuclear, and the double-core of really or multinuclear.Independently multinuclear refers to that multiple processor is in the process that independently copes with one's problems, and the mode of affairs segmentation is by fixing algorithm and strategy, there is not the overlapping and consistency problem of affairs between multinuclear.Its Problems existing is that between multinuclear, Transaction is unbalanced, has the duty factor of some cores heavier, has some cores almost unloaded, and the performance of equipment is just almost suitable with monokaryon in this case.
Summary of the invention
The control method of a kind of solid-state storage provided by the invention, device and solid storage device, solve existing double-core or multinuclear Solid State Storage Controller, the problem that performance is suitable with monokaryon.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
The control method of a kind of solid-state storage provided by the invention, is applied to the control device of solid-state storage, and the control device of described solid-state storage comprises at least two processing modules, and the control method of described solid-state storage comprises:
Receive the operational order that external host sends; In described at least two processing modules, predetermined arbitration process module selects execution processing module according to preset rules from described at least two processing modules;
Described operational order is sent to the execution processing module selected;
Described execution processing module performs described operational order.
In certain embodiments, in described at least two processing modules predetermined arbitration process module according to preset rules select from described at least two processing modules perform processing module be specially: in described at least two processing modules predetermined arbitration process module according to load balancing principle select from described at least two processing modules least-loaded conduct perform processing module.
In certain embodiments, described arbitration process module performs the operational order that described reception external host sends, and described operational order is sent to the step of the execution processing module selected.
In certain embodiments, described operational order is sent to by bus cache or message table MassageTable the execution processing module selected by described arbitration process module.
In certain embodiments, described operational order is write operation order; Described execution processing module also comprises before performing described operational order: write operation order described in described arbitration process module responds also controls new data and is sent to buffer memory assigned address; Described execution processing module performs described operational order and is specially: described execution processing module is initiated from the write operation being cached to storage array, and new data is write storage medium.Preferably, when the new data in buffer memory is accumulated to default size, at least two processing modules described in entering, predetermined arbitration process module selects according to preset rules the step performing processing module from described at least two processing modules.
In certain embodiments, described operational order is read operation order; Described execution processing module performs described operational order and is specially: described execution processing module, according to the mapping table MappingTable of described read operation order query logic block address to physical block address, initiates read operation to storage array.
The control device of a kind of solid-state storage provided by the invention, comprising:
At least two processing modules, described at least two processing modules comprise predetermined arbitration process module, described arbitration process module is used for from described at least two processing modules, selecting execution processing module according to preset rules, and described execution processing module is used for operation command;
Receiver module, for receiving the operational order that external host sends;
Sending module, for sending to described execution processing module by described operational order.
In certain embodiments, described arbitration process module performs processing module specifically for selecting the conduct of least-loaded from described at least two processing modules according to load balancing principle.
In certain embodiments, described receiver module and described sending module are integrated in described arbitration process module.
In certain embodiments, described sending module is specifically for sending to described execution processing module by bus cache or message table MassageTable by described operational order.
In certain embodiments, described receiver module is specifically for receiving the write operation order of external host transmission; Described arbitration process module is also sent to buffer memory assigned address for responding described write operation order and controlling new data; New data, specifically for initiating from the write operation being cached to storage array, is write storage medium by described execution processing module.
In certain embodiments, described arbitration process module, specifically for when the new data in buffer memory is accumulated to default size, enters and from described at least two processing modules, selects according to preset rules the step performing processing module.
In certain embodiments, described receiver module is specifically for receiving the read operation order of external host transmission; Described execution processing module, specifically for according to the mapping table MappingTable of described read operation order query logic block address to physical block address, initiates read operation to storage array.
A kind of solid storage device provided by the invention, comprises the control device of the solid-state storage described in above-mentioned any one.
The present invention, by determining arbitration process module in the control device of solid-state storage, execution processing module is selected according to preset rules by arbitration process module, the mode of the operational order of main frame is performed again by execution processing module, achieve real double-core and the multinuclear of the control device of solid-state storage, affairs distribution in the control device of solid-state storage between each processing module is decided by arbitration process module, for double-core or multinuclear Solid State Storage Controller, after determining arbitration processor, decided the distribution of affairs by arbitration processor between core and core, what such benefit was that task process can be very average distributes to each core, each core all is fully dispatched, performance increases substantially.
Accompanying drawing explanation
The process flow diagram of the control method of the solid-state storage that Fig. 1 provides for one embodiment of the invention;
The schematic diagram of the control device of the solid-state storage that Fig. 2 provides for one embodiment of the invention;
The schematic diagram of the solid storage device that Fig. 3 provides for one embodiment of the invention.
Embodiment
The solid-state storage stated in the present invention stores including, but not limited to non-volatile solid.The information interaction of bus cache or MassageTable (message table) can be passed through between arbitration process module and execution processing module.Arbitration process module can be the same processing module in the control device of solid-state storage with execution processing module, preferably, is the different disposal module in the control device of solid-state storage.By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
The process flow diagram of the control method of the solid-state storage that Fig. 1 provides for one embodiment of the invention, the control method of this solid-state storage, be applied to the control device of solid-state storage, the control device of this solid-state storage comprises at least two processing modules, the control method of this solid-state storage please refer to Fig. 1, comprises following flow process:
The operational order that S101, reception external host send; In described at least two processing modules, predetermined arbitration process module selects execution processing module according to preset rules from described at least two processing modules.
The operational order that main frame sends can be write operation order, also can be read operation order.This step first can determine arbitration process module from described at least two processing modules, received the operational order of external host transmission again by arbitration process module, arbitration process module selects execution processing module according to preset rules again from described at least two processing modules.
The mode pre-determining arbitration process module from described at least two processing modules including, but not limited to: artificially set, or automatically select present load minimum as arbitration process module.
Arbitration process module according to preset rules select from described at least two processing modules perform processing module mode including, but not limited to: according to load balancing principle select from described at least two processing modules least-loaded conduct perform processing module.Such as: the situation performed according to order, remaining order conduct that is minimum or IDLE state is selected to perform processing module.
S102, described operational order is sent to the execution processing module selected.
Described operational order can be sent to by arbitration process module the execution processing module selected by this step, and described operational order can be sent to by bus cache or MassageTable the execution processing module selected by arbitration process module.
S103, described execution processing module perform described operational order.
The present embodiment, if what step S101 received is the write operation order that external host sends, then can also comprise in step S101: this write operation order of arbitration process module responds also controls new data and is sent to equipment buffer memory (cache) assigned address from leading to the equipment interface of main frame; The LBA (Logical Block Address, logical block addresses) of new data is inserted corresponding new data LBAT (LBA table) by arbitration process module again; After new data is accumulated to pre-sizing (such as the Physical Page of a non-volatile memory medium), arbitration process module selects execution processing module according to preset rules again from described at least two processing modules; Again accumulative new data and corresponding LBAT are sent to the execution processing module selected, or notify the new data that the execution processing module selected adds up and the corresponding position of LBAT in equipment buffer memory, perform processing module from this position acquisition; After execution processing module gets accumulative new data and corresponding LBAT, according to the information of record in Other Table (other list items) in step S103, initiate the write operation from cache to storage array; After new data is write storage medium by execution processing module, corresponding LBAT can also be read further, determine PBA (physical block address), initiate the operation changing Mapping Table (mapping table of LBA to PBA) simultaneously; After this sequence of tasks completes, perform processing module and can also notify arbitration process module further, this time write operation completes; Arbitration process module finally by equipment interface to main frame send that the corresponding command completes mutual.
The present embodiment, if what step S101 received is the read operation order that external host sends, then in step S103, perform after processing module receives read operation order and inquire about Mapping Table, read operation is initiated to storage array, when the data read pass to cache or again after interface transfers to main frame from storage array, perform the notified read operation of processing module and complete; Afterwards, perform processing module and further the information that this read operation completes can be returned to arbitration process module, arbitration process module again according to the state that data complete, initiate cache transmit to the data of main frame or send directly to main frame that the corresponding command completes mutual.
For performing when processing module does garbage reclamation and the interaction process of arbitration process module, comprise following process:
Perform processing module and initiate requests for arbitration to arbitration process module, require the LBA of correspondence to carry out garbage reclamation process; After arbitration process module receives request, first the LBAT of new data is inquired about, see whether new data hits and (performing the LBA of garbage reclamation data, new data whether is had to operate this LBA, if had, then there is hit, otherwise not hit), if not hit, arbitration process module will be initiated to perform processing module by Massage Table and carry out garbage reclamation; If there is hit, arbitration process module notice performs processing module, has which LBA hit, does not need to carry out garbage reclamation, initiates the garbage reclamation operation needing to carry out simultaneously.Perform between processing module and arbitration process module and undertaken alternately by bus cache or Massage Table.
The schematic diagram of the control device of the solid-state storage that Fig. 2 provides for one embodiment of the invention, as shown in Figure 2, the control device of solid-state storage comprises:
At least two processing module (211 to 21m, m is more than or equal to 2), described at least two processing modules (211 to 21m) comprise predetermined arbitration process module, described arbitration process module is used for from described at least two processing modules, selecting execution processing module according to preset rules, and described execution processing module is used for operation command;
Receiver module 22, for receiving the operational order that external host sends;
Sending module 23, for sending to described execution processing module by described operational order.
In certain embodiments, described arbitration process module performs processing module specifically for selecting the conduct of least-loaded from described at least two processing modules (211 to 21m) according to load balancing principle.
In certain embodiments, receiver module 22 and sending module 23 are integrated in described arbitration process module, namely performed the operational order of described reception external host transmission by arbitration process module, and described operational order is sent to the function of described execution processing module.
In certain embodiments, sending module 23 is specifically for sending to described execution processing module by bus cache or message table MassageTable by described operational order.
In certain embodiments, receiver module 22 is specifically for receiving the write operation order of external host transmission; Described arbitration process module is also sent to buffer memory assigned address for responding described write operation order and controlling new data; New data, specifically for initiating from the write operation being cached to storage array, is write storage medium by described execution processing module.
In certain embodiments, described arbitration process module, specifically for when the new data in buffer memory is accumulated to default size, enters and from described at least two processing modules (211 to 21m), selects according to preset rules the step performing processing module.
In certain embodiments, receiver module 22 is specifically for receiving the read operation order of external host transmission; Described execution processing module, specifically for according to the mapping table Mapping Table of described read operation order query logic block address to physical block address, initiates read operation to storage array.
The present invention also provides a kind of solid storage device, comprises the control device of the solid-state storage described in above-mentioned any one.The schematic diagram of the solid storage device that Fig. 3 provides for one embodiment of the invention, as shown in Figure 3, solid storage device comprises equipment interface, equipment buffer memory, storage medium array and controller, equipment interface is used for being connected with external host, the control device of controller and solid-state storage provided by the invention, comprise N+1 processing module, i.e. CPU0, CPU1 to CPUN.
Design of the present invention is illustrated further below by three embodiments.
Wherein in an embodiment, have three cores in the controller of solid storage device, namely three processors (CPU0, CPU1 and CPU2) are for the process of Firmware (firmware) instruction and scheduling.Wherein, CPU0 is arbitration process module, is mainly used in the order sent from equipment interface processing host, and to instruction arbitration and call allocation process; CPU1 and CPU2 is mainly used in performing instruction that arbitration process module sends and controls corresponding storage medium array.The content assignment relevant with multinuclear process that in the present embodiment, equipment cache manages, is preset with following region in cache:
A region, what the main frame for equipment reception was sent writes data;
B region, for the LAB table of data write by main frame in cache;
Above two regions are by CPU0, and namely arbitration process module is safeguarded;
Region c is information interaction district, is mainly used in the information interaction between arbitration process module and execution processing module and handshake process, and one's respective area is safeguarded jointly by arbitration process module and execution processing module;
Region d is the mapping table of LBA to the PBA of whole solid-state storage array, is jointly safeguarded by execution processing module;
Region e is other tables irrelevant with multinuclear of each CPU independent processing.
The write operation order that CPU0 is sent by equipment interface Receiving Host, when CPU0 receives the write operation order that main frame sends, respond this write operation order and starting outfit be interfaced to equipment cache data transmission, after new data is sent to cache assigned address, the LBA of new data is inserted corresponding new data LBAT by CPU0; After new data is accumulated to pre-sizing (such as the Physical Page of a non-volatile memory medium), CPU0 is according to the size of CPU1 and CPU2 load, or according to the size of CPU0, CPU1 and CPU2 three load, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU1, then CPU1 is as execution processing module, and CPU0 will add up new data (Newsdata from interface) and the LBAT of correspondence issues CPU1 by information interaction district; After CPU1 receives, initiate from equipment cache to the write operation of non-volatile memory array according to the information recorded in Other Table, new data is write non-volatile memory medium, after write, CPU1 will read corresponding LBAT, initiate the operation of change MappingTable simultaneously; After this sequence of tasks completes, CPU1 is again by the interactive information notice CPU0 in Massage Table, and this time write operation completes; CPU0 finally by equipment interface to main frame send that the corresponding command completes mutual.
When CPU0 receives by equipment interface the read operation order that main frame sends, CPU0 judges which least-loaded of CPU1 and CPU2, or CPU0 judges CPU0, which least-loaded of CPU1 and CPU2 three, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU1, then CPU1 is as execution processing module, read operation order is issued CPU1 by Massage Table by CPU0, CPU1 inquires about Mapping Table after receiving read operation order, read operation is initiated to non-volatile memory array, when read data passes to equipment cache or after equipment interface transfers to main frame from non-volatile memory array, CPU1 read operation completes, CPU1 receives after read operation completes information, by Massage Table, the information that this read operation completes is returned to CPU0, CPU0 again according to the state that data complete, initiating equipment be cached to main frame data transmission or directly to main frame send that the corresponding command completes mutual.
When CPU1 does garbage reclamation, CPU1 initiates requests for arbitration by Massage Table to CPU0, requires the LBA of correspondence to carry out garbage reclamation process; After CPU0 receives request, first can inquire about the LBAT of new data, see the situation whether new data hits, if not hit, CPU0 will initiate CPU1 by MassageTable and carry out garbage reclamation; If there is hit, CPU0 will notify CPU1 by Massage Table, have which LBA hit, not need to carry out garbage reclamation, initiate the garbage reclamation operation needing to carry out simultaneously.
In another embodiment, identical with a upper embodiment, have three cores in the controller of solid storage device, namely three processors (CPU0, CPU1 and CPU2) are for the process of Firmware (firmware) instruction and scheduling.Wherein, CPU0 is arbitration process module, is mainly used in the order sent from equipment interface processing host, and to instruction arbitration and call allocation process; CPU1 and CPU2 is mainly used in performing instruction that arbitration process module sends and controls corresponding storage medium array.With a upper embodiment unlike, there is bus cache between CPU0 and CPU1, CPU0 and CPU2, direct instruction interaction can be carried out by bus cache.In the present embodiment, the content assignment relevant with multinuclear process of cache management, is preset with following region in cache:
A region, what the main frame for equipment reception was sent writes data;
B region, for the LAB table of data write by main frame in cache;
Above two regions are by CPU0, and namely arbitration process module is safeguarded;
Region c is the mapping table of LBA to the PBA of whole solid-state storage array, is jointly safeguarded by execution processing module;
Region d is other tables irrelevant with multinuclear of each CPU independent processing.
The write operation order that CPU0 is sent by equipment interface Receiving Host, when CPU0 receives the write operation order that main frame sends, CPU0 responds this write operation order and the data that starting outfit is interfaced to equipment cache are transmitted, after new data is sent to cache assigned address, corresponding new data LBAT is inserted in the LBA address of new data by CPU0; After new data is accumulated to pre-sizing (such as the Physical Page of a non-volatile memory medium), CPU0 is according to the size of CPU1 and CPU2 load, or according to the size of CPU0, CPU1 and CPU2 three load, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU1, then CPU1 is as execution processing module, this write operation order is issued CPU1 by bus cache by CPU0, and notifies the position of the LBAT place equipment cache of CPU1 new data and correspondence; After CPU1 receives, obtain the LBAT of new data and correspondence, according to the information recorded in Other Table, initiate from equipment cache to the write operation of non-volatile memory array, new data is write storage medium, after write, CPU1 will read corresponding LBAT, initiate the operation of change Mapping Table simultaneously; After this sequence of tasks completes, CPU1 is again by the interactive information notice CPU0 in bus cache, and this time write operation completes; CPU0 finally by equipment interface to main frame send that the corresponding command completes mutual.
When CPU0 receives by equipment interface the read operation order that main frame sends, CPU0 judges which least-loaded of CPU1 and CPU2, or CPU0 judges CPU0, which least-loaded of CPU1 and CPU2 three, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU1, then CPU1 is as execution processing module, read operation order is issued CPU1 by bus cache by CPU0, CPU1 receives rear inquiry MappingTable, read operation is initiated to non-volatile memory array, when read data passes to equipment cache or after equipment interface transfers to main frame from non-volatile memory array, CPU1 read operation completes, CPU1 receives after read operation completes information, by bus cache, the information that this read operation completes is returned to CPU0, CPU0 again according to the state that data complete, initiating equipment be cached to main frame data transmission or directly to main frame send that the corresponding command completes mutual.
When CPU1 does garbage reclamation, CPU1 initiates requests for arbitration by bus cache to CPU0, requires the LBA of correspondence to carry out garbage reclamation process; After CPU0 receives request, first can inquire about the LBAT of new data, see the situation whether new data hits, if not hit, CPU0 will initiate CPU1 by bus cache and carry out garbage reclamation; If there is hit, CPU0 will notify CPU1 by bus cache, have which LBA hit, not need to carry out garbage reclamation, initiate the garbage reclamation operation needing to carry out simultaneously.
In another embodiment, have 4 cores in the controller of solid storage device, namely 4 processors (CPU0, CPU1, CPU2 and CPU3) are for the process of Firmware (firmware) instruction and scheduling.Wherein, CPU0, CPU1 as arbitration process module, can be mainly used in the order sent from equipment interface processing host, and to instruction arbitration and call allocation process; CPU2 and CPU3 is mainly used in performing instruction that arbitration process module sends and controls corresponding storage medium array.The content assignment relevant with multinuclear process that in the present embodiment, equipment cache manages, is preset with following region in cache:
A region, what the main frame for CPU0 process was sent writes data;
B region, the LAB table of data write by the main frame for CPU0 process in cache;
Two regions are safeguarded by CPU0 above;
C region, what the main frame for CPU1 process was sent writes data;
D region, the LAB table of data write by the main frame for CPU1 process in cache;
Two regions are safeguarded by CPU1 above;
Region e is information interaction district, is mainly used in the information interaction between arbitration process module and execution processing module and handshake process, and one's respective area is safeguarded jointly by arbitration process module and execution processing module;
Region f is the mapping table of LBA to the PBA of whole solid-state storage array, is jointly safeguarded by execution processing module;
Region g is other tables irrelevant with multinuclear of each CPU independent processing.
When main frame sends write operation order by equipment interface, judge module is according to can as the CPU0 of arbitration process module in controller, the load of both CPU1, select the arbitration process module as this operation that load is less, the load of the present embodiment hypothesis CPU1 is less, then select the arbitration process module that CPU1 operates as this, this judge module can be arranged in the equipment interface of solid storage device, or be arranged in the controller of solid storage device, or be a standalone module in solid storage device, be connected between equipment interface and controller.Determine that CPU1 is as after this arbitration process module operated, the write operation command transfer sent by main frame is to CPU1, CPU1 responds this write operation order and the data that starting outfit is interfaced to cache are transmitted, after new data is sent to cache assigned address, corresponding new data LBAT is inserted in the LBA address of new data by CPU1; After new data is accumulated to pre-sizing (such as the Physical Page of a non-volatile memory medium), CPU1 is according to the size of CPU2 and CPU3 load, or according to the size of CPU0, CPU1, CPU2 and CPU3 load, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU2, then CPU2 is as execution processing module, and the LBAT of accumulative new data and correspondence is issued CPU2 by information interaction district by CPU1; After CPU2 receives, according to the information recorded in OtherTable, initiate the write operation from equipment cache to non-volatile memory array, new data is write storage medium, after write, CPU2 will read corresponding LBAT, initiate the operation of change MappingTable simultaneously; After this sequence of tasks completes, CPU2 is again by the interactive information notice CPU1 in MassageTable, and this time write operation completes; CPU1 finally by equipment interface to main frame send that the corresponding command completes mutual.
When main frame sends read operation order by equipment interface, judge module is according to can as the CPU0 of arbitration process module in controller, the load of both CPU1, select the arbitration process module as this operation that load is less, the load of the present embodiment hypothesis CPU1 is less, then select the arbitration process module that CPU1 operates as this, the read operation command transfer sent by main frame is to CPU1, CPU1 responds this read operation order, CPU1 judges which least-loaded of CPU2 and CPU3, or CPU1 judges CPU0, CPU1, which least-loaded of CPU2 and CPU3, select one of least-loaded as performing processing module, suppose in the present embodiment present load minimum for CPU2, then CPU2 is as execution processing module, CPU1, by Massage Table, CPU2 is issued in read operation order, CPU2 inquires about MappingTable after receiving read operation order, and initiate read operation to non-volatile memory array, when read data passes to equipment cache or after equipment interface transfers to main frame from non-volatile memory array, CPU2 read operation completes, CPU2 receives after read operation completes information, by Massage Table, the information that this read operation completes is returned to CPU1, CPU1 again according to the state that data complete, initiating equipment be cached to main frame data transmission or directly to main frame send that the corresponding command completes mutual.
When CPU2 does garbage reclamation, CPU2 initiates requests for arbitration by Massage Table to CPU1, requires the LBA of correspondence to carry out garbage reclamation process; After CPU1 receives request, first can inquire about the LBAT of new data, see whether new data has hit situation, if not hit, CPU1 will initiate CPU2 by MassageTable and carry out garbage reclamation; If there is hit, CPU1 will notify CPU2 by Massage Table, have which LBA hit, not need to carry out garbage reclamation, initiate the garbage reclamation operation needing to carry out simultaneously.
The present invention, by the control device of solid-state storage, if core some in the controller of solid storage device is as arbitration process module, come according to certain rule by arbitration process module, manage throughout between module as load balancing principle and carry out affairs distribution, affairs are distributed to the minimum core of present load to process, make each core all by fully scheduling, performance increases substantially.
Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (15)
1. a control method for solid-state storage, is applied to the control device of solid-state storage, and the control device of described solid-state storage comprises at least two processing modules, it is characterized in that, the control method of described solid-state storage comprises:
Receive the operational order that external host sends; In described at least two processing modules, predetermined arbitration process module selects execution processing module according to preset rules from described at least two processing modules;
Described operational order is sent to the execution processing module selected;
Described execution processing module performs described operational order.
2. the control method of solid-state storage as claimed in claim 1, it is characterized in that, in described at least two processing modules predetermined arbitration process module according to preset rules select from described at least two processing modules perform processing module be specially: in described at least two processing modules predetermined arbitration process module according to load balancing principle select from described at least two processing modules least-loaded conduct perform processing module.
3. the control method of solid-state storage as claimed in claim 1, is characterized in that, described arbitration process module performs the operational order that described reception external host sends, and described operational order is sent to the step of the execution processing module selected.
4. the control method of solid-state storage as claimed in claim 3, it is characterized in that, described operational order is sent to by bus cache or message table MassageTable the execution processing module selected by described arbitration process module.
5. the control method of solid-state storage as claimed in claim 1, it is characterized in that, described operational order is write operation order;
Described execution processing module also comprises before performing described operational order: write operation order described in described arbitration process module responds also controls new data and is sent to buffer memory assigned address;
Described execution processing module performs described operational order and is specially: described execution processing module is initiated from the write operation being cached to storage array, and new data is write storage medium.
6. the control method of solid-state storage as claimed in claim 5, it is characterized in that, when the new data in buffer memory is accumulated to default size, at least two processing modules described in entering, predetermined arbitration process module selects according to preset rules the step performing processing module from described at least two processing modules.
7. the control method of solid-state storage as claimed in claim 1, it is characterized in that, described operational order is read operation order; Described execution processing module performs described operational order and is specially: described execution processing module, according to the mapping table MappingTable of described read operation order query logic block address to physical block address, initiates read operation to storage array.
8. a control device for solid-state storage, is characterized in that, comprising:
At least two processing modules, described at least two processing modules comprise predetermined arbitration process module, described arbitration process module is used for from described at least two processing modules, selecting execution processing module according to preset rules, and described execution processing module is used for operation command;
Receiver module, for receiving the operational order that external host sends;
Sending module, for sending to described execution processing module by described operational order.
9. the control device of solid-state storage as claimed in claim 8, is characterized in that, described arbitration process module performs processing module specifically for selecting the conduct of least-loaded from described at least two processing modules according to load balancing principle.
10. the control device of solid-state storage as claimed in claim 8, it is characterized in that, described receiver module and described sending module are integrated in described arbitration process module.
The control device of 11. solid-state storage as claimed in claim 10, is characterized in that, described sending module is specifically for sending to described execution processing module by bus cache or message table MassageTable by described operational order.
The control device of 12. solid-state storage as claimed in claim 8, is characterized in that, the write operation order that described receiver module sends specifically for receiving external host; Described arbitration process module is also sent to buffer memory assigned address for responding described write operation order and controlling new data; New data, specifically for initiating from the write operation being cached to storage array, is write storage medium by described execution processing module.
The control device of 13. solid-state storage as claimed in claim 12, it is characterized in that, described arbitration process module, specifically for when the new data in buffer memory is accumulated to default size, enters and from described at least two processing modules, selects according to preset rules the step performing processing module.
The control device of 14. solid-state storage as claimed in claim 8, is characterized in that, the read operation order that described receiver module sends specifically for receiving external host; Described execution processing module, specifically for according to the mapping table MappingTable of described read operation order query logic block address to physical block address, initiates read operation to storage array.
15. 1 kinds of solid storage devices, is characterized in that, comprise the control device of the solid-state storage as described in any one of claim 8 to 14.
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