CN102938419B - A kind of self-aligned silicide transistor and its manufacture method - Google Patents
A kind of self-aligned silicide transistor and its manufacture method Download PDFInfo
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- CN102938419B CN102938419B CN201210507600.8A CN201210507600A CN102938419B CN 102938419 B CN102938419 B CN 102938419B CN 201210507600 A CN201210507600 A CN 201210507600A CN 102938419 B CN102938419 B CN 102938419B
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Abstract
The invention provides the transistor with self-aligned silicide and its manufacture method.The transistor with self-aligned silicide, including：One substrate；It is formed at the grid structure on the substrate；It is formed at the source drain region in the substrate of the grid structure both sides；It is formed at the first self-aligned metal silicate layer in the source drain region；The metal nitride layer stacked gradually and metal level being formed on the first self-aligned metal silicate layer, the metal nitride layer and metal level are spaced with the grid structure, and the second autoregistration polycide layer being formed on the grid structure.According to the present invention the transistor with self-aligned silicide, it is possible to achieve further reduction contact resistance while avoid source and drain section by through purpose.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of self-aligned silicide transistor and its manufacture method.
Background technology
Current most of integrated circuits are all integrated multiple transistors, and multiple transistor interconnection collaborations complete certain function,
When transistor AND gate other assemblies are connected, the contact resistance of transistor can influence the operational effect of whole integrated circuit.
In order to reduce contact resistance, a kind of self-aligned silicide being commonly used（SALICIDE）Transistor.From right
During the formation process of eka-silicon compound, it is necessary first to after grid etching and source and drain injection is completed, many in the way of sputtering
Layer of metal layer is deposited on crystal silicon（Generally Ti, cobalt or Ni）, then carry out the chicken fire processing that is rapidly heated for the first time（RTA）, make
Polysilicon surface and the metal of deposit react, and form metal silicide.
Metal silicide（SILICIDE）It is that a kind of compound state that physics-chemical reaction is formed is passed through by metal and silicon, its
Conductive characteristic is between metal and silicon.In order to further reduce resistance, it may also pass through multiple chicken fire and form more low resistance
Silicide is connected.
As shown in figure 1, the self-aligned silicide transistor 100 of prior art includes：Substrate 101, it is formed on substrate 101
Grid structure 102, be formed at the both sides of grid structure 102 the surface of substrate 101 the first self-aligned metal silicate 103
With the second self-aligned metal silicate 104 being formed on grid structure 102.
With the raising of integrated circuit integrated level, the size of transistor requires also less and less, and contact resistance is to whole
What the influence of integrated circuit also became increasingly protrudes, it is therefore desirable to smaller contact resistance., can in order to further reduce contact resistance
To select the thickness of the first self-aligned metal silicate 103 doing thickness, but increased first self-aligned metal silicate of thickness,
The source and drain section in its lower substrate is easily formed through, therefore further reduction contact resistance can not be realized.For these reasons,
Influence of the contact resistance to the higher and higher integrated circuit of integrated level becomes more and more prominent.
The content of the invention
The present invention provides a kind of transistor and its manufacture method with self-aligned silicide, reaches and further reduces contact
Avoided while resistance source and drain section by through purpose, to solve in above-mentioned high integrated circuit contact resistance to integrated circuit shadow
Ring prominent technology topic.
In order to solve the above technical problems, the present invention provides a kind of transistor with self-aligned silicide, including：
One substrate；
It is formed at the grid structure on the substrate；
It is formed at the source drain region in the substrate of the grid structure both sides；
It is formed at the first self-aligned metal silicate layer in the source drain region；
The metal nitride layer stacked gradually and metal level being formed on the first self-aligned metal silicate layer, institute
Metal nitride layer and metal level is stated to be spaced with the grid structure, and
It is formed at the second autoregistration polycide layer on the grid structure.
Optionally, the metal level is formed by metallic cobalt.
Optionally, the metal nitride layer is formed by titanium nitride.
Optionally, the thickness range of the first self-aligned metal silicate layer isDescribed second from right
The thickness range of quasi- polycide layer is
Optionally, the thickness range of the metal nitride layer is
Optionally, the thickness range of the metal level is
Optionally, the substrate is silicon substrate.
Accordingly, the present invention also provides a kind of manufacture method of the transistor with self-aligned silicide, including：
One substrate is provided；
Grid structure is formed over the substrate；
Source drain region is formed in the substrate of the grid structure both sides；
The first self-aligned metal silicate layer is formed in the source drain region；
The metal stacked gradually separated with the grid structure is formed on first self-aligned metal silicate layer
Nitride layer and metal level, and
The second autoregistration polycide layer on the grid structure.
Optionally, formed in the source drain region in the first self-aligned metal silicate layer step, including：
Initial metal layer, metal nitride layer and metal are sequentially formed on the substrate surface and grid structure surface
Layer；
First time chicken fire is carried out to the substrate, to form the first self-aligned metal silicate in the source drain region
Layer.
Optionally, also include after the first self-aligned metal silicate layer step is formed：
Patterned mask layer is formed on the metal level；
Etching removes the part metal level and metal nitride layer, to form the layer successively separated with the grid structure
Folded metal nitride layer and metal level.
Optionally, formed on the metal level in patterned mask layer step, including：
Formed on the metal level on photoresist layer；
Hard mask layer is formed on the photoresist layer；
Etching removes part hard mask layer and exposes part photoresist；
Etching removes the part photoresist exposed, exposes the part metal level.
Optionally, the hard mask layer is silicon oxide layer.
Optionally, the thickness range of the silicon oxide layer is
Optionally, formed in the source drain region in the first self-aligned metal silicate layer step, including：
Initial metal layer is formed on substrate surface and grid structure surface is stated；
First time chicken fire is carried out to the substrate, to form the first self-aligned metal silicate in the source drain region
Layer.
Optionally, also include after the first self-aligned metal silicate layer step is formed：
Metal nitride layer and metal level are sequentially formed on first self-aligned metal silicate layer；
Etching removes the part metal level and metal nitride layer, to form the layer successively separated with the grid structure
Folded metal nitride layer and metal level.
Optionally, also include after the second autoregistration polycide layer step on the grid structure, it is right
The substrate carries out second of chicken fire.
Optionally, the fiery temperature range of second of chicken is 650 DEG C ~ 900 DEG C, the fiery time range of second of chicken be 20Sec ~
40Sec。
Optionally, the fiery temperature range of the first time chicken is 500 DEG C ~ 700 DEG C, first time chicken fire time range be 10Sec ~
20Sec。
In the transistor with self-aligned silicide of the present invention, first is formed with the source drain region from right
Metalloid silicide layer, first self-aligned metal silicate layer on be formed with the grid structure separate according to
The metal nitride layer and metal level of secondary stacking.In the transistor, contacting with external line composition contact resistance includes the
Resistance, the resistance of the resistance of metal nitride layer and metal level of one self-aligned metal silicate layer.Therefore increase can be passed through
The thickness of metal level or the thickness of metal nitride layer, and be not necessary to by increasing by the first self-aligned metal silicate
The thickness of layer, you can to reach the purpose of reduction contact resistance, therefore the first self-aligned metal silicate layer is avoided through source
The risk of leaking joint, it is achieved thereby that further reduce contact resistance while avoid source and drain section by through purpose.
Brief description of the drawings
Fig. 1 is the structural representation of the transistor with self-aligned silicide of prior art；
Fig. 2-Fig. 9 is in each step in the transistor fabrication process with self-aligned silicide of the embodiment of the present invention one
Structural representation；
Figure 10-Figure 15 is in each step in the transistor fabrication process with self-aligned silicide of the embodiment of the present invention two
Structural representation.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
It can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, come further to do in detail below in conjunction with the accompanying drawings
Explanation.
Embodiment one
As shown in Fig. 2 the transistor 200 with self-aligned silicide of the present embodiment includes：One substrate 201, it is formed at
Grid structure 202 on the substrate, the source drain region 203 being formed in the substrate 201 of the both sides of grid structure 202,
It is formed at the first self-aligned metal silicate layer 204 in the source drain region 203, is formed at the first autoregistration metallic silicon
The metal nitride layer 205 and metal level 206 stacked gradually in compound layer 204, and be formed on the grid structure 202
Second autoregistration polycide layer 207.Wherein, the metal nitride layer 205 and metal level 206 and the grid knot
Structure is spaced.
Describe the manufacture of the transistor 200 with self-aligned silicide of the present embodiment in detail with reference to Fig. 2 to Fig. 9
Journey.
First, as shown in Figure 3 there is provided a substrate 201, grid structure 202 is formed on the substrate 201.Optionally, institute
Substrate 201 is stated for silicon substrate, the grid structure 202 includes polysilicon gate and grid oxic horizon.
Then, as shown in figure 4, using ion implantation, the shape in the substrate 201 of the both sides of grid structure 202
Into source drain region 203.
Then, as shown in figure 5, sequentially forming initial metal layer on the surface of substrate 201 and the surface of grid structure 202 is stated
208th, metal nitride materials layer 209 and metal material layer 210.The initial metal layer 208 and the metal level 210 are by gold
Belong to cobalt（Co）Formed, the metal nitride materials layer 209 is by titanium nitride（TiN）Formed.It is preferred that, the nitride metal
The thickness range of thing material layer 209 is The thickness range of the metal material layer 210 is
Then, as shown in fig. 6, carrying out first time chicken fire to the substrate 201, in the source drain region 203 formation the
One self-aligned metal silicate layer 204, and the formation metal silicide 211 on the grid structure 202.Described first from right
The thickness range of metalloid silicide layer isIt is preferred that, the fiery temperature range of the first time chicken is 500 DEG C ~
700 DEG C, first time chicken fire time range is 10Sec ~ 20Sec.
Then, as shown in fig. 7, forming photoresist layer 212 on the metal material layer 210, and in the photoresist layer
Upper 212 form hard mask layer 213.It is preferred that, the hard mask layer 213 is silicon oxide layer, the thickness model of the silicon oxide layer 213
Enclose for
Then, as shown in figure 8, dry etching etching, which removes part hard mask layer, exposes part photoresist, formed patterned
Mask layer 214.Then the part photoresist for removing and exposing is etched again, exposes the part metal material layer 210.
Then, as shown in figure 9, etching removes the part metal material layer 210 and metal nitride materials layer 209, with
The metal nitrogen stacked gradually separated with the grid structure 202 is formed on first self-aligned metal silicate layer 204
Compound material layer 209 and metal material layer 210.Meanwhile, the metal silicide of the side wall of grid structure 202 is also etched,
The surface of the grid structure 202 forms the second autoregistration polycide layer 207.It is preferred that, second autoregistration
Polycide layer thickness range be
Then, etching removes patterned mask layer 214 and photoresist layer 212., can be with order to further reduce sheet resistance
Second of chicken fire is carried out to the substrate 201, it is preferred that the fiery temperature range of second of chicken is 650 DEG C ~ 900 DEG C, second
Chicken fire time range is 20Sec ~ 40Sec.So far the transistor 200 with self-aligned silicide as shown in Figure 2 is formd.
In the present embodiment, the initial metal layer 208, metal nitride materials layer 209 and all shapes of metal material layer 210
Before first time chicken fire described in Cheng Yu.During ability etching removes part metals layer 210 and metal nitride 209, in order to keep away
Exempt from photoresist to be etched completely, it is necessary to use the mask layer with hard mask.
Embodiment two
There is the crystalline substance of self-aligned silicide in the transistor AND gate embodiment one with self-aligned silicide in the present embodiment
Body tubular construction is identical, will not be repeated here.
The present embodiment is that the initial metal layer is formed at the first time chicken fire with implementing one difference
Before, and metal nitride layer and metal level are formed in after the first time chicken fire.
Describe the manufacture of the transistor 300 with self-aligned silicide of the present embodiment in detail with reference to Figure 10 to Figure 15
Process.
As shown in Figure 10, first there is provided a substrate 301, grid structure 302 is formed on the substrate 301.Then, exist
Source drain region 303 is formed in the substrate 301 of the both sides of grid structure 302.
Then, as shown in figure 11, initial metal layer is formed on the surface of substrate 301 and the surface of grid structure 302 is stated.To institute
State substrate 301 and carry out first time chicken fire, to form the first self-aligned metal silicate layer 304 in the source drain region 303,
And form metal silicide on grid structure 302.
Then, as shown in figure 12, etching removes the metal silicide on the side wall of grid structure 302.
Then, as shown in figure 13, the shape successively on first self-aligned metal silicate layer 304 and grid structure 302
Into metal nitride materials layer 309 and metal material layer 310.
Then, as shown in figure 14, patterned photoresist 311 is formed on the metal material layer 310.
Then, as shown in figure 15, etching removes the part metal material layer 310 and metal nitride materials layer 309, with
Form the metal nitride layer 305 stacked gradually separated with the grid structure 302 and metal level 306.Then, to the lining
Bottom 301 carries out second of chicken fire, the transistor 300 with self-aligned silicide so far formd.
In the present embodiment, the initial metal layer is formed at before the first time chicken fire, and forms nitride metal
First time chicken fire is had been completed when thing material layer 309 and metal material layer 310 and to the etching of metal silicide, therefore carved
During etching off is except part metals material layer 310 and metal nitride materials layer 309, etch period is shorter, therefore need not make
Use hard mask.
In summary, in the transistor with self-aligned silicide of the present invention, in first autoregistration gold
The metal nitride layer stacked gradually separated with the grid structure and metal level are formed with category silicide layer.In the crystalline substance
, can be by increasing the thickness of metal level or the thickness of metal nitride layer in body pipe, and be not necessary to by increase
The thickness of first self-aligned metal silicate layer, you can to reach the purpose of reduction contact resistance, therefore avoid first from right
Metalloid silicide layer runs through the risk of source and drain section, it is achieved thereby that avoiding source and drain section while contact resistance is further reduced
By through purpose.
It should be noted that the embodiment of each in this specification is described by the way of progressive, each embodiment emphasis is said
Bright be all between the difference with other embodiment, each embodiment identical similar portion mutually referring to.
Obviously, those skilled in the art can carry out the spirit of various changes and modification without departing from the present invention to invention
And scope.So, if these modifications and variations of the present invention belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to including these changes and modification.
Claims (18)
1. a kind of transistor with self-aligned silicide, including：
One substrate；
It is formed at the grid structure on the substrate；
It is formed at the source drain region in the substrate of the grid structure both sides；
It is formed at the first self-aligned metal silicate layer in the source drain region；
The metal nitride layer stacked gradually and metal level being formed on the first self-aligned metal silicate layer, the gold
Category nitride layer and metal level are spaced with the grid structure, described to stack gradually metal nitride layer and metal level covering part
Divide first self-alignment silicide layer, and the second autoregistration polycide being formed on the grid structure
Layer.
2. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the metal level is by metal
Cobalt formation.
3. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the metal nitride layer is
Formed by titanium nitride.
4. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the first autoregistration metal
The thickness range of silicide layer isThe thickness range of second autoregistration polycide layer is
5. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the metal nitride layer
Thickness range is
6. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the thickness model of the metal level
Enclose for
7. there is the transistor of self-aligned silicide as claimed in claim 1, it is characterised in that the substrate is silicon substrate.
8. a kind of manufacture method of the transistor with self-aligned silicide as described in claim 1 to 7 any one, including：
One substrate is provided；
Grid structure is formed over the substrate；
Source drain region is formed in the substrate of the grid structure both sides；
The first self-aligned metal silicate layer is formed in the source drain region；
The nitride metal stacked gradually separated with the grid structure is formed on first self-aligned metal silicate layer
Nitride layer and metal level, it is described to stack gradually the first self-alignment silicide layer described in metal nitride layer and metal level covering part,
And
The second autoregistration polycide layer on the grid structure.
9. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 8, it is characterised in that in the source
Formed on drain region in the first self-aligned metal silicate layer step, including：
Initial metal layer, metal nitride layer and metal level are sequentially formed on the substrate surface and grid structure surface；
First time annealing is carried out to the substrate, to form the first self-aligned metal silicate layer in the source drain region.
10. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 9, it is characterised in that formed
Also include after the first self-aligned metal silicate layer step：
Patterned mask layer is formed on the metal level；
Etching removes the part metal level and metal nitride layer, to be formed and stacking gradually of separating of the grid structure
Metal nitride layer and metal level.
11. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 10, it is characterised in that described
Formed on metal level in patterned mask layer step, including：
Formed on the metal level on photoresist layer；
Hard mask layer is formed on the photoresist layer；
Etching removes part hard mask layer and exposes part photoresist；
Etching removes the part photoresist exposed, exposes the part metal level.
12. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 11, it is characterised in that described hard
Mask layer is silicon oxide layer.
13. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 12, it is characterised in that the oxygen
SiClx layer thickness range be
14. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 8, it is characterised in that described
Formed in source drain region in the first self-aligned metal silicate layer step, including：
Initial metal layer is formed on substrate surface and grid structure surface is stated；
First time annealing is carried out to the substrate, to form the first self-aligned metal silicate layer in the source drain region.
15. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 14, it is characterised in that in shape
Also include after into the first self-aligned metal silicate layer step：
Metal nitride layer and metal level are sequentially formed on first self-aligned metal silicate layer；
Etching removes the part metal level and metal nitride layer, to be formed and stacking gradually of separating of the grid structure
Metal nitride layer and metal level.
16. there is the manufacture method of the transistor of self-aligned silicide as claimed in claim 8, it is characterised in that described
Also include after the second autoregistration polycide layer step on grid structure, the substrate is moved back for the second time
Fire.
17. the manufacture method of the transistor with self-aligned silicide as claimed in claim 16, it is characterised in that described the
Double annealing temperature range is 650 DEG C~900 DEG C, and second of annealing time scope is 20Sec~40Sec.
18. the manufacture method of the transistor with self-aligned silicide as described in claim 9 or 14, it is characterised in that institute
It is 500 DEG C~700 DEG C to state first time annealing region, and first time annealing time scope is 10Sec~20Sec.
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| CN201210507600.8A CN102938419B (en) | 2012-11-30 | 2012-11-30 | A kind of self-aligned silicide transistor and its manufacture method |
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| CN201210507600.8A CN102938419B (en) | 2012-11-30 | 2012-11-30 | A kind of self-aligned silicide transistor and its manufacture method |
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| CN102938419B true CN102938419B (en) | 2017-09-19 |
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| CN108573910B (en) * | 2017-03-07 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110911280A (en) * | 2019-12-05 | 2020-03-24 | 上海华虹宏力半导体制造有限公司 | Method for forming metal silicide |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180469B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Low resistance salicide technology with reduced silicon consumption |
| US6281087B1 (en) * | 2000-10-12 | 2001-08-28 | Vanguard International Semiconductor Corporation | Process for fabricating metal silicide layer by using ion metal plasma deposition |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100679224B1 (en) * | 2005-11-04 | 2007-02-05 | 한국전자통신연구원 | The semiconductor device and the manufacturing method thereof |
| US7622348B2 (en) * | 2006-12-28 | 2009-11-24 | Advanced Micro Devices, Inc. | Methods for fabricating an integrated circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180469B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Low resistance salicide technology with reduced silicon consumption |
| US6281087B1 (en) * | 2000-10-12 | 2001-08-28 | Vanguard International Semiconductor Corporation | Process for fabricating metal silicide layer by using ion metal plasma deposition |
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