CN102938391B - Manufacture process of copper interconnection line - Google Patents
Manufacture process of copper interconnection line Download PDFInfo
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- CN102938391B CN102938391B CN201210432401.5A CN201210432401A CN102938391B CN 102938391 B CN102938391 B CN 102938391B CN 201210432401 A CN201210432401 A CN 201210432401A CN 102938391 B CN102938391 B CN 102938391B
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- hard mask
- interconnection line
- photoresistance
- copper interconnection
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Abstract
The invention relates to the semiconductor manufacture field and particularly relates to a manufacture process of a copper interconnection line. According to the manufacture process of the copper interconnection line, an isolating membrane is formed between two layers of light resistance in a double exposure technology by using cross-linking materials in a copper interconnection process with grooves preferred, and through holes and metal groove structures in the light resistance are transferred to a media layer successively, so that the prior art that metal groove etching and through hole etching are divided into two independent steps is replaced, etching steps in a dual damascene metal interconnection line process are effectively reduced, the productivity is improved, and the manufacture cost is decreased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture craft of copper interconnection line.
Background technology
Along with the integrated level of semiconductor chip improves constantly, the characteristic size of transistor is constantly reducing.
After the characteristic size of transistor enters into 130 nm technology node, due to the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes metal interconnected main flow, the manufacture method of the copper conductor extensively adopted now is the embedding technique of Damascus technics, and wherein groove-priority dual damascene process is one of method realizing copper conductor and through hole copper once-forming.
Fig. 1 a-1f is the Structure and Process schematic diagram of groove-priority dual damascene process in background technology of the present invention; As illustrated by figs. 1 a-1f, after deposit low dielectric constant dielectric layer 12 covers the upper surface of silicon substrate 11, the upper surface of coating photoresist 13 blanket dielectric layer 12, adopt photoetching successively, after etching technics forms metallic channel 14 in dielectric layer 12, again be coated with photoresist 15 be full of metallic channel 14 and cover the upper surface of remaining dielectric layer 12, after photoetching, etching technics, the through hole 16 being through to the upper surface of silicon substrate 11 is formed in the bottom of metallic channel 14, finally utilize metal deposition process and chemical mechanical milling tech, form plain conductor 17 and metal throuth hole 18.
And after the characteristic size micro of transistor enters into 32 nanometers and following technology node thereof, single photolithographic exposure can not meet the resolution made needed for intensive linear array figure, so double-pattern (double patterning) forming technique is widely used in the intensive linear array figure of making 32 nanometer and following technology node thereof.
Fig. 2 a-2e is the Structure and Process schematic diagram of double-pattern forming technology in background technology of the present invention; As shown in figs. 2 a-e, deposition substrate film 22, hard mask 23 and photoresist 24 successively in substrate silicon 21, after photoresist 24 is exposed, developing, form photoresistance, and with this photoresistance for mask eat-backs the upper surface of hard mask 23 to the substrate film 22 of part, form the first litho pattern 25 and metallic channel 26 after removing above-mentioned photoresistance, and the length ratio of the first litho pattern 25 and metallic channel 26 is 1:3; Afterwards, be coated with the second photoresist 27 and cover the sidewall of the first litho pattern 25 and the upper surface of upper surface and substrate film 22 exposure thereof, after exposure, development, remove unnecessary photoresist, form the second litho pattern 28 with the first litho pattern 25 equal length in metallic channel 26 middle part; Finally, with the upper surface that the first litho pattern 25 and the second litho pattern 28 are Mask portion etched substrate film 22 to silicon substrate 21, after removing the first above-mentioned litho pattern 25 and the second litho pattern 28, form target lines 29 and metallic channel structure 210, and the length ratio of target lines 29 and metallic channel structure 210 is 1:1, namely target lines 29 and metallic channel structure 210 are combined to form intensive linear array figure.Due to, double-pattern forming technique needs Twi-lithography and etching, and its cost is much larger than traditional single exposure forming technique.Therefore, one of cost direction becoming new technology development reducing double-pattern forming technique.
Summary of the invention
For above-mentioned Problems existing, present invention is disclosed a kind of groove prior copper interconnection manufacture method, mainly a kind of double-exposure technique and the photoresist of dura mater can be formed to make the metal interconnected technique of dual damascene of adopting.
The object of the invention is to be achieved through the following technical solutions:
A manufacture craft for copper interconnection line, wherein, comprises the following steps:
Step S1: after the upper surface of a silicon substrate deposits a low dielectric coefficient medium layer, the first photoresist that coating can form hard mask covers described low dielectric coefficient medium layer;
Step S2: after exposure, development, remove the first unnecessary photoresist, form the first hard mask photoresistance with metallic channel structure;
Step S3: after heating the described first hard mask photoresistance, coating cross-linked material covers the surface of the described first hard mask photoresistance, solidify to form barrier film;
Step S4: the second photoresist that coating can form hard mask is full of described metallic channel structure and covers the upper surface of described hard mask photoresistance; Wherein, described barrier film and described second photoresist immiscible;
Step S5: after exposure, development, remove the second unnecessary photoresist, form the second hard mask photoresistance with through-hole structure;
Step S6: adopt etching technics, after successively the metallic channel structure in the through-hole structure in the described second hard mask photoresistance and the described first hard mask photoresistance being transferred to described low dielectric coefficient medium layer, continue metal deposition process and grinding technics, to form wire metals and via metal;
Wherein, be coated with cross-linked material in step S3 and after cooling curing, remove unnecessary cross-linked material, forming the described barrier film covering the described first hard mask photoresistive surface.
The manufacture craft of above-mentioned copper interconnection line, wherein, containing silylation, silicon alkoxyl or cage type siloxanes etc. in the material of described first photoresist.
The manufacture craft of above-mentioned copper interconnection line, wherein, the main component of described cross-linked material is quaternary ammonium base and amine formed material.
The manufacture craft of above-mentioned copper interconnection line, wherein, heats the temperature to 150 of the described first hard mask photoresistance DEG C to 200 DEG C in step S3.
The manufacture craft of above-mentioned copper interconnection line, wherein, heats the temperature to 170 of the described first hard mask photoresistance DEG C to 180 DEG C in step S3.
The manufacture craft of above-mentioned copper interconnection line, wherein, the ratio of the etching power of described first photoresist and the etching power of described second photoresist is greater than 1.5:1.
The manufacture craft of above-mentioned copper interconnection line, wherein, adopts deionized water to remove described unnecessary cross-linked material in step S3.
The manufacture craft of above-mentioned copper interconnection line, wherein, first with after the upper surface of the described second hard mask photoresistance for the extremely described silicon substrate of low dielectric coefficient medium layer described in mask etching in step S6, remove the described second hard mask photoresistance and described barrier film successively, and with the described first hard mask photoresistance for mask, the remaining low dielectric coefficient medium layer of partial etching, removing the described first hard mask photoresistance, forming metallic channel and through hole in again etching in rear remaining low dielectric coefficient medium layer.
The manufacture craft of above-mentioned copper interconnection line, wherein, plated metal is full of described metallic channel and through hole, carries out planarization after electroplating technology, forms described wire metals and via metal.
The manufacture craft of above-mentioned copper interconnection line, wherein, adopts chemical mechanical milling tech to carry out described planarization.
In sum, the manufacture craft of a kind of copper interconnection line of the present invention, barrier film is formed by adopting between the two-layer photoresistance of cross-linked material in double-exposure technique, and successively the through hole in photoresistance and metallic channel structure are transferred to dielectric layer, thus instead of traditional existing technique metallic channel etching and via etch being divided into two independent processes, effectively reduce the etch step in the metal interconnected Wiring technology of dual damascene, improve production capacity, reduce cost of manufacture.
Accompanying drawing explanation
Fig. 1 a-1f is the Structure and Process schematic diagram of groove-priority dual damascene process in background technology of the present invention;
Fig. 2 a-2e is the Structure and Process schematic diagram of double-pattern forming technology in background technology of the present invention;
Fig. 3 a-3i is the Structure and Process schematic diagram of the method for a kind of copper interconnection line of the present invention.
embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 3 a-3i is the Structure and Process schematic diagram of the method for a kind of copper interconnection line of the present invention;
As shown in Fig. 3 a-3i, the manufacture craft of a kind of copper interconnection line of the present invention, first, at the upper surface deposit low dielectric constant dielectric layer 32 of silicon substrate 31, coating can form the upper surface of the first photoresist 33 blanket dielectric layer 32 of hard mask, after exposure, development, remove unnecessary photoresist, form the first hard mask photoresistance 331 with metallic channel structure 34; Wherein, containing silylation, silicon alkoxyl or cage type siloxanes etc. in the material of the first photoresist 33.
Secondly, in same development station, after heating the first hard mask photoresistance 331 to 150-200 DEG C, coating main component is that the cross-linked material 35 of quaternary ammonium base and amine formed material is as the disclosed material etc. in United States Patent (USP) (US20100330501), on the upper surface that cross-linked material 35 covers the first hard mask photoresistance 331 and sidewall, because the first hard mask photoresistance 331 has high temperature, cross-linked material 35 and the first hard mask photoresistance 331 are reacted, and remove unnecessary cross-linked material (cross-linked material of blanket dielectric layer 32 upper surface) by deionized water, to form the hard upper surface of mask photoresistance 331 of covering first and the barrier film 36 of sidewall, wherein, preferred heating the first hard mask photoresistance 331 to 170-180 DEG C, as 175 DEG C time, cross-linked material 35 can better react with the first hard mask photoresistance 331.
Afterwards, the second photoresist 37 that coating can form hard mask covers upper surface and the sidewall thereof of barrier film 36, and the metallic channel structure 34 be full of in the first hard mask photoresistance 331, and the ratio of the etching power of the etching power of the first photoresist 33 and the second photoresist 37 is greater than 1.5:1; Remove unnecessary photoresist after exposure, development, form the second hard mask photoresistance 371 with through-hole structure 38; Wherein, barrier film 36 and the second photoresist 37 immiscible.
Finally, after being the upper surface of mask etching dielectric layer 32 to silicon substrate 31 with the second hard mask photoresistance 371, remove the second hard mask photoresistance 371 and barrier film 36 successively, and with the first hard mask photoresistance 331 for after Mask portion etches remaining dielectric layer, metallic channel 39 and through hole 310 is formed in final remaining dielectric layer 321, plated metal such as copper etc. is full of metallic channel 39 and through hole 310, and after adopting electroplating technology, chemical mechanical milling tech is adopted to carry out planarization, final formation wire metals 311 and via metal 321.
In sum, owing to have employed technique scheme, the embodiment of the present invention proposes a kind of manufacture craft of copper interconnection line, barrier film is formed by adopting between the two-layer photoresistance of cross-linked material in double-exposure technique, and successively the through hole in photoresistance and metallic channel structure are transferred to dielectric layer, thus instead of traditional existing technique metallic channel etching and via etch being divided into two independent processes, effectively reduce the etch step in the metal interconnected Wiring technology of dual damascene, improve production capacity, reduce cost of manufacture.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. a manufacture craft for copper interconnection line, is characterized in that, comprises the following steps:
Step S1: after the upper surface of a silicon substrate deposits a low dielectric coefficient medium layer, the first photoresist that coating can form hard mask covers described low dielectric coefficient medium layer;
Step S2: after exposure, development, remove the first unnecessary photoresist, form the first hard mask photoresistance with metallic channel structure;
Step S3: after heating the described first hard mask photoresistance, coating cross-linked material covers the surface of the described first hard mask photoresistance, solidify to form barrier film;
Step S4: the second photoresist that coating can form hard mask is full of described metallic channel structure and covers the upper surface of described hard mask photoresistance; Wherein, described barrier film and described second photoresist immiscible;
Step S5: after exposure, development, remove the second unnecessary photoresist, form the second hard mask photoresistance with through-hole structure;
Step S6: adopt etching technics, after successively the metallic channel structure in the through-hole structure in the described second hard mask photoresistance and the described first hard mask photoresistance being transferred to described low dielectric coefficient medium layer, continue metal deposition process and grinding technics, to form wire metals and via metal; First with after the upper surface of the described second hard mask photoresistance for the extremely described silicon substrate of low dielectric coefficient medium layer described in mask etching, remove the described second hard mask photoresistance and described barrier film successively, and with the described first hard mask photoresistance for mask, the remaining low dielectric coefficient medium layer of partial etching, removing the described first hard mask photoresistance, forming metallic channel and through hole in again etching in rear remaining low dielectric coefficient medium layer;
Wherein, be coated with cross-linked material in step S3 and after cooling curing, remove unnecessary cross-linked material, forming the described barrier film covering the described first hard mask photoresistive surface;
Containing silylation, silicon alkoxyl or cage type siloxanes in the material of described first photoresist.
2. the manufacture craft of copper interconnection line according to claim 1, is characterized in that, the main component of described cross-linked material is quaternary ammonium base and amine formed material.
3. the manufacture craft of copper interconnection line according to claim 1, is characterized in that, heats the temperature to 150 of the described first hard mask photoresistance DEG C to 200 DEG C in step S3.
4. the manufacture craft of copper interconnection line according to claim 1, is characterized in that, heats the temperature to 170 of the described first hard mask photoresistance DEG C to 180 DEG C in step S3.
5. the manufacture craft of copper interconnection line according to claim 1, is characterized in that, the ratio of the etching power of described first photoresist and the etching power of described second photoresist is greater than 1.5:1.
6. the manufacture craft of the copper interconnection line according to claim 1-5 any one, is characterized in that, adopts deionized water to remove described unnecessary cross-linked material in step S3.
7. the manufacture craft of copper interconnection line according to claim 1, is characterized in that, plated metal is full of described metallic channel and through hole, carries out planarization after electroplating technology, forms described wire metals and via metal.
8. the manufacture craft of copper interconnection line according to claim 7, is characterized in that, adopts chemical mechanical milling tech to carry out described planarization.
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| CN201210432401.5A CN102938391B (en) | 2012-11-02 | 2012-11-02 | Manufacture process of copper interconnection line |
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| CN201210432401.5A CN102938391B (en) | 2012-11-02 | 2012-11-02 | Manufacture process of copper interconnection line |
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| CN102938391B true CN102938391B (en) | 2015-01-21 |
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| CN103646921B (en) * | 2013-11-29 | 2016-06-01 | 上海华力微电子有限公司 | The manufacture method of double damask structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556437A (en) * | 2008-02-08 | 2009-10-14 | 台湾积体电路制造股份有限公司 | Method of lithography patterning |
| CN101963755A (en) * | 2009-06-26 | 2011-02-02 | 罗门哈斯电子材料有限公司 | Self-aligned spacer multiple patterning methods |
| CN102751239A (en) * | 2012-07-27 | 2012-10-24 | 上海华力微电子有限公司 | Through hole preferential copper interconnection production method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW587279B (en) * | 2003-03-12 | 2004-05-11 | Macronix Int Co Ltd | Method for forming bi-layer photoresist and application thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556437A (en) * | 2008-02-08 | 2009-10-14 | 台湾积体电路制造股份有限公司 | Method of lithography patterning |
| CN101963755A (en) * | 2009-06-26 | 2011-02-02 | 罗门哈斯电子材料有限公司 | Self-aligned spacer multiple patterning methods |
| CN102751239A (en) * | 2012-07-27 | 2012-10-24 | 上海华力微电子有限公司 | Through hole preferential copper interconnection production method |
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