CN102810511A - Manufacturing method for copper interconnection lines - Google Patents
Manufacturing method for copper interconnection lines Download PDFInfo
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- CN102810511A CN102810511A CN2012103339032A CN201210333903A CN102810511A CN 102810511 A CN102810511 A CN 102810511A CN 2012103339032 A CN2012103339032 A CN 2012103339032A CN 201210333903 A CN201210333903 A CN 201210333903A CN 102810511 A CN102810511 A CN 102810511A
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Abstract
The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method for copper interconnection lines. According to the manufacturing method for copper interconnection lines, provided by the invention, miniature solidified materials are adopted in a slot-prior copper interconnection process to form an isolating film between two layers of light resistors in a double-exposure technology, and through holes and metal slot structures in the light resistors are shifted to media layers sequentially, so that the existing process in which metal slot etching and through hole etching are traditionally regarded as two independent steps is replaced, and further the etching steps in a double Damascus metal interconnection line process are reduced effectively. Therefore, the productivity is improved and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of copper interconnection line.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly being dwindled.
After transistorized characteristic size enters into 130 nm technology node; Because the high-ohmic of aluminium; Copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow; The manufacture method of the copper conductor that extensively adopts now is the embedding technique of Damascus technics, and wherein the preferential dual damascene process of groove is one of method that realizes copper conductor and through hole copper once-forming.
Fig. 1 a-1f is the structure schematic flow sheet of the preferential dual damascene process of groove in the background technology of the present invention; Shown in Fig. 1 a-1f; After deposition low dielectric coefficient medium layer 12 covers the upper surface of silicon substrate 11; The upper surface of coating photoresist 13 blanket dielectric layer 12, adopt photoetching, etching technics in dielectric layer 12, to form metallic channel 14 successively after, be coated with the upper surface that photoresist 15 is full of metallic channel 14 and covers remaining dielectric layer 12 once more; Behind photoetching, etching technics; Form the through hole 16 of the upper surface that is through to silicon substrate 11 in the bottom of metallic channel 14, utilize metal deposition process and chemical mechanical milling tech at last, form plain conductor 17 and metal throuth hole 18.
And after transistorized characteristic size micro enters into 32 nanometers and following technology node thereof; The single photolithographic exposure can not satisfy makes the required resolution of intensive linear array figure, so double-pattern (double patterning) forming technique is widely used in making the intensive linear array figure of 32 nanometers and following technology node thereof.
Fig. 2 a-2e is the structure schematic flow sheet of double-pattern forming technology in the background technology of the present invention; Shown in Fig. 2 a-2e; Deposition substrate film 22, hard mask 23 and photoresist 24 successively on substrate silicon 21; After photoresist 24 made public, develops, form photoresistance, and be the upper surface that mask eat-backs hard mask 23 to the substrate film 22 of part with this photoresistance; Form first litho pattern 25 and metallic channel 26 after removing above-mentioned photoresistance, and the length ratio of first litho pattern 25 and metallic channel 26 is 1:3; Afterwards; Be coated with second photoresist 27 and cover the sidewall of first litho pattern 25 and the upper surface of upper surface and substrate film 22 exposures thereof; After exposure, the development, remove unnecessary photoresist, form second litho pattern 28 in metallic channel 26 middle parts with first litho pattern, 25 equal length; At last; With first litho pattern 25 and second litho pattern 28 is the upper surface of mask partial etching substrate film 22 to silicon substrate 21; After removing above-mentioned first litho pattern 25 and second litho pattern 28; Form target lines 29 and metallic channel structure 210, and the length ratio of target lines 29 and metallic channel structure 210 is 1:1, promptly target lines 29 are combined to form intensive linear array figure with metallic channel structure 210.Because the double-pattern forming technique needs Twi-lithography and etching, its cost is much larger than traditional single exposure forming technique.Therefore, the cost of reduction double-pattern forming technique becomes one of direction of new technology development.
Summary of the invention
To the problem of above-mentioned existence, the present invention has disclosed the preferential copper-connection manufacture method of a kind of groove, mainly is that a kind of double-exposure technique and photoresist that can form dura mater of adopting made the metal interconnected technology of dual damascene.
The objective of the invention is to realize through following technical proposals:
A kind of manufacture method of copper interconnection line wherein, may further comprise the steps:
Step S1: after the upper surface of a silicon substrate deposited a low dielectric coefficient medium layer, first photoresist that coating can form hard mask covered said low dielectric coefficient medium layer;
Step S2: after exposure, the development, remove the first unnecessary photoresist, form the first hard mask photoresistance with metallic channel structure;
Step S3: in same development station, coating micro curing materials covers the surface of the said first hard mask photoresistance, adds the thermosetting barrier film;
Step S4: second photoresist that coating can form hard mask is full of said metallic channel structure and covers the upper surface of said hard mask photoresistance; Wherein, said barrier film and said second photoresist are immiscible;
Step S5: after exposure, the development, remove the second unnecessary photoresist, form the second hard mask photoresistance with through-hole structure;
Step S6: adopt etching technics; After successively the metallic channel structure in the through-hole structure in the said second hard mask photoresistance and the said first hard mask photoresistance being transferred to said low dielectric coefficient medium layer; Continue metal deposition process and grinding technics, to form lead metal and via metal;
Wherein, when carrying out heating process among the step S3, the surface of the said micro curing materials and the said first hard mask photoresistance is reacted after, remove unnecessary micro curing materials, form and cover the surperficial said barrier film of the said first hard mask photoresistance.
The manufacture method of above-mentioned copper interconnection line wherein, contains siloyl group, silicon alkoxyl or cage type siloxanes in the material of said first photoresist.
The manufacture method of above-mentioned copper interconnection line, wherein, said micro curing materials is the micro auxiliary film.
The manufacture method of above-mentioned copper interconnection line wherein, adopts-30 ℃ to+30 ℃ temperature to form said barrier film among the step S3.
The manufacture method of above-mentioned copper interconnection line wherein, adopts the deionized water solution of deionized water or surfactant to remove said unnecessary micro curing materials among the step S3.
The manufacture method of above-mentioned copper interconnection line, wherein, the ratio of the etching power of the etching power of said first photoresist and said second photoresist is greater than 1.5:1.
The manufacture method of above-mentioned copper interconnection line wherein, is removed unnecessary silanization material through heating evaporation among the step S3.
The manufacture method of above-mentioned copper interconnection line; Wherein, after elder generation is the said low dielectric coefficient medium layer of mask etching to the upper surface of said silicon substrate with the said second hard mask photoresistance among the step S6, remove said second hard mask photoresistance and the said barrier film successively; And be grinding with the said first hard mask photoresistance; The remaining low dielectric coefficient medium layer of partial etching is removed the said first hard mask photoresistance, after etching once more, forms metallic channel and through hole in the remaining low dielectric coefficient medium layer.
The manufacture method of above-mentioned copper interconnection line, wherein, plated metal is full of said metallic channel and through hole, carries out planarization behind the electroplating technology, forms said lead metal and via metal.
The manufacture method of above-mentioned copper interconnection line wherein, adopts chemical mechanical milling tech to carry out said planarization.
In sum; The manufacture method of a kind of copper interconnection line of the present invention; Form barrier film through adopting between the two-layer photoresistance of micro curing materials in double-exposure technique, and successively the through hole in the photoresistance and metallic channel structure are transferred to dielectric layer, thereby substituted traditional existing technology that metallic channel etching and via etch is divided into two independent processes; Reduced the etch step in the metal interconnected Wiring technology of dual damascene effectively, improved production capacity, reduce cost of manufacture.
Description of drawings
Fig. 1 a-1f is the structure schematic flow sheet of the preferential dual damascene process of groove in the background technology of the present invention;
Fig. 2 a-2e is the structure schematic flow sheet of double-pattern forming technology in the background technology of the present invention;
Fig. 3 a-3i is the structure schematic flow sheet of the method for a kind of copper interconnection line of the present invention.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 3 a-3i is the structure schematic flow sheet of the method for a kind of copper interconnection line of the present invention;
Shown in Fig. 3 a-3i; The manufacture method of a kind of copper interconnection line of the present invention, at first, at the upper surface deposition low dielectric coefficient medium layer 32 of silicon substrate 31; Coating can form the upper surface of first photoresist, 33 blanket dielectric layer 32 of hard mask; After exposure, the development, remove unnecessary photoresist, form the first hard mask photoresistance 331 with metallic channel structure 34; Wherein, contain siloyl group, silicon alkoxyl or cage type siloxanes etc. in the material of first photoresist 33.
Secondly; In same development station; Coating micro curing materials 35 is like the micro cured film etc.; (also can the silicon substrate 31 with first hard mask photoresistance 331 structures be placed into and have in the reaction chamber that is full of the silanization material gas) on the upper surface and sidewall that cover the first hard mask photoresistance 331; The heating environment temperature is in-30 ℃ to+30 ℃ scopes; The micro curing materials 35 and the first hard mask photoresistance 331 are reacted, and remove unnecessary micro curing materials (the micro curing materials of blanket dielectric layer 32 upper surfaces), cover the upper surface of the first hard mask photoresistance 331 and the barrier film 36 of sidewall with formation through the deionized water solution of deionized water or surfactant; Wherein, preferred heating environment temperature can better make the micro curing materials 35 and the first hard mask photoresistance 331 react to 100-200 ℃.
Afterwards; Coating can form the upper surface and the sidewall thereof of second photoresist, the 37 covering barrier films 36 of hard mask; And be full of the metallic channel structure 34 in the first hard mask photoresistance 331, and the ratio of the etching power of the etching power of first photoresist 33 and second photoresist 37 is greater than 1.5:1; Unnecessary photoresist is removed in exposure, the back of developing, and forms the second hard mask photoresistance 371 with through-hole structure 38; Wherein, the barrier film 36 and second photoresist 37 are immiscible.
At last; After being the upper surface of mask etching dielectric layer 32 to silicon substrate 31 with the second hard mask photoresistance 371; Remove the second hard mask photoresistance 371 and barrier film 36 successively, and after be the remaining dielectric layer of mask partial etching with the first hard mask photoresistance 331, formation metallic channel 39 and through hole 310 in final remaining dielectric layer 321; Plated metal such as copper etc. are full of metallic channel 39 and through hole 310; And behind the employing electroplating technology, adopt chemical mechanical milling tech to carry out planarization, finally form lead metal 311 and via metal 321.
In sum; Owing to adopted technique scheme; The embodiment of the invention proposes a kind of manufacture method of copper interconnection line; Form barrier film through adopting between the two-layer photoresistance of micro curing materials in double-exposure technique, and successively the through hole in the photoresistance and metallic channel structure are transferred to dielectric layer, thereby substituted traditional existing technology that metallic channel etching and via etch is divided into two independent processes; Reduced the etch step in the metal interconnected Wiring technology of dual damascene effectively, improved production capacity, reduce cost of manufacture.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (10)
1. the manufacture method of a copper interconnection line is characterized in that, may further comprise the steps:
Step S1: after the upper surface of a silicon substrate deposited a low dielectric coefficient medium layer, first photoresist that coating can form hard mask covered said low dielectric coefficient medium layer;
Step S2: after exposure, the development, remove the first unnecessary photoresist, form the first hard mask photoresistance with metallic channel structure;
Step S3: in same development station, coating micro curing materials covers the surface of the said first hard mask photoresistance, adds the thermosetting barrier film;
Step S4: second photoresist that coating can form hard mask is full of said metallic channel structure and covers the upper surface of said hard mask photoresistance; Wherein, said barrier film and said second photoresist are immiscible;
Step S5: after exposure, the development, remove the second unnecessary photoresist, form the second hard mask photoresistance with through-hole structure;
Step S6: adopt etching technics; After successively the metallic channel structure in the through-hole structure in the said second hard mask photoresistance and the said first hard mask photoresistance being transferred to said low dielectric coefficient medium layer; Continue metal deposition process and grinding technics, to form lead metal and via metal;
Wherein, when carrying out heating process among the step S3, the surface of the said micro curing materials and the said first hard mask photoresistance is reacted after, remove unnecessary micro curing materials, form and cover the surperficial said barrier film of the said first hard mask photoresistance.
2. the manufacture method of copper interconnection line according to claim 1 is characterized in that, contains siloyl group, silicon alkoxyl or cage type siloxanes in the material of said first photoresist.
3. the manufacture method of copper interconnection line according to claim 1 is characterized in that, said micro curing materials is the micro auxiliary film.
4. the manufacture method of copper interconnection line according to claim 1 is characterized in that, adopts-30 ℃ to+30 ℃ temperature to form said barrier film among the step S3.
5. the manufacture method of copper interconnection line according to claim 1 is characterized in that, adopts the deionized water solution of deionized water or surfactant to remove said unnecessary micro curing materials among the step S3.
6. the manufacture method of copper interconnection line according to claim 1 is characterized in that, the ratio of the etching power of the etching power of said first photoresist and said second photoresist is greater than 1.5:1.
7. according to the manufacture method of any described copper interconnection line of claim 1-6, it is characterized in that, remove unnecessary silanization material through heating evaporation among the step S3.
8. the manufacture method of copper interconnection line according to claim 7; It is characterized in that; After being the said low dielectric coefficient medium layer of mask etching to the upper surface of said silicon substrate with the said second hard mask photoresistance earlier among the step S6; Remove said second hard mask photoresistance and the said barrier film successively, and be grinding, the remaining low dielectric coefficient medium layer of partial etching with the said first hard mask photoresistance; Remove the said first hard mask photoresistance, after etching once more, form metallic channel and through hole in the remaining low dielectric coefficient medium layer.
9. the manufacture method of copper interconnection line according to claim 8 is characterized in that, plated metal is full of said metallic channel and through hole, carries out planarization behind the electroplating technology, forms said lead metal and via metal.
10. the manufacture method of copper interconnection line according to claim 9 is characterized in that, adopts chemical mechanical milling tech to carry out said planarization.
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| CN2012103339032A CN102810511A (en) | 2012-09-11 | 2012-09-11 | Manufacturing method for copper interconnection lines |
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| CN2012103339032A CN102810511A (en) | 2012-09-11 | 2012-09-11 | Manufacturing method for copper interconnection lines |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367192A (en) * | 2013-07-09 | 2013-10-23 | 上海华力微电子有限公司 | Method for detecting under-etching and deficiency defect of through hole |
| CN110415966A (en) * | 2019-07-30 | 2019-11-05 | 新纳传感系统有限公司 | Coil and preparation method thereof |
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| US5935762A (en) * | 1997-10-14 | 1999-08-10 | Industrial Technology Research Institute | Two-layered TSI process for dual damascene patterning |
| US6350674B1 (en) * | 1999-04-05 | 2002-02-26 | Seiko Epson Corporation | Manufacturing method for semiconductor device having a multilayer interconnect |
| US20040180528A1 (en) * | 2003-03-12 | 2004-09-16 | Ching-Yu Chang | Method of forming a dual-layer resist and application thereof |
| CN1947068A (en) * | 2004-04-09 | 2007-04-11 | Az电子材料（日本）株式会社 | Water-soluble resin composition and method of forming pattern therewith |
| CN101266941A (en) * | 2007-03-15 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Dual damascene process |
| CN101556437A (en) * | 2008-02-08 | 2009-10-14 | 台湾积体电路制造股份有限公司 | Method of lithography patterning |
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2012
- 2012-09-11 CN CN2012103339032A patent/CN102810511A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5935762A (en) * | 1997-10-14 | 1999-08-10 | Industrial Technology Research Institute | Two-layered TSI process for dual damascene patterning |
| US6350674B1 (en) * | 1999-04-05 | 2002-02-26 | Seiko Epson Corporation | Manufacturing method for semiconductor device having a multilayer interconnect |
| US20040180528A1 (en) * | 2003-03-12 | 2004-09-16 | Ching-Yu Chang | Method of forming a dual-layer resist and application thereof |
| CN1947068A (en) * | 2004-04-09 | 2007-04-11 | Az电子材料（日本）株式会社 | Water-soluble resin composition and method of forming pattern therewith |
| CN101266941A (en) * | 2007-03-15 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Dual damascene process |
| CN101556437A (en) * | 2008-02-08 | 2009-10-14 | 台湾积体电路制造股份有限公司 | Method of lithography patterning |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367192A (en) * | 2013-07-09 | 2013-10-23 | 上海华力微电子有限公司 | Method for detecting under-etching and deficiency defect of through hole |
| CN103367192B (en) * | 2013-07-09 | 2015-12-09 | 上海华力微电子有限公司 | Detect the method for through hole undercut and through hole disappearance defect |
| CN110415966A (en) * | 2019-07-30 | 2019-11-05 | 新纳传感系统有限公司 | Coil and preparation method thereof |
| CN110415966B (en) * | 2019-07-30 | 2024-03-12 | 新纳传感系统有限公司 | Coil and manufacturing method thereof |
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Application publication date: 20121205 |