CN102810511A - Manufacturing method for copper interconnection lines - Google Patents

Manufacturing method for copper interconnection lines Download PDF

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Publication number
CN102810511A
CN102810511A CN2012103339032A CN201210333903A CN102810511A CN 102810511 A CN102810511 A CN 102810511A CN 2012103339032 A CN2012103339032 A CN 2012103339032A CN 201210333903 A CN201210333903 A CN 201210333903A CN 102810511 A CN102810511 A CN 102810511A
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photoresist
metal
hard mask
copper interconnect
manufacturing
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CN2012103339032A
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Chinese (zh)
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毛智彪
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上海华力微电子有限公司
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Publication of CN102810511A publication Critical patent/CN102810511A/en

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Abstract

The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method for copper interconnection lines. According to the manufacturing method for copper interconnection lines, provided by the invention, miniature solidified materials are adopted in a slot-prior copper interconnection process to form an isolating film between two layers of light resistors in a double-exposure technology, and through holes and metal slot structures in the light resistors are shifted to media layers sequentially, so that the existing process in which metal slot etching and through hole etching are traditionally regarded as two independent steps is replaced, and further the etching steps in a double Damascus metal interconnection line process are reduced effectively. Therefore, the productivity is improved and the manufacturing cost is reduced.

Description

ー种铜互联线的制作方法 The method of making copper interconnects ー species line

技术领域 FIELD

[0001] 本发明涉及半导体制造领域,尤其涉及一种铜互联线的制作方法。 [0001] The present invention relates to semiconductor manufacturing, and more particularly relates to a method for manufacturing a copper interconnect lines.

背景技术 Background technique

[0002] 随着半导体芯片的集成度不断提高,晶体管的特征尺寸在不断縮小。 [0002] With the integration of the semiconductor chip continues to increase, transistor feature sizes shrinking.

[0003] 当晶体管的特征尺寸进入到130纳米技术节点之后,由于铝的高电阻特性,铜互连逐渐替代铝互连成为金属互连的主流,现在广泛采用的铜导线的制作方法是大马士革エ艺的镶嵌技术,其中沟槽优先双大马士革エ艺是实现铜导线和通孔铜一次成形的方法之 [0003] When the feature size of transistors into 130 nm technology node due to the high resistance characteristic of aluminum, copper interconnect gradual replacement of aluminum interconnect metal interconnects become the mainstream, the method of manufacturing copper wire are now widely used for damascene Ester Arts damascene technique wherein trenches are preferentially dual damascene method arts Ester copper wire and a copper through-hole formed in Achieving

o [0004] 图Ia-If为本发明背景技术中沟槽优先双大马士革エ艺的结构流程示意图;如图Ia-If所示,沉积低介电常数介质层12覆盖硅衬底11的上表面后,涂布光刻胶13覆盖介质层12的上表面,依次采用光刻、刻蚀エ艺于介质层12中形成金属槽14后,再次涂布光刻胶15充满金属槽14井覆盖剩余的介质层12的上表面,经过光刻、刻蚀エ艺后,于金属槽14的底部形成贯穿至硅衬底11的上表面的通孔16,最后利用金属沉积エ艺和化学机械研磨エ艺,形成金属导线17和金属通孔18。 Structural schematic flow chart o [0004] FIGS Ia-If present disclosure background art dual damascene trench priority Ester arts; shown in FIG Ia-If, the low-K dielectric layer 12 is deposited to cover the upper surface of the silicon substrate 11 after coating the photoresist 13 covering the upper surface of the dielectric layer 12, followed by photolithography, etching the metallic Ester groove 14 formed in the arts dielectric layer 12, a photoresist 15 is applied again filled with 14 wells covering the remaining metal bath upper surface of the dielectric layer 12 through photolithography, the etching Ester arts, the groove 14 formed in the bottom of the metal to the through holes through the upper surface 16 of the silicon substrate 11, and finally the use of metal deposition and chemical mechanical polishing arts Ester Ester Yi, metal wires 17 and the metal vias 18 are formed.

[0005] 而当晶体管的特征尺寸微缩进入到32纳米及其以下技术节点后,单次光刻曝光已经不能满足制作密集线阵列图形所需的分辨率,于是双重图形(double patterning)成形技术被广泛应用于制作32纳米及其以下技术节点的密集线阵列图形。 [0005] When the feature size of transistors into miniature 32nm technology node and below, a single lithography exposure can not meet the required production line array dense graphics resolution, then double patterning (double patterning) is forming techniques widely used in making the array pattern of dense lines and below 32 nm technology node.

[0006] 图2a_2e为本发明背景技术中双重图形成形エ艺的结构流程示意图;如图2a_2e所示,在衬底硅21上依次沉积衬底膜22、硬掩膜23和光刻胶24,对光刻胶24进行曝光、显影后,形成光阻,并以该光阻为掩膜回蚀部分硬掩膜23至衬底膜22的上表面,去除上述光阻后形成第一光刻图形25和金属槽26,且第一光刻图形25和金属槽26的长度比例为1:3;之后,涂布第二光刻胶27覆盖第一光刻图形25的侧壁及其上表面和衬底膜22暴露的上表面,曝光、显影后,去除多余的光刻胶,于金属槽26中间部位形成与第一光刻图形25相同长度的第二光刻图形28 ;最后,以第一光刻图形25和第二光刻图形28为掩膜部分刻蚀衬底膜22至硅衬底21的上表面,去除上述的第一光刻图形25和第二光刻图形28后,形成目标线条29和金属槽结构210,且目标线条29和金属槽结构210的长度比例为1:1,即目标线条29 Background [0006] FIG 2a_2e double patterning technique of the present invention forming a schematic flow Ester arts structure; 2a_2e shown in FIG, 21 on a silicon substrate, sequentially depositing a base film 22, the hard mask 23 and photoresist 24, photolithography after forming the first photoresist pattern 24 is exposed and after development, a photoresist, and the photoresist as a mask to etch back the upper surface portion of the hard mask film 22 to the substrate 23, removing the photoresist grooves 25 and the metal 26, and the first lithographic pattern and the metal ratio of the length 25 of the groove 26 is 1: 3; then, applying a second photoresist pattern 27 covering a first sidewall 25 and photolithography on the surface, and 22 the exposed surface of the substrate film, exposure, development, the removal of the excess photoresist, a second photolithographic patterning a first lithographic pattern 2528 of the same length formed in an intermediate portion of the metal tank 26; and finally, to a first lithographic patterning lithographic pattern 25 and a second 28 upper surface of substrate 22 to the silicon substrate 21 is partially etched mask film, removing the first lithographic pattern and a second lithographic pattern 25 after 28, to form a target metal lines 29 and groove structure 210, and the target 29 and metal line trench structure 210 is the length ratio of 1: 1, i.e., the target line 29 金属槽结构210组合形成密集线阵列图形。 210 combination of metal line trench structure forming a dense array pattern. 由于,双重图形成形技术需要两次光刻和刻蚀,其成本远大于传统的单次曝光成形技木。 Since, double patterning techniques require forming two photolithography and etching, which is much greater than the cost of a conventional single exposure technique wood molding. 因此,降低双重图形成形技术的成本成为新技术开发的方向之一。 Therefore, reducing the cost of forming dual graphics technology to become one of the new technology development direction.

发明内容 SUMMARY

[0007] 针对上述存在的问题,本发明掲示了ー种沟槽优先铜互连制作方法,主要是ー种采用双重曝光技术和可形成硬膜的光刻胶来制作双大马士革金属互连的エ艺。 [0007] For the above problems, the present invention is illustrated ー kei species preferentially copper interconnection trenches manufacturing method, primarily species ー double exposure technique and a photoresist can form a hard film to make dual damascene metal interconnection Ester art.

本发明的目的是通过下述技术方案实现的: Object of the present invention are achieved by the following technical solution:

一种铜互联线的制作方法,其中,包括以下步骤:步骤SI :在一硅衬底的上表面沉积ー低介电常数介质层后,涂布可形成硬掩膜的第一光刻胶覆盖所述低介电常数介质层; A method of making a copper interconnect lines, comprising the following steps: the SI: After the surface of a silicon substrate of low dielectric constant dielectric layer is deposited ー, covered by the photoresist coating may be formed first hardmask the low dielectric constant dielectric layer;

步骤S2:曝光、显影后,去除多余的第一光刻胶,形成具有金属槽结构的第一硬掩膜光 Step S2: exposing, after development, removing excess first photoresist to form a first hard mask having a light metal trench structure

阻; Resistance;

步骤S3:在同一显影台内,涂布微缩固化材料覆盖所述第一硬掩膜光阻的表面,加热形成隔离膜; Step S3: In the same developing station, the cured coating material covers the surface of the miniature first resist hard mask, forming an isolation film is heated;

步骤S4 :涂布可形成硬掩膜的第二光刻胶充满所述金属槽结构并覆盖所述硬掩膜光阻的上表面;其中,所述隔离膜与所述第二光刻胶不相溶; Step S4: second photoresist coating may be a hard mask structure is filled with the metal bath and the photoresist covering the upper surface of the hard mask; wherein, said separator film and the second resist is not compatibility;

步骤S5:曝光、显影后,去除多余的第二光刻胶,形成具有通孔结构的第二硬掩膜光 Step S5: after exposure and development, removing excess second resist, forming a second hard mask having a light-via structure

阻; Resistance;

步骤S6 :采用刻蚀エ艺,依次将所述第二硬掩膜光阻中的通孔结构和所述第一硬掩膜光阻中的金属槽结构转移至所述低介电常数介质层后,继续金属沉积エ艺和研磨エ艺,以形成导线金属和通孔金属; Step S6: Ester arts using etching, the via structure sequentially second hard mask and photoresist in the groove structure of the first metal hard mask photoresist is transferred to the low-K dielectric layer after metal deposition continued Ester Ester arts processes and grinding, to form the metal wires and metal vias;

其中,步骤S3中进行加热エ艺时,使所述微缩固化材料与所述第一硬掩膜光阻的表面进行反应后,去除多余的微缩固化材料,形成覆盖所述第一硬掩膜光阻表面的所述隔离膜。 Wherein after heating step S3 is performed Ester arts, curing the miniature surface of the first hard mask material is reacted photoresist, removing excess miniature curable material is formed overlying the first hard mask light the surface resistance of the separator.

[0008] 上述的铜互联线的制作方法,其中,所述第一光刻胶的材质中含有硅烷基、硅烷氧基或笼形硅氧烷。 [0008] In the above-described method for manufacturing a copper interconnect lines, wherein the first photoresist material containing a silane group, silane group or a cage siloxane.

[0009] 上述的铜互联线的制作方法,其中,所述微缩固化材料为微缩辅助膜。 [0009] The manufacturing method of the copper interconnect lines, wherein the curable material is a miniature miniature auxiliary film.

[0010] 上述的铜互联线的制作方法,其中,步骤S3中采用_30°C至+30°C的温度形成所述 [0010] The above-described method for manufacturing a copper interconnect lines, wherein, in step S3, using a temperature of _30 ° C to + 30 ° C to form the

隔离膜。 Separator.

[0011] 上述的铜互联线的制作方法,其中,步骤S3中采用去离子水或表面活性剂的去离子水溶液去除所述多余的微缩固化材料。 [0011] The above-described method for manufacturing a copper interconnect lines, wherein, in step S3, the deionized water or deionized water to remove the surfactant excess miniature curable material.

[0012] 上述的铜互联线的制作方法,其中,所述第一光刻胶的刻蚀能力与所述第二光刻胶的刻蚀能力的比值大于1.5:1。 [0012] In the above-described method for manufacturing a copper interconnect lines, wherein a ratio of the first photoresist and etching the second photoresist ability etching capacity is greater than 1.5: 1.

[0013] 上述的铜互联线的制作方法,其中,步骤S3中通过加热蒸发去除多余的硅烷化材料。 [0013] The above-described method for manufacturing a copper interconnect lines, wherein, in step S3, by heating the evaporation material removing excess silane.

[0014] 上述的铜互联线的制作方法,其中,步骤S6中先以所述第二硬掩膜光阻为掩膜刻蚀所述低介电常数介质层至所述硅衬底的上表面后,依次去除所述第二硬掩膜光阻和所述隔离膜,并以所述第一硬掩膜光阻为研磨,部分刻蚀剩余的低介电常数介质层,去除所述第一硬掩膜光阻,于再次刻蚀后剩余的低介电常数介质层中形成金属槽和通孔。 [0014] The manufacturing method of the copper interconnect lines, wherein, prior to the step S6, the second hard mask photoresist as a mask to etch the low-k dielectric layer to the upper surface of the silicon substrate, after sequentially removing the second photoresist and the hard mask insulating film, the first hard mask and the photoresist to an abrasive, etching the remaining portions of the low dielectric constant layer, removing the first hard mask photoresist after metal etching again trenches and vias formed in the low dielectric constant remaining layers.

[0015] 上述的铜互联线的制作方法,其中,沉积金属充满所述金属槽和通孔,电镀エ艺后进行平坦化处理,形成所述导线金属和通孔金属。 [0015] The copper interconnect line production method, wherein a metal is deposited filling the trenches and vias metal plating treatment after flattening Ester arts, and metal wires forming the via metal.

上述的铜互联线的制作方法,其中,采用化学机械研磨エ艺进行所述平坦化处理。 The above-described method for manufacturing a copper interconnect lines, wherein the chemical mechanical polishing Ester arts for the planarization process.

综上所述,本发明ー种铜互联线的制作方法,通过采用微缩固化材料于双重曝光技术中的两层光阻之间形成隔离膜,并依次将光阻中的通孔和金属槽结构转移至介质层,从而替代了传统将金属槽刻蚀和通孔刻蚀分为两个独立步骤的现有エ艺,有效地減少了双大马士革金属互连线エ艺中的刻蚀步骤,提高产能、減少制作成本。 In summary, the present invention ー method of fabricating a copper interconnect lines is formed on the insulating film double exposure technique between two layers of photoresist material is cured by using miniature and successively through holes in the photoresist and the metal slot structure transferred to the dielectric layer, thereby replacing the conventional prior arts Ester metal etching and groove etching vias into two separate steps, effectively reducing the dual damascene metal interconnection line in the etching step arts Eito, improve production capacity, reduce production costs.

附图说明[0016] 图Ia-If为本发明背景技术中沟槽优先双大马士革エ艺的结构流程示意图; BRIEF DESCRIPTION [0016] FIGS Ia-If present disclosure background art trench structure schematic priority dual damascene process Ester arts;

图2a_2e为本发明背景技术中双重图形成形エ艺的结构流程示意图; FIG 2a_2e background art dual flow forming structure diagram of a graphics arts Ester present invention;

图3a_3i是本发明的一种铜互联线的方法的结构流程示意图。 FIG 3a_3i is a structural schematic flow chart of a method of copper wire interconnect of the present invention.

[0017] 具体实施方式 [0017] DETAILED DESCRIPTION

下面结合附图对本发明的具体实施方式作进ー步的说明: DRAWINGS The specific embodiments of the present invention will be further described into ー:

图3a_3i是本发明的一种铜互联线的方法的结构流程示意图; FIG 3a_3i structure is a flowchart of a method of the present invention, the copper wire interconnects a schematic view;

如图3a_3i所示,本发明ー种铜互联线的制作方法,首先,在硅衬底31的上表面沉积低介电常数介质层32,涂布可形成硬掩膜的第一光刻胶33覆盖介质层32的上表面,曝光、显影后,去除多余的光刻胶,形成具有金属槽结构34的第一硬掩膜光阻331 ;其中,第一光刻胶33的材质中含有硅烷基、硅烷氧基或笼形硅氧烷等。 FIG 3a_3i, the present invention ー method of fabricating a copper interconnect lines, first, a low dielectric constant dielectric layer 32 is deposited on the surface of the silicon substrate 31, a hard coating may be formed first photoresist mask 33 covering the upper surface of the dielectric layer 32, exposure, after development, removing excess photoresist, photoresist mask 331 is formed having a first hard metal tank structure 34; wherein the material of the first resist 33 contain a silane group , silane group or a cage siloxane.

[0018] 其次,在同一显影台内,涂布微缩固化材料35如微缩固化膜等,以覆盖第一硬掩膜光阻331的上表面和侧壁上(也可将具有第一硬掩膜光阻331结构的硅衬底31放置入具有充满硅烷化材料气体的反应腔室中),加热环境温度到_30°C至+30°C范围内,使微缩固化材料35与第一硬掩膜光阻331进行反应,并通过去离子水或表面活性剂的去离子水溶液去除多余的微缩固化材料(覆盖介质层32上表面的微缩固化材料),以形成覆盖第一硬掩膜光阻331的上表面及侧壁的隔离膜36 ;其中,优选的加热环境温度至100-200°C,能更好的使微缩固化材料35与第一硬掩膜光阻331进行反应。 [0018] Next, in the same development stage, curing the coating material 35, such as miniature thumbnail cured film so as to cover the upper surface and sidewalls of the first hard mask photoresist 331 (also having a first hard mask 331 silicon substrate photoresist structure 31 is placed into a material having a silane gas filled reaction chamber) and heated to ambient temperature _30 ° C to + 30 ° C range, so that the thumbnail cured material 35 and the first hard mask the reaction photoresist film 331, and the thumbnail to remove excess cured material (32 covers the upper surface of the dielectric layer miniature cured material) in deionized water by deionized water or a surfactant, to form a first hard mask covering the photoresist 331 the upper surface of the insulating film 36 and the sidewall; wherein, preferably heated from ambient temperature to 100-200 ° C, better make miniature cured material 35 is reacted with a first hard mask 331 of photoresist.

[0019] 之后,涂布可形成硬掩膜的第二光刻胶37覆盖隔离膜36的上表面及其侧壁,且充满第一硬掩膜光阻331中的金属槽结构34,且第一光刻胶33的刻蚀能力与第二光刻胶37的刻蚀能力的比值大于I. 5:1 ;曝光、显影后去除多余的光刻胶,形成具有通孔结构38的第ニ硬掩膜光阻371 ;其中,隔离膜36与第二光刻胶37不相溶。 A second insulating film covering the photoresist 37 after [0019] the coating may be formed on the hard mask 36 and the side wall surface, and filled with a metal slot structure 34 of the first hard mask 331 is a photoresist, and the first a ratio of the photoresist 33 and etching ability etching ability second photoresist 37 is greater than I. 5: 1; the exposure, the photoresist after development to remove the excess, formed of Ni having a through hole 38 of the rigid structure photoresist mask 371; wherein the second insulating film 36 and the photoresist 37 is not compatible.

[0020] 最后,以第二硬掩膜光阻371为掩膜刻蚀介质层32至硅衬底31的上表面后,依次去除第二硬掩膜光阻371和隔离膜36,并以第一硬掩膜光阻331为掩膜部分刻蚀剩余的介质层后,于最终剰余的介质层321中形成金属槽39和通孔310,沉积金属如铜等充满金属槽39和通孔310,并采用电镀エ艺后,采用化学机械研磨エ艺进行平坦化处理,最終形成导线金属311和通孔金属321。 [0020] Finally, a second hard mask after the photoresist 371 on the surface of the silicon substrate 32 to the dielectric layer 31 is etched mask, successively removing the second hard mask photoresist film 371 and the separator 36, and with the first a hard mask after the photoresist mask 331 and etching the rest part of the dielectric layer, the groove 39 is formed of metal and vias 310, metal such as copper or the like is deposited on the dielectric layer 321 in the final remainder for surplus metal filled groove 39 and the through hole 310, Ester arts and after electroplating, chemical mechanical polishing planarization process Ester arts, eventually forming a metal wire 311 and the metal vias 321.

[0021] 综上所述,由于采用了上述技术方案,本发明实施例提出一种铜互联线的制作方法,通过采用微缩固化材料于双重曝光技术中的两层光阻之间形成隔离膜,并依次将光阻中的通孔和金属槽结构转移至介质层,从而替代了传统将金属槽刻蚀和通孔刻蚀分为两个独立步骤的现有エ艺,有效地減少了双大马士革金属互连线エ艺中的刻蚀步骤,提高产能、减少制作成本。 [0021] In summary, the use of the above technical solution, embodiments of the present invention provides a method for manufacturing a copper interconnect lines is formed on the insulating film between the double exposure technique by using two layers of photoresist miniature cured material, and sequentially through holes in the resist structure is transferred to the groove and the metal dielectric layer, thereby replacing the conventional prior arts Ester metal etching and groove etching vias into two separate steps, effectively reducing the dual damascene Ester arts metallic interconnect in the etching step, increase productivity, reduce production costs.

[0022] 通过说明和附图,给出了具体实施方式的特定结构的典型实施例,基于本发明精ネ申,还可作其他的转换。 [0022] The description and drawings, given the particular structure of the exemplary embodiment of specific embodiments, the present invention is based on fine ne application, but also for other transformations. 尽管上述发明提出了现有的较佳实施例,然而,这些内容并不作为局限。 Although the foregoing prior proposed invention, the preferred embodiment, however, the content is not by way of limitation.

[0023] 对于本领域的技术人员而言,阅读上述说明后,各种变化和修正无疑将显而易见。 [0023] For those skilled in the art, upon reading the foregoing description, various changes and modifications will no doubt become apparent. 因此,所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。 Accordingly, the appended claims should be considered all alterations and modifications to cover the true spirit and scope of the present invention. 在权利要求书范围内任何和所有等价的范围与内容,都应认为仍属本发明的意图和范围内。 Within the scope of the appended claims and any and all equivalents ranges content, to be considered within the spirit and scope of the present invention still.

Claims (10)

1. 一种铜互联线的制作方法,其特征在于,包括以下步骤: 步骤SI :在一硅衬底的上表面沉积一低介电常数介质层后,涂布可形成硬掩膜的第一光刻胶覆盖所述低介电常数介质层; 步骤S2:曝光、显影后,去除多余的第一光刻胶,形成具有金属槽结构的第一硬掩膜光阻; 步骤S3:在同一显影台内,涂布微缩固化材料覆盖所述第一硬掩膜光阻的表面,加热形成隔离膜; 步骤S4 :涂布可形成硬掩膜的第二光刻胶充满所述金属槽结构并覆盖所述硬掩膜光阻的上表面;其中,所述隔离膜与所述第二光刻胶不相溶; 步骤S5:曝光、显影后,去除多余的第二光刻胶,形成具有通孔结构的第二硬掩膜光阻; 步骤S6 :采用刻蚀工艺,依次将所述第二硬掩膜光阻中的通孔结构和所述第一硬掩膜光阻中的金属槽结构转移至所述低介电常数介质层后,继续金属沉积工艺和研磨工 Depositing a first low-k dielectric layer on a surface of a silicon substrate after forming a hard mask can be applied: 1. A method of making a copper interconnect lines, characterized by, comprising the following steps: Step SI the photoresist covering the low dielectric constant dielectric layer; step S2: exposing, after development, removing excess first photoresist, forming a first groove having a metal hard mask photoresist structure; step S3: in the same developing the table, the cured coating material covers the surface of the miniature first resist hard mask, forming an isolation film heating; step S4: second photoresist coating may be a hard mask structure is filled with the metal bath and covering the upper surface of the hard resist mask; wherein, said separator film and the second photoresist immiscible; step S5: exposing, after development, removing excess second photoresist, having a through hole is formed the second hard mask photoresist structure; step S6: using an etching process, sequentially transferring the metal structure of the tank via structure in the second hard mask photoresist and the photoresist in the first hard mask after the low dielectric constant to the dielectric layer, and a metal deposition process to continue grinding work ,以形成导线金属和通孔金属; 其中,步骤S3中进行加热工艺时,使所述微缩固化材料与所述第一硬掩膜光阻的表面进行反应后,去除多余的微缩固化材料,形成覆盖所述第一硬掩膜光阻表面的所述隔离膜。 To form a via metal wires and a metal; wherein after step S3, the heating process, the surface of the cured material of the first hard mask photoresist miniature reaction to remove excess cured material miniature form covering the surface of the first hard mask photoresist barrier film.
2.根据权利要求I所述的铜互联线的制作方法,其特征在于,所述第一光刻胶的材质中含有硅烷基、硅烷氧基或笼形硅氧烷。 The method of manufacturing a copper interconnect lines according to claim I, wherein the first photoresist material containing a silane group, silane group or a cage siloxane.
3.根据权利要求I所述的铜互联线的制作方法,其特征在于,所述微缩固化材料为微缩辅助膜。 The method of manufacturing a copper interconnect lines according to claim I, wherein the curable material is a miniature miniature auxiliary film.
4.根据权利要求I所述的铜互联线的制作方法,其特征在于,步骤S3中采用-30°C至+30°C的温度形成所述隔离膜。 The method of manufacturing a copper interconnect lines according to claim I, characterized in that, in step S3 using the temperature of -30 ° C to + 30 ° C forming the isolation film.
5.根据权利要求I所述的铜互联线的制作方法,其特征在于,步骤S3中采用去离子水或表面活性剂的去离子水溶液去除所述多余的微缩固化材料。 The method of manufacturing a copper interconnect lines according to claim I, wherein the step S3 deionized water or a surfactant in deionized water removed the excess miniature curable material.
6.根据权利要求I所述的铜互联线的制作方法,其特征在于,所述第一光刻胶的刻蚀能力与所述第二光刻胶的刻蚀能力的比值大于I. 5:1。 6. The method of manufacturing a copper interconnect lines according to claim I, wherein a ratio of the first photoresist and etching the second photoresist ability etching capacity is greater than I. 5: 1.
7.根据权利要求1-6任意一项所述的铜互联线的制作方法,其特征在于,步骤S3中通过加热蒸发去除多余的硅烷化材料。 The manufacturing method of any one of claims 1-6 copper interconnect lines claim, wherein, in step S3, by heating the evaporation material removing excess silane.
8.根据权利要求7所述的铜互联线的制作方法,其特征在于,步骤S6中先以所述第二硬掩膜光阻为掩膜刻蚀所述低介电常数介质层至所述硅衬底的上表面后,依次去除所述第二硬掩膜光阻和所述隔离膜,并以所述第一硬掩膜光阻为研磨,部分刻蚀剩余的低介电常数介质层,去除所述第一硬掩膜光阻,于再次刻蚀后剩余的低介电常数介质层中形成金属槽和通孔。 The manufacturing method of the copper interconnect lines 7 claim, wherein, prior to the step S6, the second hard mask photoresist as a mask to etch the low-k dielectric layer to the rear surface of the silicon substrate, successively removing the second photoresist and the hard mask insulating film, the first hard mask and the photoresist to an abrasive, etching the remaining portions of the low dielectric constant layer removing the first hard mask photoresist after metal etching again trenches and vias formed in the low dielectric constant remaining layers.
9.根据权利要求8所述的铜互联线的制作方法,其特征在于,沉积金属充满所述金属槽和通孔,电镀工艺后进行平坦化处理,形成所述导线金属和通孔金属。 9. The manufacturing method of the copper interconnect lines 8 according to the preceding claims, characterized in that the deposition of the metal filled planarized after the metal trenches and vias, plating process, and forming the metal via metal wires.
10.根据权利要求9所述的铜互联线的制作方法,其特征在于,采用化学机械研磨工艺进行所述平坦化处理。 10. The manufacturing method of the copper interconnect line 9 claim wherein the process is performed using the chemical mechanical polishing planarization process.
CN2012103339032A 2012-09-11 2012-09-11 Manufacturing method for copper interconnection lines CN102810511A (en)

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