CN102931988A

CN102931988A - Complex programmable logic device (CPLD) programme based test system of analog-to-digital (AD) converter

Info

Publication number: CN102931988A
Application number: CN2012104448501A
Authority: CN
Inventors: 薛海英
Original assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Current assignee: Huadong Photoelectric Integrated Device Research Institute
Priority date: 2012-11-08
Filing date: 2012-11-08
Publication date: 2013-02-13
Anticipated expiration: 2032-11-08
Also published as: CN102931988B

Abstract

The invention relates to a CPLD programme based test system of an AD converter. The test system comprises a CPLD programmable control circuit U2, a single chip microcomputer circuit U3, a serial port level converting circuit U5 and a 16-bit serial A/D converter circuit U1, wherein the CPLD programmable control circuit U2, the single chip microcomputer circuit U3, the serial port level converting circuit U5 and the 16-bit serial A/D converter circuit U1 are in protocol communication with a universal asynchronous receiver/transmitter (UART) port through a serial peripheral interface (SPI). Conversion data of the 16-bit serial A/D converter circuit are processed by combination of a single chip microcomputer and a CPLD, the hardware circuit is simple in structure and low in cost, and by the aid of the test system, the conversion error of a 16-bit precision A/D converter is tested to be 4LSB.

Description

A kind of test macro of the AD converter based on CPLD programming

Technical field

The present invention relates to a kind of test of A/D converter, particularly require the test of the rear message transmission rate height of conversion and the demanding A/D change-over circuit of parameters precision.

Background technology

At present, the test point of A/D converter conversion accuracy errors many, that record are large, and message transmission rate is high after the A/D conversion, and the test data reprocessing is complicated.A kind of method of testing of the high-precision a/d converter based on the CPLD programming is proposed for this situation.

Summary of the invention

The objective of the invention is for present A/D converter test point many, when calculation of parameter serial data rate complicated, particularly A/D converter output is higher behind the data measured, a test A/D conversion accuracy error large difficult problem design a kind of test macro of AD converter of programming based on CPLD.

For achieving the above object, the technical solution used in the present invention is: a kind of test macro of the AD converter based on CPLD programming, and it comprises CPLD programmable control circuit U2, single chip circuit U3, serial port level chance-over circuit U5 and 16 bits serial A/D converter circuit U1; Write control 16 bits serial A/D converter circuit U1 among the described CPLD programmable control circuit U2 and start and the program of Collect conversion data and the program of communicating by letter with single chip circuit U3 by the SPI agreement, its control signal output terminals A DRC is connected with the control signal input ADRC of described 16 bits serial A/D converter circuit U1; The data-signal output terminals A DDATA of the translation data of described 16 bits serial A/D converter circuit U1 is connected with the data-signal input ADDATA of the translation data of CPLD programmable control circuit U2; Write among the described single chip circuit U3 and receive CPLD FPGA (Field Programmable Gate Array) control circuit U2 by the data of SPI protocol transmission and process the program and the program of communicating by letter with host computer by the UART agreement of these data, its data-signal input MOSI is connected with the data-signal output MOSI of described CPLD programmable control circuit U2, and its data-signal output TX is connected with the data-signal input TX of described serial port level chance-over circuit U5; The feedback signal output RX of described serial port level chance-over circuit U5 is connected with the feedback signal input RX of described single chip circuit U3 and it is connected with host computer.

It also comprises clock circuit U4, and the clock signal output terminal CLK of described clock circuit U4 is connected with the clock signal input terminal CLK of CPLD FPGA (Field Programmable Gate Array) control circuit U2.

The clock signal input terminal ADCLK of the translation data of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the clock signal output terminal ADCLK of the translation data of described 16 bits serial A/D converter circuit U1.

The busy-idle condition signal input part ADBUSY of the translation data of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the busy-idle condition signal output part ADBUSY of the translation data of described 16 bits serial A/D converter circuit U1.

The clock signal output terminal SCK of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the clock signal input terminal SCK of described single chip circuit U3.

The filter capacitor of the external reset circuit of described single chip circuit U3 and power end, described single chip circuit uses inner crystal oscillator, the reset terminal RST/C2CK series resistance R2 of single chip circuit U3, another termination R1 and the C15 of R2, another termination power of R1, the other end ground connection of C15.

The external a plurality of electric capacity of described serial port level chance-over circuit U5 seal in capacitor C 1 between its 15 pin and 16 pin, seal in capacitor C 2 between its 16 pin and 2 pin, seal in capacitor C 3 between its 1 pin and 3 pin, seal in capacitor C 4 between its 4 pin and 5 pin, seal in capacitor C 13 between its 6 pin and ground wire.

Because technique scheme is used, the present invention compared with prior art has following advantages: the mode that the employing single-chip microcomputer is combined with CPLD is processed the translation data of 16 bits serial A/D converter circuit, and hardware circuit is simple, cost is low; Adopt CPLD to realize communicating by letter between 16 bits serial A/D converter circuit and single-chip microcomputer and host computer as Master control chip; When realizing that the A/D data output rate is 9MHz can with single chip communication; The transformed error that can record 16 precision A/D converters is 4LSB.

Description of drawings

Accompanying drawing 1 is the circuit diagram of 16 bits serial A of the present invention/D change-over circuit;

Accompanying drawing 2 is the circuit diagram of FPGA (Field Programmable Gate Array) control circuit of the present invention;

Accompanying drawing 3 is the circuit diagram of single chip circuit of the present invention;

Accompanying drawing 4 is the circuit diagram of clock circuit of the present invention;

Accompanying drawing 5 is the circuit diagram of serial port level chance-over circuit of the present invention;

Accompanying drawing 6 is the program flow diagram of utilization of the present invention based on the method for the test system and test A/D converter of the high-precision a/d converter of CPLD programming.

Embodiment

The present invention is further described below in conjunction with accompanying drawing.

This test macro based on the high-precision a/d converter of CPLD programming comprises 16 bits serial A/D change-over circuit U1, CPLD programmable control circuit U2, clock circuit U4, single chip circuit U3, serial port level chance-over circuit U5.

As shown in Figure 1, input VHELM0C, VHELM1C, VHELM2C, VHELM3C, TEST, ADCH4, ADCH5 and the GND of 16 bits serial A/D change-over circuit U1 are the input of its inner 8 path analoging switch, its input CHE0, CHE1 and CHE2 are the gating control end of its inner 8 path analoging switch

Shown in Fig. 2,4, CPLD programmable control circuit U2 has input end of clock, and input end of clock is the input CLK of programmable control system, and it is connected with the output CLK of clock circuit U4.The output terminals A DRC of CPLD programmable control circuit U2 is connected with the ADRC input of 16 bits serial A/D change-over circuit U1, the input ADCLK of CPLD programmable control circuit U2 is connected with the ADCLK output of 16 bits serial A/D change-over circuit U1, the input ADDATA of CPLD programmable control circuit U2 is connected with the ADDATA output of 16 bits serial A/D change-over circuit U1, the input ADBUSY of CPLD programmable control circuit U2 is connected with the ADBUSY output of 16 bits serial A/D change-over circuit U1, the output SCK of CPLD programmable control circuit U2 is connected with the SCK input of single chip circuit U3, and the output MOSI of CPLD programmable control circuit U2 is connected with the MOSI input of single chip circuit U3.

As shown in Figure 3, the filter capacitor of the external reset circuit of single chip circuit U3 and power end, described single chip circuit uses inner crystal oscillator, the reset terminal RST/C2CK series resistance R2 of single chip circuit U3, another termination R1 and the C15 of R2, another termination power of R1, the other end ground connection of C15.The output TX of single chip circuit meets the input TX of serial port level chance-over circuit U5, and the input RX of single chip circuit meets the output RX of serial port level chance-over circuit U5.

As shown in Figure 5, the external a plurality of electric capacity of serial port level chance-over circuit U5, wherein, seal in capacitor C 1 between its 15 pin and 16 pin, seal in capacitor C 2 between its 16 pin and 2 pin, seal in capacitor C 3 between its 1 pin and 3 pin, seal in capacitor C 4 between its 4 pin and 5 pin, seal in capacitor C 13 between its 6 pin and ground wire.

Below in conjunction with shown in the accompanying drawing 6 course of action of the present invention is further described.

After system powers on, program is carried out self check and the initial work of system parameters, 16 bits serial A after finishing/D change-over circuit U1 work, judge whether 16 bits serial A/D change-over circuit U1 converts, if do not finish conversion then wait for, if finish conversion then carry out 16 bits serial A/D change-over circuit U1 data acquisition, after image data is finished, simulation SPI agreement sends to single chip circuit U3 after transmission rate is reduced, data herein need to send twice and just can finish, need to judge whether single chip circuit U3 finishes receiving, do not need to wait for if finish, single chip circuit U3 carries out the disposal of gentle filter on the software with the data that receive after finishing, and is after the processing that these data are temporary, again starts 16 bits serial A/D change-over circuit U1 and finishes once circulation, repeatedly after the circulation, be averaged after the data of single chip circuit U3 inside are removed minimum value and maximum by algorithm, this average sent out host computer show, finish the test of 16 a bits serial A/D change-over circuit U1 parameter.

Above-described embodiment only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with technique can understand content of the present invention and according to this enforcement, can not limit protection scope of the present invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.

Claims

1. test macro based on the AD converter of CPLD programming, it is characterized in that: it comprises CPLD programmable control circuit U2, single chip circuit U3, serial port level chance-over circuit U5 and 16 bits serial A/D converter circuit U1; Write control 16 bits serial A/D converter circuit U1 among the described CPLD programmable control circuit U2 and start and the program of Collect conversion data and the program of communicating by letter with single chip circuit U3 by the SPI agreement, its control signal output terminals A DRC is connected with the control signal input ADRC of described 16 bits serial A/D converter circuit U1; The data-signal output terminals A DDATA of the translation data of described 16 bits serial A/D converter circuit U1 is connected with the data-signal input ADDATA of the translation data of CPLD programmable control circuit U2; Write among the described single chip circuit U3 and receive CPLD FPGA (Field Programmable Gate Array) control circuit U2 by the data of SPI protocol transmission and process the program and the program of communicating by letter with host computer by the UART agreement of these data, its data-signal input MOSI is connected with the data-signal output MOSI of described CPLD programmable control circuit U2, and its data-signal output TX is connected with the data-signal input TX of described serial port level chance-over circuit U5; The feedback signal output RX of described serial port level chance-over circuit U5 is connected with the feedback signal input RX of described single chip circuit U3 and it is connected with host computer.

2. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: it also comprises clock circuit U4, and the clock signal output terminal CLK of described clock circuit U4 is connected with the clock signal input terminal CLK of CPLD FPGA (Field Programmable Gate Array) control circuit U2.

3. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: the clock signal input terminal ADCLK of the translation data of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the clock signal output terminal ADCLK of the translation data of described 16 bits serial A/D converter circuit U1.

4. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: the busy-idle condition signal input part ADBUSY of the translation data of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the busy-idle condition signal output part ADBUSY of the translation data of described 16 bits serial A/D converter circuit U1.

5. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: the clock signal output terminal SCK of described CPLD FPGA (Field Programmable Gate Array) control circuit U2 is connected with the clock signal input terminal SCK of described single chip circuit U3.

6. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: the filter capacitor of the external reset circuit of described single chip circuit U3 and power end, described single chip circuit uses inner crystal oscillator, the reset terminal RST/C2CK series resistance R2 of single chip circuit U3, another termination R1 and the C15 of R2, another termination power of R1, the other end ground connection of C15.

7. the test macro of the AD converter based on CPLD programming according to claim 1, it is characterized in that: the external a plurality of electric capacity of described serial port level chance-over circuit U5, seal in capacitor C 1 between its 15 pin and 16 pin, seal in capacitor C 2 between its 16 pin and 2 pin, seal in capacitor C 3 between its 1 pin and 3 pin, seal in capacitor C 4 between its 4 pin and 5 pin, seal in capacitor C 13 between its 6 pin and ground wire.