CN205091569U - Data acquisition circuit, control system and vehicle - Google Patents

Abstract

The utility model discloses a data acquisition circuit, control system and vehicle. The data acquisition circuit includes: micro controller unit (1), data buffer circuit (2), adc (3), wherein, clk port, sdo port, cs port and the sdi port number of pass of micro controller unit (1) according to buffer circuit (2) and SPI bus with the clk port of adc (3), sdo port, cs port, sdi port correspond to be connected, wherein, micro controller unit (1) further includes the GPIO port, the GPIO port of micro controller unit (1) with the ADC conversion of adc (3) is accomplished port INT and is connected. The utility model discloses an in the data acquisition circuit, the GPIO port of micro controller unit (1) with the ADC conversion of adc (3) is accomplished port INT and is connected to can directly acquire ADC's status signal, need not micro controller unit and send the instruction of inquiry ADC operating condition, so can improve the corresponding speed of data, simplified operation.

Description

A kind of data acquisition circuit, control system and vehicle

Technical field

The utility model relates to circuit engineering field, particularly relates to a kind of data acquisition circuit based on spi bus, control system and vehicle.

Background technology

In vehicle electronic circuit, the simulating signal collected usually uses spi bus to be sent to micro controller unit.After the voltage measurement of particularly high-pressure system through often to use the spi bus of isolation and micro controller unit carry out instruction and the transmission of data.Need owing to reading adc data the duty being judged analog to digital converter (ADC) 1 by spi bus, belong to inquiry mode.Data Update needs the fixing cycle, and real time data acquisition is poor.

As shown in Figure 1, its principle of work is as follows for the signal acquisition circuit based on the isolation of SPI signal conventional at present:

Step 11: micro controller unit 1 sends data acquisition instructions by spi bus;

Step 12: the ADC such as time delay complete data conversion;

Step 13: micro controller unit 1 sends inquiry ADC operating state instruction;

Step 14: if data conversion does not complete, jump to step 12, otherwise go to step 15;

Step 15: send adc data transfer instruction;

Step 16: the data receiving ADC passback.

Need owing to reading adc data the duty being judged ADC by spi bus, belong to inquiry mode.ADC completes data conversion and upgrades the cycle needing to fix, and real time data acquisition is poor.

Therefore, wish a kind of technical scheme to overcome or at least alleviate the above-mentioned defect of prior art.

Utility model content

The purpose of this utility model is the above-mentioned defect providing a kind of data acquisition circuit to overcome or at least alleviate prior art.

For achieving the above object, the utility model provides a kind of data acquisition circuit, described data acquisition circuit comprises: micro controller unit, data isolation circuit and analog to digital converter, wherein, the Clk port of described micro controller unit, Sdo port, Cs port and Sdi port by Clk port, Sdo port, the Cs port of data isolation circuit and spi bus and described analog to digital converter, Sdi port is corresponding is connected

Wherein, described micro controller unit comprises GPIO port further, and GPIO port and the ADC of described analog to digital converter of described micro controller unit convert port INT and be connected.

Preferably, the GPIO port of described micro controller unit and described ADC are converted port INT and are interconnected by described data isolation circuit.

Preferably, described data acquisition circuit comprises mux decode circuit and multiplexer coding circuit further,

Wherein, the input end of described mux decode circuit is connected with the Sdi port of described data isolation circuit, and the first output terminal is connected with the Sdi port of described micro controller unit, and the second output terminal is connected with the GPIO port of described micro controller unit;

The output terminal of described multiplexer coding circuit is connected with the Sdi_iso port of described data isolation circuit, and first input end is connected with the Sdi port of described analog to digital converter, and the second input end and the ADC of described analog to digital converter convert port INT and be connected.

Preferably, described mux decode circuit and described multiplexer coding circuit are by the chip selection signal line traffic control of spi bus.

Preferably, the control end of described mux decode circuit is communicated with the Cs port of described micro controller unit; The control end of described multiplexer coding circuit is communicated with the Cs port of described analog to digital converter.

Preferably, described data acquisition circuit comprises voltage collecting device further, and described voltage collecting device is electrically connected with described analog to digital converter.

The utility model also provides a kind of control system, and described control system comprises data acquisition circuit as above.

The utility model also provides a kind of vehicle, and described vehicle comprises data acquisition circuit as above, or control system as above.In data acquisition circuit of the present utility model, GPIO port and the ADC of described analog to digital converter of micro controller unit convert port INT and are connected, thus directly can obtain the status signal of ADC, inquiry ADC operating state instruction is sent without the need to micro controller unit, so data corresponding speed can be improved, simplify the operation.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of the data acquisition circuit of prior art.

Fig. 2 is the schematic circuit of the data acquisition circuit according to the utility model first embodiment.

Fig. 3 is the schematic circuit of the data acquisition circuit according to the utility model second embodiment.

Reference numeral:

1	Micro controller unit	4	Mux decode circuit
				2	Data isolation circuit	5	Multiplexer coding circuit
3	ADC

Embodiment

In the accompanying drawings, use same or similar label to represent same or similar element or there is element that is identical or similar functions.Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.

Data acquisition circuit of the present utility model comprises: micro controller unit, data isolation circuit and analog to digital converter.The Clk port of described micro controller unit, Sdo port, Cs port and Sdi port by Clk port, Sdo port, the Cs port of data isolation circuit and spi bus and described analog to digital converter, Sdi port is corresponding is connected.Wherein, described micro controller unit comprises GPIO port further, and GPIO port and the ADC of described analog to digital converter of described micro controller unit convert port INT and be connected.

In data acquisition circuit of the present utility model, GPIO port and the ADC of described analog to digital converter of described micro controller unit convert port INT and are connected, thus directly can obtain the status signal of ADC, inquiry ADC operating state instruction is sent without the need to micro controller unit, so data corresponding speed can be improved, simplify the operation.

Fig. 2 is the schematic circuit of the data acquisition circuit according to the utility model first embodiment.Data acquisition circuit shown in Fig. 2 comprises: micro controller unit 1, data isolation circuit 2, analog to digital converter 3, mux decode circuit 4 and multiplexer coding circuit 5.Wherein micro controller unit 1 is connected with analog to digital converter 3 by data isolation circuit 2 and spi bus.In other words, micro controller unit 1 is connected with analog to digital converter 3 by the spi bus with data isolation circuit 2.

More specifically, the Clk port of micro controller unit 1, Sdo port, Cs port and Sdi port by Clk port, Sdo port, the Cs port of data isolation circuit 2 and spi bus and analog to digital converter 3, Sdi port is corresponding is connected.

Micro controller unit 1 comprises GPIO port further, and GPIO port and the ADC of analog to digital converter 3 of micro controller unit 1 convert port INT and be connected.Advantageously, as shown in Figure 2, the GPIO port of micro controller unit 1 and ADC are converted port INT and are interconnected by described data isolation circuit 2.

GeneralPurposeInputOutput (universal input/output) is referred to as GPIO, or bus extender.It is the expansion utilizing industrial standard I2C, SMBus or SPI interface to simplify I/O mouth.When microcontroller or chipset do not have enough I/O ports, or when system needs adopt far-end serial communication or control, GPIO product can provide extra control & monitor function.

See Fig. 2, the input end (the right side port in Fig. 2) of mux decode circuit 4 is connected with the Sdi port of data isolation circuit 2, first output terminal (left side upper port) is connected with the Sdi port of micro controller unit 1, and the second output terminal (left side lower port) is connected with the GPIO port of micro controller unit 1.The output terminal (the left side port in Fig. 2) of multiplexer coding circuit 5 is connected with the Sdi_iso port of data isolation circuit 2, first input end (right side upper port) is connected with the Sdi port of analog to digital converter 3, and the second input end and the ADC of analog to digital converter 3 convert port INT (right side lower port) and be connected.

Further, mux decode circuit 4 and multiplexer coding circuit 5 are controlled by the chip selection signal line (Cs line) of spi bus.In the illustrated embodiment, the control end of mux decode circuit 4 is communicated with the Cs port of micro controller unit 1; The control end of multiplexer coding circuit 5 is communicated with the Cs port of analog to digital converter 3.

In a preferred embodiment, described data acquisition circuit comprises voltage collecting device further, and described voltage collecting device is electrically connected with analog to digital converter 3.Thus the voltage of voltage collecting device collection is delivered to micro controller unit 1.

Above-described embodiment increases multiplexer rate matching device decoding circuit on the basis of former design circuit.Use the chip selection signal (Cs) of spi bus by ADC transition status by setting up Direct Communication with microcontroller after data isolation chip.Status poll instruction need not be sent and directly send the read work that data transfer instruction can complete data after microcontroller detects the ready hardware trigger signal of adc data.

When micro controller unit 1 does not start SPI instruction (Cs=" H "), the GPIO port that microcontroller is corresponding is set to input, for detecting the data transition status from ADC feedback.After GPIO receives a low level (namely adc data converts and is ready to), send and read data command and receive ADC valid data.Its workflow is as follows:

Step 21: micro controller unit 1 sends data acquisition instructions by spi bus;

Step 22: micro controller unit 1 monitors GPIO state, can adopt interrupt mode;

Step 23: when receiving effective (GPIO) look-at-me, going to step 24, otherwise jumping to step 22;

Step 24: micro controller unit 1 sends adc data transfer instruction;

Step 25: micro controller unit 1 receives the data of ADC passback.

Relative to traditional repeating query mode, effectively data sampling period be can shorten, data acquisition and treatment effeciency improved.

When Cs (control chip port status) is " H " (high level, or " 1 "), namely spi bus is in not serviceable condition.As shown, the Sdi port of mux decode circuit 4 by connection data buffer circuit and the GPIO port of micro controller unit 1, multiplexer coding circuit 5 is by Sdi_iso port and Adc_State expanding channels, and the ADC being namely connected to ADC converts port (INT).The data that " Sdi_iso port " and " Sdi port " are data isolation circuit 2 (isolating chip) same passage.At this moment micro controller unit 1 directly can read the state that ADC converts port (INT).

When Cs is " L " (low level, or " 0 "), namely spi bus is in serviceable condition.As shown, mux decode circuit 4 will connect Sdi and Sdi passage, and multiplexer coding circuit 5 is by Sdi_iso and Adc_Data expanding channels.At this moment microcontroller can directly read ADC translation data.

SPI is the abbreviation of Serial Peripheral Interface (SPI) (SerialPeripheralInterface).Specifically spi bus is a kind of high speed, full duplex, synchronous communication bus, and on the pin of chip, only take four lines, save the pin of chip, simultaneously for the layout of PCB saves space, provide convenience, just for this characteristic be simple and easy to, nowadays this communication protocol of increasing integrated chip.

The Principle of Communication of SPI is very simple, and it is with master-slave mode work.This pattern has a main equipment and one or more from equipment usually, needs at least 4 lines, in fact 3 also can (during one-way transmission).Also be that all equipment based on SPI is total, they are Sdi (data input), SDo (data output), Clk (clock), Cs (sheet choosing or enable).

(1) Sdo – main equipment data export, and input from device data;

(2) Sdi – main equipment data input, exports from device data;

(3) Clk – clock signal, is produced by main equipment;

(4) Cs – is from equipment chip selection signal, is controlled by main equipment.

Wherein, CS is whether control chip is selected, when that is only having chip selection signal to be prespecified enable signal (noble potential or electronegative potential), just effective to the operation of this chip.This just allows on same bus, connect multiple SPI equipment becomes possibility.

Fig. 3 is the schematic circuit of the data acquisition circuit according to the utility model second embodiment.In the embodiments of figure 3, the GPIO port of micro controller unit directly converts port INT with the ADC of analog to digital converter by rigid line and is connected.This technical scheme eliminates mux decode circuit 4 and multiplexer coding circuit 5, but needs 5 single data transmission lines.

In a not shown alternative, the GPIO port of micro controller unit converts port INT by data isolation circuit 2 with the ADC of analog to digital converter and is connected, but, do not use mux decode circuit 4 and multiplexer coding circuit 5.Like this, the security of data acquisition can be improved.

The utility model also provides a kind of control system, and described control system comprises data acquisition circuit as above.

The utility model also provides a kind of vehicle, and described vehicle comprises data acquisition circuit as above, or control system as above.

Finally it is to be noted: above embodiment only in order to the technical solution of the utility model to be described, is not intended to limit.Those of ordinary skill in the art is to be understood that: can modify to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; These amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the utility model.

Claims (8)

1. a data acquisition circuit, it is characterized in that, comprise: micro controller unit (1), data isolation circuit (2) and analog to digital converter (3), wherein, the Clk port of described micro controller unit (1), Sdo port, Cs port and Sdi port by Clk port, Sdo port, the Cs port of data isolation circuit (2) and spi bus and described analog to digital converter (3), Sdi port is corresponding is connected

Wherein, described micro controller unit (1) comprises GPIO port further, and the GPIO port of described micro controller unit (1) converts port INT with the ADC of described analog to digital converter (3) and is connected.

2. data acquisition circuit as claimed in claim 1, it is characterized in that, the GPIO port of described micro controller unit (1) and described ADC are converted port INT and are interconnected by described data isolation circuit (2).

3. data acquisition circuit as claimed in claim 2, is characterized in that, comprise mux decode circuit (4) and multiplexer coding circuit (5) further,

Wherein, the input end of described mux decode circuit (4) is connected with the Sdi port of described data isolation circuit (2), first output terminal is connected with the Sdi port of described micro controller unit (1), and the second output terminal is connected with the GPIO port of described micro controller unit (1);

The output terminal of described multiplexer coding circuit (5) is connected with the Sdi_iso port of described data isolation circuit (2), first input end is connected with the Sdi port of described analog to digital converter (3), and the second input end converts port INT with the ADC of described analog to digital converter (3) and is connected.

4. data acquisition circuit as claimed in claim 3, is characterized in that, described mux decode circuit (4) and described multiplexer coding circuit (5) are by the chip selection signal line traffic control of spi bus.

5. data acquisition circuit as claimed in claim 4, it is characterized in that, the control end of described mux decode circuit (4) is communicated with the Cs port of described micro controller unit (1); The control end of described multiplexer coding circuit (5) is communicated with the Cs port of described analog to digital converter (3).

6. the data acquisition circuit according to any one of claim 1-5, is characterized in that, comprises voltage collecting device further, and described voltage collecting device is electrically connected with described analog to digital converter (3).

7. a control system, is characterized in that, comprises the data acquisition circuit according to any one of claim 1-6.

8. a vehicle, comprises the data acquisition circuit according to any one of claim 1-6, or control system as described in claim 7.