CN102931315A - Semiconductor structure and manufacture method thereof - Google Patents
Semiconductor structure and manufacture method thereof Download PDFInfo
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- CN102931315A CN102931315A CN2011102275363A CN201110227536A CN102931315A CN 102931315 A CN102931315 A CN 102931315A CN 2011102275363 A CN2011102275363 A CN 2011102275363A CN 201110227536 A CN201110227536 A CN 201110227536A CN 102931315 A CN102931315 A CN 102931315A
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Abstract
The invention provides a semiconductor structure which comprises a c-plane sapphire substrate, a nano structure and an m-plane gallium nitride epitaxial layer, wherein the nano structure is formed on the c-plane sapphire substrate, and the m-plane gallium nitride epitaxial layer is formed on the nano structure of the c-plane sapphire substrate, and a half-peak double amplitude of an X ray rocking curve of the semiconductor structure is 316 arc-seconds. In addition, the root-mean-square surface roughness of the semiconductor structure is 0.3namometer, the semiconductor structure meets the manufacture demand that the root-mean-square surface roughness must be less than +/-0.5nanometer.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture method, particularly a kind of structure and manufacture method of m-plane gallium nitride epitaxial layer.
Background technology
Take the device, particularly light-emitting diode (LEDs) of gallium nitride as base, source benefit and environmental protection had powerful motive force.Recently, light-emitting diode is to be manufactured on the gallium nitride epitaxial layer, particularly on the c-plane sapphire substrate.On economic market, since the obtaining property of low-cost and large-scale wafer supply and c-plane sapphire substrate, the potential that the light-emitting diode take gallium nitride as base has volume production.
Because limited quantum Stark effect (quantum-confined stark effect, QCSE), main polarity c-plane gallium nitride epitaxial layer can be subject to the internal electrical place impact of polarization.The minimizing that so, will cause the wave function in quantum well (quantum well) interior electronics and electric hole to separate and cause luminous efficiency.
On the other hand, take nonpolar gallium nitride as the base light-emitting diode be proved its be better than via the manufacturing of limited quantum Stark effect take the c-plane gallium nitride as the base light-emitting diode.Nonpolar gallium nitride epitaxial layer can be grown up at m-plane carborundum, a-plane carborundum, γ lithium metaaluminate and m-plane sapphire.The relation that the thought lattice does not mate (lattice mismatch) and thermal coefficient of expansion, nonpolar gallium nitride is measured via X-ray swing curve (X-ray rocking curve, XRC), and its crystalline quality often surpasses 500 rads (arcsec).
For improving the problems referred to above, nonpolar gallium nitride is formed on a-plane sapphire or the r-plane sapphire, and proved its X-ray swing curve (X-ray rocking curve, XRC) half-peak double amplitude (full width at half maximum, FWHM) is about 400 rads.Yet r.m.s. (root-mean square, rms) surface roughness will be greater than 1 nanometer.According to manufacturing demand now, the r.m.s. surface roughness must be less than ± 0.5 nanometer.
In view of this, the invention provides a kind of semiconductor structure and manufacture method, to address the above problem.
Summary of the invention
A purpose of the present invention is to provide a kind of semiconductor structure.Semiconductor structure includes a c-plane sapphire substrate, a nanostructure and a m-plane (10-10) gallium nitride epitaxial layer.Nanostructure is formed on the c-plane sapphire substrate, and m-plane (10-10) gallium nitride epitaxial layer is formed on the nanostructure of c-plane sapphire substrate.
Wherein, nanostructure is for covering the surface of c-plane sapphire substrate fully.In addition, nanostructure is one to have the laciniation on n-plane (11-23) surface.The spacing of laciniation is between 50 nanometer to 350 nanometers.
In addition, the c-plane sapphire substrate has a crystal plane (crystal surface), and crystal plane has one between the inclination angle of-5 degree to+5 degree with respect to the c-axis direction.M-plane (10-10) gallium nitride epitaxial layer utilizes a low pressure metal organic chemical vapor deposition processing procedure (metal-organic chemical vapor deposition, MOCVD), on the nanostructure that is formed on the c-plane sapphire substrate.
Another object of the present invention is to provide a kind of manufacture method of semiconductor structure.The manufacture method of semiconductor structure includes the following step: (S1) prepare a c-plane sapphire substrate; (S2) form a nanostructure at the c-plane sapphire substrate; (S3) nanostructure at the c-plane sapphire substrate forms a m-plane (10-10) gallium nitride epitaxial layer.
Wherein, nanostructure is for covering the surface of c-plane sapphire substrate fully.In addition, nanostructure is one to have the laciniation on n-plane (11-23) surface.The spacing of laciniation is between 50 nanometer to 350 nanometers.
In addition, the c-plane sapphire substrate has a crystal plane, and crystal plane has one between the inclination angle of-5 degree to+5 degree with respect to the c-axis direction.M-plane (10-10) gallium nitride epitaxial layer utilizes a low pressure metal organic chemical vapor deposition processing procedure, on the nanostructure that is formed on the c-plane sapphire substrate.
Compared to prior art, its X-ray swing curve of semiconductor structure provided by the present invention and manufacture method (X-ray rocking curve, XRC) half-peak double amplitude (full width at half maximum, FWHM) is 316 rads (arcsec).In addition, the r.m.s. of semiconductor structure provided by the present invention and manufacture method (root-mean square, rms) surface roughness is 0.3 nanometer, also is satisfied with that the r.m.s. surface roughness must be less than the manufacturing demand of ± 0.5 nanometer now.
Can be further understood by following detailed Description Of The Invention and institute's accompanying drawing about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the profile that illustrates according to the semiconductor structure of a specific embodiment of the present invention.
Fig. 2 A is the profile that illustrates according to the nanostructure of the semiconductor structure of a specific embodiment of the present invention.
Fig. 2 B is the stereogram that illustrates according to the nanostructure of the semiconductor structure of a specific embodiment of the present invention.
Fig. 3 A is the schematic diagram that illustrates on the nanostructure that m-plane gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate.
Fig. 3 B is the schematic diagram that illustrates on the nanostructure that m-plane gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate.
Fig. 3 C is the schematic diagram that illustrates on the nanostructure that m-plane gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate.
Fig. 4 A is the X-ray diffraction result who illustrates according to the gallium nitride epitaxial layer of the semiconductor structure of a specific embodiment of the present invention.
Fig. 4 B is the X-ray swing curve that illustrates according to the gallium nitride epitaxial layer of the semiconductor structure of a specific embodiment of the present invention.
Fig. 5 A illustrates the comparison diagram that is formed on the photoluminescence on the c-plane sapphire substrate on the nanostructure that m-plain gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate with c-plain gallium nitride epitaxial layer.
Fig. 5 B illustrates the comparison diagram that is formed on the time resolution photoluminescence on the c-plane sapphire substrate on the nanostructure that m-plain gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate with c-plain gallium nitride epitaxial layer.
Fig. 6 is the flow chart that illustrates according to the manufacture method of the semiconductor structure of a specific embodiment of the present invention.
[primary clustering symbol description]
1: semiconductor structure 10:c-plane sapphire substrate
11: nanostructure 12:m-plain gallium nitride epitaxial layer
S1～S3: steps flow chart
Embodiment
Predeclared is that in this description, "-" symbol before the numeral is equal to "-" and is positioned on this numeral.For instance, in the specification, (10-10) interior " 1 " namely is equal to " i ".Also that is to say, (10-10) namely be equal to (1010).
See also Fig. 1, Fig. 1 is the profile that illustrates according to the semiconductor structure of a specific embodiment of the present invention.As shown in the figure, the invention provides a kind of semiconductor structure 1, include a c-plane sapphire substrate 10, a nanostructure 11 and a m-plane (10-10) gallium nitride epitaxial layer 12.Nanostructure 11 is formed on the c-plane sapphire substrate 10.M-plane (10-10) gallium nitride epitaxial layer 12 is formed on the nanostructure 11 of c-plane sapphire substrate 10.
C-plane sapphire substrate 10 has a crystal plane (crystal surface), and crystal plane has one between the inclination angle of-5 degree to+5 degree with respect to the c-axis direction.In addition, in practice, big or small about 2 o'clock of c-plane sapphire substrate.
See also Fig. 2 A and Fig. 2 B.Fig. 2 A is the profile that illustrates according to the nanostructure of the semiconductor structure of a specific embodiment of the present invention.Fig. 2 B is the stereogram that illustrates according to the nanostructure of the semiconductor structure of a specific embodiment of the present invention.As shown in the figure, nanostructure 11 is formed on the c-plane sapphire substrate 10.Wherein, nanostructure 11 is for covering the surface of c-plane sapphire substrate 10 fully.In addition, nanostructure 11 is one to have the laciniation on n-plane (11-23) surface, and the spacing of laciniation is between 50 nanometer to 350 nanometers.
In practice, c-plane sapphire substrate 10 is for utilizing an induction coupled plasma reactive ion etch method (inductively coupied plasma-reactive ion etching, ICP-RIE), nanostructure 11 is formed on the c-plane sapphire substrate 10.In addition, c-plane sapphire substrate 10 utilizes induction coupled plasma reactive ion etch method to form nanostructure 11, and about 20 minutes consuming time of its process palpus is until nanostructure 11 must cover the surface of c-plane sapphire substrate 10 fully.
See also Fig. 3 A, Fig. 3 B and Fig. 3 C.Fig. 3 A, Fig. 3 B and Fig. 3 C are the schematic diagram that illustrates on the nanostructure that m-plane gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate.As shown in the figure, m-plane (10-10) gallium nitride epitaxial layer 12 is formed on the nanostructure 11 of c-plane sapphire substrate 10.M-plane (10-10) gallium nitride epitaxial layer 12 utilizes a low pressure metal organic chemical vapor deposition processing procedure (metal-organic chemical vapor deposition in practice, MOCVD), with on the nanostructure 11 that is formed on c-plane sapphire substrate 10.
In addition, m-plane (10-10) gallium nitride epitaxial layer 12 was shaped via the two-stage.In the time of 530 ℃ and 1050 ℃ the time, by low pressure metal organic chemical vapor deposition processing procedure, can form the thick gallium nitride crystalline nucleation layer (nucleation layer, NL) of 30nm and the thick undoped gallium nitride resilient coating of 2.5 μ m.At last, m-plane (10-10) gallium nitride epitaxial layer 12 can be formed on the nanostructure 11 of c-plane sapphire substrate 10 accordingly.At last, scan gallium nitride epitaxial layer 125 * 5 μ m with atomic force microscope (atomic force microscopy, AFM)
2The surface, the r.m.s. surface roughness of gallium nitride epitaxial layer 12 (rms surface roughness) is 0.3nm.
See also Fig. 4 A and Fig. 4 B.Fig. 4 A is the X-ray diffraction result who illustrates according to the gallium nitride epitaxial layer of the semiconductor structure of a specific embodiment of the present invention.Fig. 4 B is the X-ray swing curve that illustrates according to the gallium nitride epitaxial layer of the semiconductor structure of a specific embodiment of the present invention.Shown in Fig. 4 A, 2.5 the gallium nitride epitaxial layer 12 of μ m is via X-ray diffraction (X-ray diffraction, XRD), its peak value is located in 32.3 °, 41.7 °, 67.7 °, corresponds respectively to gallium nitride (10-10) plane, sapphire (0006) plane and gallium nitride (20-20) plane.In addition, shown in Fig. 4 B, the half-peak double amplitude of the X-ray swing curve at the vertical incidence angle on gallium nitride (10-10) plane (X-ray rocking curve, XRC) (full width at half maximum, FWHM) is 316 rads.
See also Fig. 5 A and Fig. 5 B.Fig. 5 A illustrates the comparison diagram that is formed on the photoluminescence on the c-plane sapphire substrate on the nanostructure that m-plain gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate with c-plain gallium nitride epitaxial layer.Fig. 5 B illustrates the comparison diagram that is formed on the time resolution photoluminescence on the c-plane sapphire substrate on the nanostructure that m-plain gallium nitride epitaxial layer according to the semiconductor structure of a specific embodiment of the present invention is formed on the c-plane sapphire substrate with c-plain gallium nitride epitaxial layer.In practice, this implementation environment is measured with a 266nm femtosecond pulse ripple at room temperature.Wherein, pulse-wave strength is three times an of ti sapphire laser.
Please again referring to Fig. 5 A, curve A is m-plain gallium nitride epitaxial layer during corresponding to different wave length, the intensity level of photoluminescence.Curve B is c-plain gallium nitride epitaxial layer during corresponding to different wave length, the intensity level of photoluminescence.As shown in the figure, the intensity peak of m-plain gallium nitride epitaxial layer photoluminescence is 1.7 times of c-plain gallium nitride epitaxial layer photoluminescence.In addition, the intensity level of indivedual accumulative total two curves in wave-length coverage 350～390nm, the efficient of curve A photoluminescence is 2.5 times of curve B.
Please again referring to Fig. 5 B, curve A be m-plain gallium nitride epitaxial layer corresponding to different time, photon excitation light intensity logarithm value.Curve B be c-plain gallium nitride epitaxial layer corresponding to different time, photon excitation light intensity logarithm value.Curve C is instrument response.As shown in the figure, the life cycle of the photoluminescence of curve A is greater than curve B.Therefore the m-plain gallium nitride epitaxial layer quality that is formed on the nanostructure of c-plane sapphire substrate is very good.
See also Fig. 6, Fig. 6 is the flow chart that illustrates according to the manufacture method of the semiconductor structure of a specific embodiment of the present invention.As shown in the figure, the manufacture method of semiconductor structure includes the following step: (S1) prepare a c-plane sapphire substrate; (S2) form a nanostructure at the c-plane sapphire substrate; (S3) nanostructure at the c-plane sapphire substrate forms a m-plane (10-10) gallium nitride epitaxial layer.
At first, in step (S1), prepare a c-plane sapphire substrate.Big or small about 2 o'clock of c-plane sapphire substrate.Wherein, the c-plane sapphire substrate has a crystal plane, and crystal plane has one between the inclination angle of-5 degree to+5 degree in the c-axis direction relatively.
Then, in step (S2), form a nanostructure at the c-plane sapphire substrate.Nanostructure is one to have the laciniation on n-plane (11-23) surface.Wherein, the spacing of laciniation is between 50 nanometer to 350 nanometers.In practice, the c-plane sapphire substrate utilizes an induction coupled plasma reactive ion etch method, and nanostructure is formed on the c-plane sapphire substrate.In addition, c-plane sapphire substrate utilization induction coupled plasma reactive ion etch method is to form nanostructure, and about 20 minutes consuming time of its process palpus is until nanostructure must cover the surface of c-plane sapphire substrate fully.
Then, in step (S3), at nanostructure formation one m-plane (10-10) of c-plane sapphire substrate gallium nitride epitaxial layer.M-plane (10-10) gallium nitride epitaxial layer is for utilizing a low pressure metal organic chemical vapor deposition processing procedure, on the nanostructure that is formed on the c-plane sapphire substrate.
The c-plane sapphire substrate of mentioning in the manufacture method about semiconductor structure, nanostructure, m-plane (10-10) gallium nitride epitaxial layer with and detailed content all similar in appearance to c-plane sapphire substrate 10, nanostructure 11, m-plane (10-10) the gallium nitride epitaxial layer 12 of aforesaid semiconductor structure, so do not given unnecessary details at this.
Compared to prior art, nonpolar gallium nitride is formed on a-plane sapphire or the r-plane sapphire, the half-peak double amplitude of its X-ray swing curve is about 400 rads.Its r.m.s. surface roughness will be greater than 1 nanometer.According to manufacturing demand now, the r.m.s. surface roughness must be less than ± 0.5 nanometer.The half-peak double amplitude of its X-ray swing curve of semiconductor structure provided by the present invention and manufacture method is 316 rads.In addition, its r.m.s. surface roughness is 0.3 nanometer, and the r.m.s. surface roughness of also being satisfied with now must be less than the manufacturing demand of ± 0.5 nanometer.
By the above detailed description of preferred embodiments, for hope can be known description feature of the present invention and spirit more, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention wish application.
Claims (12)
1. a semiconductor structure is characterized in that, includes:
One c-plane sapphire substrate;
One nanostructure is formed on this c-plane sapphire substrate; And
One m-plane (10-10) gallium nitride epitaxial layer is formed on this nanostructure of this c-plane sapphire substrate.
2. semiconductor structure as claimed in claim 1, wherein this nanostructure is for covering the surface of this c-plane sapphire substrate fully.
3. semiconductor structure as claimed in claim 2, wherein this nanostructure is one to have the laciniation on n-plane (11-23) surface.
4. semiconductor structure as claimed in claim 3, wherein the spacing of this laciniation is between 50 nanometer to 350 nanometers.
5. semiconductor structure as claimed in claim 1, wherein this m-plane (10-10) gallium nitride epitaxial layer utilizes a low pressure metal organic chemical vapor deposition processing procedure (MOCVD) with on this nanostructure that is formed on this c-plane sapphire substrate.
6. semiconductor structure as claimed in claim 1, wherein this c-plane sapphire substrate has a crystal plane (Crystal Surface), and this crystal plane has one between the inclinations angle of-5 degree to+5 degree with respect to the c-axis direction.
7. semiconductor structure manufacture method is characterized in that it includes following steps:
(S1) prepare a c-plane sapphire substrate;
(S2) form a nanostructure at this c-plane sapphire substrate; And
(S3) this nanostructure at this c-plane sapphire substrate forms a m-plane (10-10) gallium nitride epitaxial layer.
8. semiconductor structure manufacture method as claimed in claim 7, wherein this nanostructure is for covering the surface of this c-plane sapphire substrate fully.
9. semiconductor structure manufacture method as claimed in claim 8, wherein this nanostructure is one to have the laciniation on n-plane (11-23) surface.
10. semiconductor structure manufacture method as claimed in claim 9, wherein the spacing of this laciniation is between 50 nanometer to 350 nanometers.
11. semiconductor structure manufacture method as claimed in claim 7, wherein this m-plane (10-10) gallium nitride epitaxial layer utilizes a low pressure metal organic chemical vapor deposition processing procedure (MOCVD) with on this nanostructure that is formed on this c-plane sapphire substrate.
12. semiconductor structure manufacture method as claimed in claim 7, wherein this c-plane sapphire substrate has a crystal plane (Crystal Surface), and this crystal plane has one between the inclination angle of-5 degree to+5 degree with respect to the c-axis direction.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005064643A1 (en) * | 2003-04-15 | 2005-07-14 | The Regents Of The University Of California | NON-POLAR (A1,B,In,Ga)N QUANTUM WELLS |
| CN101373714A (en) * | 2007-08-22 | 2009-02-25 | 中国科学院半导体研究所 | Method for preparing nano-scale pattern substrate for nitride epitaxial growth |
| WO2009090904A1 (en) * | 2008-01-16 | 2009-07-23 | Sumitomo Electric Industries, Ltd. | Method for growing group iii nitride crystal |
| CN101728248A (en) * | 2008-10-15 | 2010-06-09 | 中国科学院半导体研究所 | Growing method of gallium nitride |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005064643A1 (en) * | 2003-04-15 | 2005-07-14 | The Regents Of The University Of California | NON-POLAR (A1,B,In,Ga)N QUANTUM WELLS |
| CN101373714A (en) * | 2007-08-22 | 2009-02-25 | 中国科学院半导体研究所 | Method for preparing nano-scale pattern substrate for nitride epitaxial growth |
| WO2009090904A1 (en) * | 2008-01-16 | 2009-07-23 | Sumitomo Electric Industries, Ltd. | Method for growing group iii nitride crystal |
| CN101728248A (en) * | 2008-10-15 | 2010-06-09 | 中国科学院半导体研究所 | Growing method of gallium nitride |
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Application publication date: 20130213 |