CN102931163A - Semiconductor device having an inductor - Google Patents

Semiconductor device having an inductor Download PDF

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Publication number
CN102931163A
CN102931163A CN2012104075370A CN201210407537A CN102931163A CN 102931163 A CN102931163 A CN 102931163A CN 2012104075370 A CN2012104075370 A CN 2012104075370A CN 201210407537 A CN201210407537 A CN 201210407537A CN 102931163 A CN102931163 A CN 102931163A
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China
Prior art keywords
interconnection
zone
inductor
pad
semiconductor device
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CN2012104075370A
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Chinese (zh)
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CN102931163B (en
Inventor
中柴康隆
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority claimed from CNA2007101278067A external-priority patent/CN101101912A/en
Publication of CN102931163A publication Critical patent/CN102931163A/en
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Publication of CN102931163B publication Critical patent/CN102931163B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Abstract

A semiconductor device 1 is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, a wiring layer, the inductor 16, and a conductive pad 18 (a first pad). The wiring layer is provided on the semiconductor substrate. The wiring layer includes the inductor 16. The pad 18 is provided on the wiring layer. The pad 18 is inside a circuit formation region D1 of the semiconductor chip and is provided in a region that is not overlapped with the inductor 16.

Description

Semiconductor device with inductor
The application be that July 3, application number in 2007 are 2007101278067 the applying date, application artificial " Renesas Electronics Corporation ", denomination of invention divide an application for the application for a patent for invention of " semiconductor device with inductor ".
The application is based on Japanese patent application No.2006-183569,2007-011995 and 2007-159764, its in full content be incorporated herein as a reference.
Technical field
The present invention relates to a kind of semiconductor device with inductor.
Prior art
In some cases, inductor is arranged in the MMIC(monolithic integrated microwave circuit) etc. traditional match circuit (for example Japanese unexamined patent publication No. communique No.2002-289782).In addition, in recent years, utilize the voltage-controlled oscillator of the resonance phenomena of LC accumulator in parallel sometimes to be used as the PLL(phase-locked loop) local oscillator of circuit.Naturally, inductor (is for example offered this voltage-controlled oscillator, the people's such as Ali Hajimiri " Design Issue in CMOS Differential LC Oscillators ", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.34, No.5, in May, 1999,717-724 page or leaf).
Fig. 7 has schematically shown the plane graph of the disclosed MMIC of Japanese unexamined patent publication No. communique No.2002-289782.The inductor 101 that forms match circuit is formed among the MMIC.In addition, formed the pad 102 that is connected with the projection that is used for upside-down mounting installation MMIC on substrate.The circuit that pad 102 is placed on this MMIC forms the outside of regional D2.
The inventor has approved following aspect.The circuit scale of MMIC among Fig. 7 is little, and therefore, pad 102 can be placed on the outside that circuit forms regional D2.But when circuit scale became large, for example ISL formed the regional D2 outside in the situation that pad is arranged on circuit, and the quantity of pad 102 increases, thereby chip size increases.
Therefore, as shown in Figure 8, consider in circuit forms regional D2, to arrange pad 102.Thereby, the pad 102 of larger amt can be provided, and not increase the size of chip.
But in Fig. 8, the pad 102 of the magnetic field of inductor 101 on be positioned at inductor (dash area) produced eddy current.Then, offset above-mentioned magnetic field of following Lenz's law to such an extent as to this eddy current has produced polarizing magnetic field, therefore, reduced the intensity in this magnetic field.The reduction of magnetic field intensity causes the reduction of Q value.
Summary of the invention
According to the present invention, a kind of semiconductor device is provided, comprise semiconductor chip, it has Semiconductor substrate; Interconnection layer, it comprises the inductor that is positioned on the described Semiconductor substrate; And first conductive welding disk, it is positioned on the described interconnection layer; Wherein circuit form the zone be positioned at described the first pad under, and the first pad is arranged in from not overlapping with the described inductor zone of plane angle.
In this semiconductor device, circuit form the zone be positioned at pad under.Therefore, can provide the pad of q.s, and can not increase the size of chip.In addition, pad is set to avoid the part above the inductor.Therefore, can avoid the magnetic field of inductor in pad, to produce eddy current.
According to the present invention, can realize a kind of semiconductor device, it can avoid producing eddy current in pad, avoid simultaneously the increase of chip size.
Description of drawings
Above and other objects of the present invention, advantage and feature will be more apparent from the following description of by reference to the accompanying drawings some embodiment, wherein
Fig. 1 shows the plane graph according to the semiconductor device of first embodiment of the invention;
Fig. 2 shows along the sectional view of the line II-II of the semiconductor device among Fig. 1;
Fig. 3 A and 3B show the sectional view according to the semiconductor device of second embodiment of the invention;
Fig. 4 A and 4B show the first plane graph to the four-range definition;
Fig. 5 shows the 5th and arrives the plane graph of the definition in Section Eight territory;
Fig. 6 A and 6B show the plane graph of the distortion of these embodiment;
Fig. 7 shows the plane graph according to the example of the semiconductor device of conventional art;
Fig. 8 shows the plane graph according to another example of the semiconductor device of conventional art;
Fig. 9 A and 9B show the sectional view according to the semiconductor device of third embodiment of the invention;
Figure 10 A and 10B show the sectional view according to the semiconductor device of third embodiment of the invention.
Embodiment
At this, with reference to illustrative examples the present invention is described.Those skilled in the art will approve, use instruction of the present invention can realize multiple interchangeable embodiment, and the invention is not restricted to illustrational these embodiment for task of explanation.
Below, be described in detail with reference to the attached drawings the preferred embodiment according to semiconductor device of the present invention.Here, identical element in the identical Reference numeral respective figure, and no longer repeat description to similar elements.
The first embodiment
Fig. 1 shows the plane graph according to the semiconductor device of first embodiment of the invention.Fig. 2 is the sectional view along the line II-II of the semiconductor device among Fig. 1.Semiconductor device 1 has semiconductor chip 10.Semiconductor chip 10 has Semiconductor substrate 12, interconnection layer 14, inductor 16 and conductive welding disk 18(the first pad).For example, Semiconductor substrate 12 is silicon substrates.
Interconnection layer 14 is positioned on the Semiconductor substrate 12.Interconnection layer 14 comprises inductor 16 and interconnection 29.In interconnection layer 14, inductor 16 is formed by the interconnection of coil shape.
Pad 18 is positioned on the interconnection layer 14.The circuit that pad 18 is arranged in semiconductor chip 10 forms regional D1.Also namely, circuit forms the below that the zone is located immediately at pad 18.It is the zone that wherein forms circuit element and interconnection that circuit forms the zone.Here alleged circuit element comprises active element, for example transistor, and passive component, and for example resistor, capacitor and inductor, and do not comprise interconnection.In Fig. 2, for example, the MOS transistor 22 that is comprised of gate electrode 26, grid insulating film 28 and source/drain regions 24 and interconnecting 29 directly is formed under the pad 18.Here, circuit form the zone can be wherein form circuit element and the interconnection at least zone of one of them.Pad 18 is arranged in along the inductor 16 nonoverlapping zones of plane with semiconductor chip 10.That is to say do not have pad 18 at inductor 16.
As Fig. 1 sees, pad 18 with inductor 16 nonoverlapping zones in arrange regularly (with the square pattern according to the present embodiment).The layout of the pad 18 among Fig. 1 is corresponding to by removing nine following configurations that pad 102 is realized, and these nine pads are included in five pads and near four pads 102 these pads of picture shade among above-mentioned Fig. 8.
Projection 20 is positioned on the pad 18 of semiconductor chip 10.The same with pad 18, projection 20 also is arranged in from plane angle and inductor 16 nonoverlapping zones.For example, projection 20 is solder projection or golden projection.Projection 20 is as the outer electrode end of semiconductor device 1.When semiconductor device 1 was installed on the substrate of interconnect substrate for example, semiconductor device 1 and this substrate were connected to each other by these projections 20.Here, from plane angle projection 20 is not shown at Fig. 1.
The effect of the present embodiment is described below.In semiconductor device 1, circuit forms the below that the zone is located immediately at pad 18.As a result, the pad 18 of sufficient amount can be provided, and not increase chip size.In addition, pad 18 is placed on the position of avoiding the part on the inductor 16.As a result, can avoid the magnetic field of inductor 16 in pad 18, to produce eddy current.Therefore, can realize a kind ofly can avoiding in pad 18, producing eddy current, and preventing simultaneously the semiconductor device 1 that chip size increases.
And projection 20 also is arranged in from plane angle and inductor 16 nonoverlapping zones.Therefore, also can avoid the magnetic field of inductor 16 in projection 20, to produce eddy current.The same with the situation that in pad 18, produces eddy current, if in projection 20, produced eddy current, then can reduce the magnetic field intensity in the inductor.
From the regional different zone overlapping from plane angle and inductor 16, with square pattern arrangement pad 18.Therefore, can provide a large amount of pads 18.Here, pad 18 can be arranged with diagonal comb mesh pattern rather than square pattern.
Inductor 16 is formed by the interconnection of the coil shape in the interconnection layer 14.Therefore, be easy in semiconductor chip 10, provide inductor 16.
According to the present embodiment, all pads 18 are arranged in circuit and form regional D1, and are therefore, can the holding core chip size especially little.
The second embodiment
Fig. 3 A shows the sectional view according to the semiconductor device of second embodiment of the invention.Semiconductor device 2 has semiconductor chip 10 and mounting substrates 30.Identical with described in the first embodiment of the structure of semiconductor chip 10.Mounting substrates 30 has conductive welding disk 30(the second pad that is located thereon the surface).By projection 20 being connected to pad 32 and semiconductor chip 10 upside-down mountings being installed on the mounting substrates 30.For example, mounting substrates 30 is printing interconnect substrate or silicon substrate.In addition, mounting substrates 30 can be the semiconductor chip different from semiconductor chip 10.
The same with projection 20 with pad 18, pad 32 also is arranged in from the inductor 16 nonoverlapping zones of plane angle with semiconductor chip 10.And the interconnection 34 that is arranged in mounting substrates 30 also is positioned at from the inductor 16 nonoverlapping zones of plane angle with semiconductor chip 10.Interconnection 34 is electrically connected to pad 32.
According to the present embodiment, pad 32 and interconnection 34 are arranged in from plane angle and inductor 16 nonoverlapping zones.Therefore, can avoid the magnetic field of inductor 16 in pad 32 and interconnection 34, to produce eddy current.The same with the situation that in pad 18, produces eddy current, if at pad 32 or interconnect and produce eddy current in 34, then can reduce the magnetic field intensity in the inductor.Other effect of the present embodiment is identical with the first embodiment.
Here, according to the present embodiment.Only pad 32 or interconnect 34 can be placed on the position of avoiding the part below the inductor 16.Fig. 3 B shows the example that pad 32 only is placed on the locational situation of avoiding the part below the inductor 16.And, in this case, to compare with the situation below interconnection 34 all is positioned at inductor 16 with pad 32, meeting is so that magnetic field intensity reduces lessly.
The 3rd embodiment
Fig. 9 A shows the sectional view according to the semiconductor device of third embodiment of the invention.Semiconductor device 3 has semiconductor chip 10 and mounting substrates 30.The structure of semiconductor chip 10 have with the first embodiment in describe identical.Interconnection 34 in mounting substrates 30 has the interconnection by interconnection 34a(first), interconnection 34b(the second interconnection), interconnection 34c(the 3rd interconnection) and interconnection 34d(the 4th interconnect) multilayer interconnect structure that forms.Interconnection 34a is the interconnection in the top layer and is arranged in the layer identical with pad 32.Interconnection 34b is located on the layer of interconnection below the 34a.Equally, interconnection 34c and interconnection 34d lay respectively at interconnection 34b and interconnection on the layer below the 34c.
In semiconductor device 3, the part of interconnection 34a, 34b, 34c and 34d can be arranged in from plane angle and inductor 16 nonoverlapping zones.Do like this, can be so that the eddy current that produces in interconnection 34 owing to the magnetic field of inductor 16 be less.In addition, in order effectively to realize this effect, preferably close to the interconnection of inductor 16 as the interconnection that is not positioned under the inductor 16.
Therefore, any among will interconnect 34a, 34b, 34c and 34d is elected to be in the situation that is not positioned at the interconnection under the inductor 16, preferably the interconnection 34a shown in Fig. 9 B.Be elected to be in the another kind of situation of the interconnection that is not positioned under the inductor 16 among will interconnect 34a, 34b, 34c and the 34d any two, preferably discretionary interconnections 34a and the 34b shown in Figure 10 A.Wantonly three among will interconnect 34a, 34b, 34c and 34d are elected to be in the another kind of situation that is not positioned at the interconnection below the inductor 16, preferably interconnection 34a, 34b and the 34c shown in Figure 10 B.
Semiconductor device according to the present invention is not limited to the semiconductor device according to above-described embodiment, and different alter mode also is fine.For example, except example shown in Figure 1, as long as pad 18 is positioned at circuit and forms on regional D1 and the inductor 16 nonoverlapping zones, just different configurations can be used for pad 18.
Here, in order to guarantee enough pad sources, pad 18 is preferably placed in many lines at least any one zone in the defined first, second, third and the 4th zone below.In order to define these zones, shown in Fig. 4 A and 4B, among four sides of semiconductor device 10, a pair of side of facing is called as the first side S1 and the second side S2, and another is called as the 3rd side S3 and the 4th side S4 to the side of facing.At this moment, more be respectively first area R1, second area R2, the 3rd regional R3 and the 4th regional R4 near the zone of the first side S1, the second side S2, the 3rd side S3 and the 4th side S4 than inductor 16.Although for convenient, Fig. 4 A shows regional R1 and R2, Fig. 4 B shows regional R3 and R4, and these Fig. 4 A show identical semiconductor chip 10 with 4B.
And, as shown in Figure 5, by with the zone of inductor 16 along perpendicular to the above-below direction among the S1(figure of side) direction extend to the zone that side S1 and side S2 obtain and be respectively defined as the 5th regional R5 and the 6th regional R6, and by with the edge, zone of inductor 16 perpendicular to the left and right directions among the S3(figure of side) direction extend to the zone that side S3 and side S4 obtain and be respectively defined as SECTOR-SEVEN territory R7 and Section Eight territory R8.Here, any among regional R5, R9, R7 and the R8 do not comprise the zone that comprises at first inductor 16.
For in defined regional R5, R6, R7 and R8 by this mode, guarantee enough pad sources, pad 18 be preferably placed at regional R5 and R6 one of them in, and pad 18 be preferably placed at regional R7 and R8 one of them in.
Below, come more above-mentioned Fig. 1 and 7 with the regional R1 that introduces to the concept of R8 here.Fig. 1 satisfies the condition of " pad is arranged in regional R1 to one of them many individual line of R4 ".This is because pad 18 is arranged in two zones: the many lines of regional R2 and R4.Simultaneously, in Fig. 7, pad 102 is not arranged in regional R1 to any many lines of R4, therefore, does not satisfy this condition.
In addition, in Fig. 1, satisfy condition " pad is arranged in one of them of regional R5 and R6, and simultaneously pad must be arranged in one of them of regional R7 and R8 ".This is because pad 18 is arranged in four zones: regional R5, R6, R7 and R8.Simultaneously, in Fig. 7, pad 102 is not arranged in regional R7 or R8, therefore, does not satisfy this condition.
Here, in Fig. 1 and Fig. 7, be respectively defined as regional R1, R2, R3 and R4 in the zone on upside, downside, left side and the right side of inductor 16, as Fig. 4 A and 4B.
In addition, Fig. 1 show pad 18 except along in the plane with the overlapping zone of inductor 16 almost whole circuit form the example that regional D1 arranges.But, shown in Fig. 6 A and 6B, can there be following part (dash area), in this part, do not have pad 18 to be arranged in inductor 16 nonoverlapping circuit and form in the zone in the regional D1.The configuration of the pad 18 of Fig. 6 A namely, is positioned at four configurations that pad 18 obtains at center corresponding to following configuration by removal from the configuration that is obtained by four pads 18 of removal among Fig. 1.In addition, in Fig. 6 B the configuration of pad 18 corresponding to following configuration, that is, and by from the configuration of Fig. 1, removing along 11 configurations that pad 18 obtains of the periphery configure of four pads 18 that are positioned at the center.
In addition, all be positioned at the example that circuit forms regional D1 inside although show all pads 18 according to above-described embodiment, some part 18 can be positioned at the outside that circuit forms regional D1.
Can understand, the invention is not restricted to above-described embodiment, but in the situation that do not depart from the scope of the present invention with spirit and can modify and change.

Claims (13)

1. semiconductor device, it comprises:
Semiconductor chip, this semiconductor chip have Semiconductor substrate, interconnection layer and the first conductive welding disk, and described interconnection layer comprises the inductor that is positioned on the described Semiconductor substrate, and described the first conductive welding disk is arranged on the described interconnection layer,
Projection, described projection are positioned on described the first pad, and
Mounting substrates, described mounting substrates have the second pad of conduction and are positioned at the first following interconnection of described the second pad,
Wherein, be provided with circuit and form the zone under described the first pad, described circuit forms the zone and has circuit element and interconnection, and described the first pad is arranged on from plane angle and the nonoverlapping zone of described inductor,
Wherein, described inductor is arranged in the ground floor, this ground floor be arranged at described the first conductive welding disk below,
Wherein, described projection is arranged on from plane angle and the nonoverlapping zone of described inductor,
Wherein, by described projection being connected to described the second pad, described semiconductor chip is installed on the described mounting substrates,
Wherein, described the second pad is arranged in from the described inductor nonoverlapping zone of plane angle with described semiconductor chip, and
Wherein, from plane angle, described the first interconnection is overlapping with described inductor.
2. semiconductor device as claimed in claim 1, wherein,
Described the first pad be arranged in first, second, third and four-range one of them the zone many lines,
Wherein, be respectively defined as described first, second, third and four zone than described inductor closer to the zone of the first, second, third and the 4th side of described semiconductor chip from plane angle.
3. semiconductor device as claimed in claim 1, wherein,
Described the first pad be arranged in the 5th and the 6th zone one of them, and be arranged in the 7th and the Section Eight territory one of them,
Wherein, a pair of side of facing in the first, second, third and the 4th side of described semiconductor chip is defined as the first side and the second side, and another is defined as the 3rd side and the 4th side to the surface of facing, and
Be respectively defined as the 5th zone and the 6th zone by the zone of described inductor is extended to the zone that described the first and second sides obtain along the direction perpendicular to described the first side, and be respectively defined as SECTOR-SEVEN territory and Section Eight territory by the edge, zone of described inductor is extended to the zone that described the third and fourth side obtains perpendicular to the direction of described the 3rd side.
4. semiconductor device as claimed in claim 1, wherein,
Except with the overlapping zone of described inductor, described the first pad is to arrange regularly from plane angle.
5. semiconductor device as claimed in claim 4, wherein,
From plane angle, described the first pad all with square pattern arrangement except with the overlapping zone of described inductor the zone in.
6. semiconductor device as claimed in claim 1, wherein,
Described mounting substrates has the second interconnection, and this second interconnection is arranged in the layer identical with described the second pad, and
Described the second interconnection is arranged in from the described inductor nonoverlapping zone of plane angle with described semiconductor chip.
7. semiconductor device as claimed in claim 6, wherein,
Described mounting substrates has the 3rd interconnection, and the 3rd interconnection is located at the one deck below described the second interconnection, and
Described the 3rd interconnection is arranged at from the nonoverlapping zone of described inductor of plane angle and described semiconductor chip.
8. semiconductor device as claimed in claim 7, wherein,
Described the 3rd interconnection is positioned on described the first interconnection.
9. semiconductor device as claimed in claim 7, wherein,
Described mounting substrates has the 4th interconnection, and the 4th interconnection is located at the one deck below described the 3rd interconnection, and
Described the 4th interconnection is arranged at from the nonoverlapping zone of described inductor of plane angle and described semiconductor chip.
10. semiconductor device as claimed in claim 9, wherein,
Described the 4th interconnection is positioned on described the first interconnection.
11. want 1 described semiconductor device such as right, wherein,
Described inductor is formed by the interconnection of the coil shape in the described interconnection layer.
12. semiconductor device as claimed in claim 1 also comprises the MOS transistor of the top that is arranged on described Semiconductor substrate,
Wherein, described circuit element comprises from the non-overlapping described MOS transistor of plane graph and described inductor.
13. semiconductor device as claimed in claim 12, wherein,
Described MOS transistor has gate electrode, gate insulating film and source/drain region.
CN201210407537.0A 2006-07-03 2007-07-03 There is the semiconductor device of inductor Active CN102931163B (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP2006-183569 2006-07-03
JP2006183569 2006-07-03
JP2007011995 2007-01-22
JP2007-011995 2007-01-22
JP2007159764A JP2008205422A (en) 2006-07-03 2007-06-18 Semiconductor device
JP2007-159764 2007-06-18
CNA2007101278067A CN101101912A (en) 2006-07-03 2007-07-03 Semiconductor device having an inductor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101278067A Division CN101101912A (en) 2006-07-03 2007-07-03 Semiconductor device having an inductor

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CN102931163A true CN102931163A (en) 2013-02-13
CN102931163B CN102931163B (en) 2016-05-18

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JP6318565B2 (en) * 2013-11-13 2018-05-09 セイコーエプソン株式会社 Semiconductor device and electronic equipment
US9245940B2 (en) * 2014-02-12 2016-01-26 Qualcomm Incorporated Inductor design on floating UBM balls for wafer level package (WLP)
WO2022163299A1 (en) * 2021-01-29 2022-08-04 株式会社村田製作所 Wiring board
WO2022163298A1 (en) * 2021-01-29 2022-08-04 株式会社村田製作所 Wiring board

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US6423576B1 (en) * 1997-10-14 2002-07-23 Amkor Technology, Inc. Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package
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