CN102916781A - Calibration method and calibration device - Google Patents

Abstract

The embodiment of the invention discloses a verification method and a verification device. The verification method includes: receiving parallel data, the number of bytes of the parallel data is X, the bit width of the parallel data is Y bytes, X is a positive integer, and Y is a positive integer; a cyclic redundancy check is adopted The CRC circuit operates on the parallel data to obtain a first CRC value; compares whether the first CRC value is the same as a second CRC value, and the second CRC value is a CRC value obtained by performing CRC on the first data, so The first data is data obtained by adding M bytes of data at the end of the second data, and the second data is obtained by adding a third CRC value at the end of the third data, and the third CRC value is The CRC value of the third data, M, is equal to the remainder of Y minus X divided by Y; if the first CRC value is the same as the second CRC value, it is determined that the parallel data passes the CRC. This technical solution requires only one CRC circuit. Compared with the prior art, this technical solution requires less hardware resources.

Description

Calibration method and calibration device

technical field

The invention relates to the technical field of data processing, in particular to a verification method and a verification device.

Background technique

CRC (Cyclic Redundancy Check) technology is widely used in the field of data communication. CRC can be implemented by software lookup table or hardware. Performing CRC on high-speed data is generally implemented by hardware.

In the prior art, when CRC is performed on parallel data with a bit width of multiple bytes by hardware, multiple CRC circuits are required. For example, to perform CRC on parallel data with a bit width of 4 bytes, a CRC circuit corresponding to 1 byte, a CRC circuit corresponding to 2 bytes, a CRC circuit corresponding to 3 bytes, and a CRC circuit corresponding to 4 bytes are required. Corresponding CRC circuit. In the prior art, performing CRC on parallel data with a bit width of multiple bytes requires many hardware resources.

Contents of the invention

Embodiments of the present invention provide a CRC checking method and device, which can reduce required hardware resources.

In order to solve the above technical problems, the embodiment of the present invention discloses the following technical solutions:

In the first aspect, a verification method is provided, including:

Receiving parallel data, the number of bytes of the parallel data is X, the bit width of the parallel data is Y bytes, X is a positive integer, and Y is a positive integer;

using a CRC circuit to operate on the parallel data to obtain a first CRC value;

Comparing whether the first CRC value is the same as the second CRC value, the second CRC value is a CRC value obtained by performing CRC on the first data, and the first data is to add M bytes at the end of the second data The data obtained from the data, the second data is the data obtained by adding the third CRC value at the end of the third data, the third CRC value is the CRC value of the third data, M is equal to Y minus X divided by Take the remainder of Y;

If the first CRC value is the same as the second CRC value, it is determined that the parallel data passes the CRC.

With reference to the first aspect, in a first possible implementation manner of the first aspect, using the CRC circuit to perform operations on the parallel data includes:

If the remainder of dividing X by Y is not equal to 0, add fourth data at the end of the parallel data, the length of the fourth data is M bytes, and obtain new parallel data;

The CRC circuit is used to perform operations on the new parallel data.

With reference to the first aspect, or the first possible implementation of the first aspect, in a second possible implementation of the first aspect, the parallel data Operations include:

If the remainder of dividing X by Y is equal to 0, no data is added to the end of the parallel data, and the CRC circuit is used to perform operations on the parallel data.

In combination with the first aspect, or the first possible implementation manner of the first aspect, or the second possible implementation manner provided in the first aspect, the third possibility provided in the first aspect In an implementation manner, before comparing whether the first CRC value is the same as the second CRC value, the method further includes:

respectively adding 1 to Y bytes of data at the end of the second data to obtain Y data;

performing CRC on the Y data respectively to obtain Y CRC values;

Determining a CRC value among the Y CRC values corresponding to data obtained by adding the M bytes of data at the end of the second data among the Y data as the second CRC value.

In a second aspect, a verification device is provided, including:

The receiving unit is used to receive parallel data, the number of bytes of the parallel data is X, the bit width of the parallel data is Y bytes, X is a positive integer, and Y is a positive integer;

a CRC circuit, configured to perform operations on the parallel data received by the receiving unit to obtain a first CRC value;

A comparison unit, configured to compare whether the first CRC value generated by the CRC circuit is the same as a second CRC value, the second CRC value is a CRC value obtained by performing CRC on the first data, and the first data is Data obtained by adding M bytes of data at the end of the second data, the second data being data obtained by adding a third CRC value at the end of the third data, the third CRC value being the third data CRC value, M is equal to the remainder of Y minus X divided by Y;

The first determination unit is configured to determine that the parallel data passes the CRC if the comparison result of the comparison unit is that the first CRC value is the same as the second CRC value.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the CRC circuit is specifically used for:

If the remainder of dividing X by Y is not equal to 0, add fourth data at the end of the parallel data, the length of the fourth data is M bytes, and obtain new parallel data;

Operations are performed on the new parallel data.

With reference to the second aspect, or the first possible implementation manner of the second aspect, in the second possible implementation manner of the second aspect, the CRC circuit is specifically used for:

If the remainder of dividing X by Y is equal to 0, no data is added to the end of the parallel data, and operations are performed on the parallel data.

In combination with the second aspect, or the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in the third possible implementation of the second aspect In the mode, the verification device also includes:

an adding unit, configured to add 1 to Y bytes of data at the end of the second data respectively to obtain Y data;

a computing unit, configured to perform CRC on the Y pieces of data generated by the adding unit, respectively, to obtain Y CRC values;

A second determination unit, configured to determine whether the Y CRC values obtained by the calculation unit are the same as those obtained by the adding unit before the comparison unit compares whether the first CRC value is the same as the second CRC value The CRC value corresponding to the data obtained by adding the M bytes of data at the end of the second data among the Y data is the second CRC value.

In a third aspect, a network device is provided, and the network device includes the second aspect, or the first possible implementation of the second aspect, or the second possible implementation of the second aspect , or the verification device provided in a third possible implementation manner of the second aspect.

In the above technical solution, by comparing whether the first CRC value generated by the CRC circuit corresponding to the bit width of the parallel data is the same as the second CRC value, it can be determined whether the parallel data passes the CRC. That is to say, the above technical solution only needs one CRC circuit. Compared with the technical solution in the prior art that requires multiple CRC circuits for CRC checking on parallel data with a bit width of multiple bytes, the above technical solution requires fewer hardware resources.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

Fig. 1 is a flow chart of a verification method provided by an embodiment of the present invention;

FIG. 2 is a flow chart of a method for processing second data to obtain Y data provided by an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a verification device provided by an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a verification device provided by an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the following describes the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings For further detailed explanation.

FIG. 1 is a flowchart of a verification method provided by an embodiment of the present invention. Referring to Figure 1, the method includes:

101. Receive parallel data.

For example, the execution subject of 101 may be a receiver.

For example, the parallel data can be obtained as follows:

The serial-to-parallel converter processes the received serial data and converts it into the parallel data.

The number of bytes of the parallel data is X, and the bit width of the parallel data is Y bytes, where X is a positive integer and Y is a positive integer. For example, the value of Y can be 1, 2 or 3.

102. Use a CRC circuit to perform operations on the parallel data to obtain a first CRC value.

For example, the execution subject of 102 may be a hardware circuit, such as ASIC (Application Specific Integrated Circuit, application specific integrated circuit) or FPGA (Field-Programmable Gate Array, field programmable gate array).

Those skilled in the art can understand that the CRC circuit is a circuit corresponding to the bit width of the parallel data.

103. Compare whether the first CRC value is the same as the second CRC value.

The second CRC value is a CRC value obtained by performing CRC on the first data, the first data is data obtained by adding M bytes of data at the end of the second data, and the second data is the data obtained by adding M bytes at the end of the second data. The data obtained by adding the third CRC value to the end of the data, the third CRC value is the CRC value of the third data, and M is equal to the remainder of Y minus X divided by Y, that is, M=Y-MOD(X, Y ). MOD(X,Y) is equal to the remainder of dividing X by Y. The M bytes of data may be constants, such as M bytes of 0 or M bytes of 1.

For example, the execution subject of 103 may be a comparator.

104. If the first CRC value is the same as the second CRC value, determine that the parallel data passes the CRC.

The execution subject of 104 may be a central processing unit (central processing unit, CPU), or a network processor (network processor, NP). For example, the execution subject of 104 may be the forwarding unit of the NP. For example, if the forwarding unit determines that the parallel data passes the CRC, the forwarding unit may forward the parallel data. If the forwarding unit determines that the parallel data does not pass the CRC, the forwarding unit may discard the parallel data.

Those skilled in the art can understand that in the above technical solution, if the third data takes different values, the second data must also take different values, and the first data must also take different values, but the The second CRC value takes the same value.

For example, if the third data is 0x55, the third CRC value obtained by using Ethernet CRC32 to operate on the third data is 0xfb4a03c9, then the data obtained by adding the third CRC value at the end of the third data is 0x55fb4a03c9, that is, the second data is 0x55fb4a03c9. Adding N bytes of data at the end of the second data to obtain the first data. The first data is 0x55fb4a03c900. The data of the N bytes is 0x00. Wherein, N is 1. Then, CRC calculation is performed on the first data, for example, using Ethernet CRC32, and the obtained CRC value of the first data is 0x1df722c6. Therefore, the second CRC value is 0x1df722c6.

If the third data is 0x55aa, the third CRC value obtained by using Ethernet CRC32 to operate on the third data is 0x18f116b0, then the data obtained by adding the third CRC value at the end of the third data is 0x55aa18f116b0, That is, the second data is 0x55aa18f116b0. N bytes of data are also added to the end of the second data to obtain the first data. The first data is 0x55aa18f116b000, and the N bytes of data are 0x00. Wherein, N is 1. Then perform CRC calculation on the first data, for example, using Ethernet CRC32, and the obtained CRC value of the first data is also 0x1df722c6. Therefore, the second CRC value is 0x1df722c6.

If the third data is 0x55aa55, the third CRC value obtained by using Ethernet CRC32 to operate on the third data is 0x51c4dfda, then the data obtained by adding the third CRC value at the end of the third data is 0x55aa5551c4dfda, That is, the second data is 0x55aa5551c4dfda. N bytes of data are also added to the end of the second data to obtain the first data. The first data is 0x55aa5551c4dfda00, and the N bytes of data are 0x00. Wherein, N is 1. Then perform CRC calculation on the first data, for example, using Ethernet CRC32, and the obtained CRC value of the first data is also 0x1df722c6. Therefore, the second CRC value is 0x1df722c6.

According to the above description, it can be seen that the second CRC value is related to M, has nothing to do with the third data, has nothing to do with the second data, and has nothing to do with the values of the M bytes. After the value of M is determined, the second CRC value is also determined. According to the above rules, after the first CRC value of the parallel data is obtained, if the first CRC value is the same as the second CRC value, it can be determined that the parallel data passes the CRC.

In the above technical solution, by comparing whether the first CRC value generated by the CRC circuit corresponding to the bit width of the parallel data is the same as the second CRC value, it can be determined whether the parallel data passes the CRC. That is to say, the above technical solution only needs one CRC circuit. Compared with the technical solution in the prior art that requires multiple CRC circuits for CRC checking on parallel data with a bit width of multiple bytes, the above technical solution requires fewer hardware resources.

Optionally, in the method shown in FIG. 1, using the CRC circuit to perform operations on the parallel data may include:

If the remainder of dividing X by Y is not equal to 0, then add the fourth data at the end of the parallel data, the length of the fourth data is M bytes to obtain new parallel data; the fourth data can be a constant , for example, can be M bytes of 0 or M bytes of 1, etc. The byte length of the fourth data and the byte length of the data added at the end of the second data are both M.

The CRC circuit is used to perform operations on the new parallel data.

Optionally, in the method shown in FIG. 1, using the CRC circuit to perform operations on the parallel data may include:

If the remainder of dividing X by Y is equal to 0, no data is added to the end of the parallel data, and the CRC circuit is used to perform operations on the parallel data.

Optionally, in the method shown in FIG. 1, before comparing whether the first CRC value is the same as the second CRC value, the method may also include:

201. Add 1 to Y bytes of data to the end of the second data respectively to obtain Y data.

For example, if the bit width of the parallel data is 8 bytes, 1 to 8 bytes of data are respectively added to the end of the second data to obtain 8 data. The data obtained by adding 4 bytes of data at the end of the second data is one of the 8 pieces of data.

202. Perform CRC on the Y data respectively to obtain Y CRC values.

For example, after the Y CRC values are obtained, the Y CRC values may be stored, specifically, the added bytes and their corresponding CRC values may be stored in a list form.

203. Determine that the CRC value corresponding to the Y CRC value and the Y data obtained by adding the M bytes of data at the end of the second data is the second CRC value .

For example, if the number of bytes of the parallel data is 36, and the bit width of the parallel data is 8 bytes, then it can be determined that M is 4 according to the formula M=Y-MOD(X,Y), then the Among the 8 pieces of data, data obtained by adding the 4 bytes of data at the end of the second data is used as the first data. The CRC value corresponding to the first data is the second CRC value.

Regarding 201, 202 and 203, please refer to FIG. 2 for details.

Fig. 3 is a schematic structural diagram of a verification device provided by an embodiment of the present invention. The checking device can execute the method shown in FIG. 1 . Referring to Fig. 3, the verification device includes:

The receiving unit 301 is configured to receive parallel data, the number of bytes of the parallel data is X, the bit width of the parallel data is Y bytes, X is a positive integer, and Y is a positive integer.

For example, the receiving unit 301 may be a receiver.

For example, the parallel data can be obtained as follows:

The serial-to-parallel converter processes the received serial data and converts it into the parallel data.

The number of bytes of the parallel data is X, and the bit width of the parallel data is Y bytes, where X is a positive integer and Y is a positive integer. For example, the value of Y can be 1, 2 or 3.

The CRC circuit 302 is configured to perform operations on the parallel data received by the receiving unit 301 to obtain a first CRC value.

For example, the CRC circuit 302 may be a hardware circuit. The hardware circuit may be ASIC or FPGA.

Those skilled in the art can understand that the CRC circuit is a circuit corresponding to the bit width of the parallel data.

A comparing unit 303, configured to compare whether the first CRC value generated by the cyclic redundancy check circuit 302 is the same as a second CRC value, the second CRC value being a CRC value obtained by performing CRC on the first data, The first data is data obtained by adding M bytes of data at the end of the second data, the second data is data obtained by adding a third CRC value at the end of the third data, and the third CRC value is the CRC value of the third data, and M is equal to the remainder of Y minus X divided by Y.

The second CRC value is a CRC value obtained by performing CRC on the first data, the first data is data obtained by adding M bytes of data at the end of the second data, and the second data is the data obtained by adding M bytes at the end of the second data. The data obtained by adding the third CRC value to the end of the data, the third CRC value is the CRC value of the third data, and M is equal to the remainder of Y minus X divided by Y, that is, M=Y-MOD(X, Y ). MOD(X,Y) is equal to the remainder of dividing X by Y. The M bytes of data may be constants, such as M bytes of 0 or M bytes of 1.

For example, the comparison unit 303 may be a comparator.

The first determining unit 304 is configured to determine that the parallel data passes the CRC if the comparison result of the comparing unit 303 is that the first CRC value is the same as the second CRC value.

The first determination unit 304 may be a CPU or an NP. For example, the first determining unit 304 may be a forwarding unit of the NP. For example, if the forwarding unit determines that the parallel data passes the CRC, the forwarding unit may forward the parallel data. If the forwarding unit determines that the parallel data does not pass the CRC, the forwarding unit may discard the parallel data.

The verification device can determine whether the parallel data passes the CRC by comparing whether the first CRC value generated by the CRC circuit corresponding to the bit width of the parallel data is the same as the second CRC value. That is to say, the above checking device only needs one CRC circuit. Compared with the device in the prior art that requires multiple CRC circuits for performing CRC verification on parallel data with a bit width of multiple bytes, the verification device requires fewer hardware resources.

Optionally, in the verification device shown in FIG. 3, the CRC circuit may be specifically configured to: if the remainder of dividing X by Y is not equal to 0, add fourth data at the end of the parallel data, and the first The length of the four data is M bytes, and new parallel data is obtained; and operation is performed on the new parallel data.

Optionally, in the verification device shown in FIG. 3 , the CRC circuit can be specifically used for: if the remainder of dividing X by Y is equal to 0, then no data is added to the end of the parallel data, and the parallel data is performed operation.

Optionally, in the verification device shown in Figure 3, it may also include:

Adding unit 405, configured to respectively add 1 to Y bytes of data at the end of the second data to obtain Y data;

A computing unit 406, configured to perform CRC on the Y data generated by the adding unit 405 to obtain Y CRC values;

The second determination unit 407 is configured to determine whether the Y CRC values obtained by the calculation unit 406 are consistent with the addition before the comparison unit 303 compares whether the first CRC value is the same as the second CRC value. Among the Y data obtained by the unit 405, the CRC value corresponding to the data obtained by adding the M bytes of data at the end of the second data is the second CRC value.

For example, the comparing unit 303 may compare whether the first CRC value is the same as the second CRC value according to the second CRC value determined by the second determining unit 407 .

For details about the adding unit 405 , the calculating unit 406 and the second determining unit 407 , please refer to FIG. 4 .

An embodiment of the present invention also provides a network device, which includes the verification device shown in FIG. 3 or the verification device shown in FIG. 4 .

For example, the network device may be a router, a switch, a broadband remote access server (broadband remote access server, BRAS), a firewall or a load balancer.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (9)

1. a method of calibration is characterized in that, comprising:

Receive parallel data, the byte number of described parallel data is X, and the bit wide of described parallel data is Y byte, and X is positive integer, and Y is positive integer;

Adopt the cyclic redundancy check (CRC) circuit that described parallel data is carried out computing, obtain the first crc value;

Whether more described the first crc value is identical with the second crc value, described the second crc value is that the first data are carried out the crc value that CRC obtains, the data that described the first data obtain for the data of adding M byte at the afterbody of the second data, described the second data are added the data that the 3rd crc value obtains for the afterbody in the 3rd data, described the 3rd crc value is the crc value of described the 3rd data, and M equals Y and deducts X divided by the remainder of Y;

If described the first crc value is identical with described the second crc value, then definite described parallel data is passed through CRC.

2. method according to claim 1 is characterized in that, the described CRC circuit of described employing carries out computing to described parallel data and comprises:

If X is not equal to 0 divided by the remainder of Y, then the afterbody in described parallel data adds the 4th data, and the length of described the 4th data is M byte, obtains new parallel data;

Adopt described CRC circuit that described new parallel data is carried out computing.

3. method according to claim 1 and 2 is characterized in that, the described CRC circuit of described employing carries out computing to described parallel data and comprises:

If X equals 0 divided by the remainder of Y, then not in the afterbody interpolation data of described parallel data, adopt described CRC circuit that described parallel data is carried out computing.

4. arbitrary described method in 3 according to claim 1 is characterized in that, before whether more described the first crc value and described the second crc value be identical, described method also comprised:

Add respectively the data of 1 to Y byte at the afterbody of described the second data, obtain Y data;

Respectively described Y data are carried out CRC, obtain Y crc value;

Determine in the described Y crc value with a described Y data in to add crc value corresponding to data that the data of a described M byte obtain by the afterbody in described the second data be described the second crc value.

5. a calibration equipment is characterized in that, comprising:

Receiving element is used for receiving parallel data, and the byte number of described parallel data is X, and the bit wide of described parallel data is Y byte, and X is positive integer, and Y is positive integer;

The cyclic redundancy check (CRC) circuit is used for the described parallel data that described receiving element receives is carried out computing, obtains the first crc value;

Comparing unit, whether described the first crc value that is used for more described CRC circuit evolving is identical with the second crc value, described the second crc value is that the first data are carried out the crc value that CRC obtains, the data that described the first data obtain for the data of adding M byte at the afterbody of the second data, described the second data are added the data that the 3rd crc value obtains for the afterbody in the 3rd data, described the 3rd crc value is the crc value of described the 3rd data, and M equals Y and deducts X divided by the remainder of Y;

The first determining unit is that described the first crc value is identical with described the second crc value if be used for the comparative result of described comparing unit, and then definite described parallel data is passed through CRC.

6. calibration equipment according to claim 5 is characterized in that, described CRC circuit specifically is used for:

If X is not equal to 0 divided by the remainder of Y, then the afterbody in described parallel data adds the 4th data, and the length of described the 4th data is M byte, obtains new parallel data;

Described new parallel data is carried out computing.

7. according to claim 5 or 6 described calibration equipments, it is characterized in that, described CRC circuit specifically is used for:

If X equals 0 divided by the remainder of Y, then not in the afterbody interpolation data of described parallel data, described parallel data is carried out computing.

8. arbitrary described calibration equipment in 7 according to claim 5 is characterized in that, described calibration equipment also comprises:

Adding device, the data for add respectively 1 to Y byte at the afterbody of described the second data obtain Y data;

Computing unit, described Y data that are used for respectively described adding device being generated are carried out CRC, obtain Y crc value;

Adding crc value corresponding to data that the data of a described M byte obtain by the afterbody in described the second data in described Y the data that the second determining unit, described Y the crc value that is used for that definite described computing unit obtains before more described the first crc value of described comparing unit and described the second crc value be whether identical and described adding device obtain is described the second crc value.

9. a network equipment is characterized in that, the described network equipment comprises such as arbitrary described calibration equipment in the claim 5 to 8.

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