CN103888314B - The method that finite state machine status are verified based on uio sequence method - Google Patents
The method that finite state machine status are verified based on uio sequence method Download PDFInfo
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Abstract
The invention discloses a kind of method that finite state machine status are verified based on uio sequence method, mainly solve in communication protocol, when some states do not exist uio sequence, it is impossible to use uio sequence method, the complicated problem of state verification process.Implementation step is：1）The finite state machine of abbreviation communication protocol；2）Selection does not exist the state of uio sequence as state to be verified；3）The state that there is identical input, output behavior with state to be verified is selected as verification state；4）Input, output action selection incoming event sequence according to state to be verified and verification state；5）Whether the outgoing event sequence according to system under test (SUT) is consistent with the regulation of finite state machine, verifies whether state to be verified is expecting state.The present invention extends the range of application of uio sequence method, simplifies the generating process of uniformity test collection and shortens the test sequence of generation, can be applied to the design of test set in the uniformity test of communication protocol.
Description
Technical field
The invention belongs to communication technical field, more particularly to a kind of method for verifying finite state machine status can be used
Uniformity is surveyed in the case of in various communication protocols, some states are in the absence of unique input and output uio sequence in its finite state machine
Try the design and realization of collection.
Background technology
The uniformity test of agreement is a kind of Black-box Testing, system and consensus standard the purpose is to check operation agreement
Matching degree.In unification of communication protocol test, test set is the set of the multiple cycle tests for meeting test philosophy.Test
Sequence is generally made up of three parts：Homing sequence, test input-output operation, state verification sequence.Wherein, homing sequence is used for
System under test (SUT) state in which is set to required state；Test input-output operation is used to verify system under test (SUT) with protocol requirement
Whether behavior is consistent；State verification sequence is used to check whether system under test (SUT) has been transformed into the state described by protocol specification.Shape
State verifies part one of of the sequence as cycle tests, and the error detecing capability to improving cycle tests plays an important role.
At present, the building method of most state verification sequence is all based on finite state machine.One finite state
Machine can be expressed as five-tuple（S, I, O, δ, γ）, wherein, S is that the finite nonempty set of state is closed, and I is the limited non-of incoming event
Null set, O is that the finite nonempty set of outgoing event is closed, and δ is state transition function, and γ is output function.Finite state machine needs tool
Standby following essential characteristic：
1. the status number of finite state machine, incoming event number and produced outgoing event number are all limited, determine.
2. all incoming events can be received under each state of finite state machine.
3. for each incoming event, if finite state machine can produce outgoing event, then the outgoing event will be
Produced in given finite time.
4. each state of finite state machine is reachable, and its state transition diagram is connected graph.
Finite state machine is currently directed to, the method for main state verification sequence structure there are three kinds：Distinguishing sequence method, feature
Sequence sets method, uio sequence method.Compared with distinguishing sequence method, characteristic sequence collection method, uio sequence method complexity is low, and the survey for generating
Examination sequence length is shorter, therefore, in the modeling process in the sequential behavior field such as digital display circuit and communication, particularly finding excellent
The test set aspect extensive application of change.
Uio sequence is unique input and output sequence, i.e., for finite state machine in a certain state, other states all can not
Same input/output I/O sequences are shown, thus the uio sequence can be with unique mark and this state of checking.A certain
Under state Sa, for a certain input y, the output λ a of and if only if state Sa from other it is stateful under output it is different when,
Then y/ λ a are the uio sequences of state Sa, are denoted as UIO (Sa)=y/ λ a, wherein, y/ λ a represent the input/output sequence in state Sa
Row.The step of solving UIO (Sa) is as follows：
1）If state set P is the set of the state that can be just reached by 1 step from Sa, check from Sa to state set P
Whether have the unique path of I/O sequences in 1 stateful step footpath：If so, then the I/O sequences be exactly Sa uniquely input it is defeated
Go out uio sequence；Otherwise, step 2 is performed）；
2）If state set Q is the set of the state that can be just reached by n steps from Sa, n >=2 are checked from Sa to state set
Whether there is the unique path of I/O sequences in stateful n steps footpath in conjunction Q：If so, then the I/O sequences are exactly the unique of Sa
Input and output uio sequence；Otherwise, whether n=n+1, reexamining in stateful n steps footpath from Sa to state set Q has
The unique path of I/O sequences；
I/O sequences and uio sequence are constituted by incoming event sequence and outgoing event sequence, and incoming event sequence represents I/
The combination of an incoming event in O sequences or the multiple incoming events with precedence relationship, outgoing event sequence represents I/O sequences
The combination of an outgoing event in row or the multiple outgoing events with precedence relationship.
Based on uio sequence method is exactly the uio sequence of each state in finding finite state machine, structural regime checking sequence
The method of row.After obtaining state verification sequence, in conjunction with homing sequence, test input-output operation, so that it may obtain cycle tests,
The set of all cycle tests just constitutes complete test set.It is, therefore, usually considered that, stateful UIO could be searched out
Can sequence be the premise that use uio sequence method.
In most cases, each state can find uio sequence in finite state machine, but in some cases, it is limited
Some states of state machine do not exist uio sequence.For example for a certain state Sa, to any input y, there are output λ a, and shift
To a certain state Sb, to state Sb, y is equally input into, if identical exports λ a, then state Sa does not exist uio sequence.It is such as attached
Shown in Fig. 2, wherein representing state with circular, the transfer of state is represented with the solid line with arrow, what is identified on solid line is state
The condition of transfer, i.e. I/O behaviors represent incoming event and outgoing event with English alphabet.Under state S2, B is input into, obtains defeated
Go out Y and be transferred to state S3, due to being input into B under state S3, be similarly obtained output Y, then state S2 does not exist uio sequence.It is logical
Often think now to will be unable to carry out state verification to these states using uio sequence method, can only transfer using distinguishing sequence method, spy
The increasingly complex verification method such as sequence sets method is levied, makes uniformity test collection more complicated, increased the length of cycle tests.
The content of the invention
The present invention is proposed a kind of based on residing for uio sequence method checking finite state machine for the deficiency of above-mentioned prior art
The method of state, in the case of not existing uio sequence in partial status, with reference to the I/O sequences of other states, has by excluding
Limit state machine is in the possibility of other states, and realization carries out state verification to the state in the absence of uio sequence, so as to simplify consistent
The generating process of property test set and shorten generation cycle tests length.
To achieve the above object, technical scheme comprises the following steps：
（1）To the finite state machine of the communication protocol of uniformity test to be carried out, merge its equivalent state, make finite state
Machine is most simple；
（2）The uio sequence of each state in finite state machine is obtained, the state in the absence of uio sequence is found out, and constitute to be tested
Card state set M；
（3）From the state set M to be verified, a state is arbitrarily chosen as state Si to be verified；
（4）Any input/output I/O sequences of state Si to be verified are selected, containing in addition to state Si to be verified is found out
There is the institute of input/output I/O sequences stateful, and constitute verification state set N；
（5）System under test (SUT) state in which is set to state Si to be verified；
（6）To system under test (SUT) input step（4）The incoming event sequence of the I/O sequences of middle selection, and check system under test (SUT)
Outgoing event sequence：
6a）If the outgoing event sequence phase under state Si to be verified that outgoing event sequence specifies with finite state machine
Symbol, then perform step（7）；
6b）If the outgoing event sequence under state Si to be verified that outgoing event sequence specifies with finite state machine is not
It is consistent, then state to be verified is not expecting state, terminates this state verification process.
（7）System under test (SUT) state in which is set to state Si to be verified；
（8）An optional state is used as verification state Sj from verification state set N；
（9）An I/O sequence for selecting state Si to be verified to be differed with state Sj, the I/O sequences are input into system under test (SUT)
The incoming event sequence of row, and check the outgoing event sequence of system under test (SUT)：
9a）If the outgoing event sequence under state Si to be verified that outgoing event sequence specifies with finite state machine is not
It is consistent, then state to be verified is not expecting state, terminates this state verification process；
9b）If the outgoing event sequence phase under state Si to be verified that outgoing event sequence specifies with finite state machine
Symbol, state Sj is deleted from verification state set N, and judges whether verification state set N is empty：
9b1）If verification state set N is not sky, step is performed（7）；
9b2）If verification state set N is sky, prove that state to be verified, for expecting state, performs step（10）；
（10）Above-mentioned state Si to be verified is deleted from state set M to be verified；
（11）Repeat step（3）To step（10）, it is verified as until the institute in state set M to be verified is stateful
Only.
The present invention combines exclusive method thought on the basis of uio sequence is used as state verification sequence, by excluding
Finite state machine is in the possibility of some states, and whether final checking finite state machine is in expected state, so as to extend
The scope of application of uio sequence method, makes partial status avoid using more complicated differentiation in the absence of the finite state machine of uio sequence
Serial method and characteristic sequence collection method, simplify the generating process of uniformity test collection and shorten the length of the cycle tests of generation.
Brief description of the drawings
Fig. 1 realizes flow chart for of the invention；
Fig. 2 is the state transition diagram of the finite state machine of embodiment one；
Fig. 3 is the state transition diagram before the finite state machine merging phase of embodiment two；
Fig. 4 is the state transition diagram after the finite state machine merging phase of embodiment two.
Specific embodiment
Present disclosure is further elaborated below in conjunction with the accompanying drawings.
Reference picture 1, the present invention provides following two embodiments.
Embodiment one：
The present embodiment is identical defeated not contain equivalent state and have a state to have with the state in the absence of uio sequence
Enter/communication protocol of output sequence as a example by, illustrate to run the communication protocol system under test (SUT) in the absence of uio sequence state
Carry out the process of state verification.
The state transition diagram of the communication protocol as shown in Fig. 2 wherein, state is represented with circular, with the solid line table with arrow
Show the transfer of state, what is identified on solid line is the condition of state transfer, i.e. input/output behavior represents three with alphabetical A, B and C
Different incoming events are planted, three kinds of different outgoing events are represented with alphabetical X, Y and Z.This finite state machine includes three states：
First state S1, the second state S2 and third state S3.If the original state of finite state machine is first state S1.When limited shape
When state machine is in a certain state, if receiving certain incoming event, finite state chance produces corresponding outgoing event, and its institute
The state at place can also be shifted.Reference picture 2, this finite state machine be directed to outgoing event produced by the incoming event that receives and
Its state transfer case is：
When finite state machine is in first state S1, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to the second state S2.If the incoming event that it is received is B or C, limited shape
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the second state S2, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is Y, and its state in which is transferred to third state S3.If the incoming event that it is received is A or C, limited shape
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in third state S3, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is Y, and its state in which is transferred to third state S3.If the incoming event that it is received is C, finite state machine
The outgoing event of generation is Z, and its state in which is transferred to first state S1.If the incoming event that it is received is A, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
Reference picture 2 is as follows the step of carry out state verification to this example：
Step 1, the finite state machine of abbreviation communication protocol.
Because the finite state machine that this example is used does not contain equivalent state, without merging.
Step 2, the method using uio sequence is solved obtains the uio sequence of each state finite state machine Nei.
When finite state machine is in first state S1, if its incoming event for receiving is A, it is defeated that finite state machine is produced
Outgoing event is X, because other states in finite state machine all do not have input/output A/X, so the UIO of first state S1
Sequence is A/X.
The solution procedure of the uio sequence of the second state S2 includes following three kinds of situations：
When incoming event is A, the second state S2 and third state S3 has identical outgoing event, and shape residing for finite state machine
State is not shifted.
When incoming event is B, the second state S2 and third state S3 has identical outgoing event, and shape residing for finite state machine
State is transferred to state S3.
When incoming event is C, the second state S2 and first state S1 has identical outgoing event, and shape residing for finite state machine
State is not shifted.
So the second state S2 does not exist uio sequence；
When finite state machine is in third state S3, if its incoming event for receiving is C, it is defeated that finite state machine is produced
Outgoing event is Z, because other states in finite state machine all do not have sequence C/Z, so the uio sequence of third state S3 is
C/Z。
Step 3, uio sequence is whether there is according to each state in finite state machine, finds out the state in the absence of uio sequence,
State set M to be verified is constituted, to select state to be verified.
The uio sequence of each state tried to achieve from step 2, only the second state S2 do not exist uio sequence, so second
State S2 is separately formed state set M to be verified, and selects the second state S2 as state Si to be verified.
Step 4, finds out the state that verification state set N is included, with selection check state Sj.
Input/output sequence B/the Y of the second state S2 is selected, it is defeated due to only having third state S3 to contain in other states
Enter/output sequence B/Y, so verification state set N includes third state S3, and select third state S3 as verification state
Sj。
Step 5, to system under test (SUT) incoming event A, makes system under test (SUT) state in which be transferred to state Si to be verified.
Step 6, to the incoming event B of the input/output sequence selected in system under test (SUT) input step 4, checks tested system
The outgoing event of system：
If outgoing event is not Y, prove that state to be verified is not expected second state S2, state verification process knot
Beam；
If outgoing event is Y, the possibility that state to be verified is first state S1 is eliminated, if because tested
System is in first state S1, and for incoming event B, its outgoing event should be without response.Perform step 7.
Step 7, event C and A are sequentially input to system under test (SUT), system under test (SUT) state in which is transferred to state to be verified
Si。
Step 8, input, output behavior according to state Si to be verified and verification state Sj, selects incoming event, checks defeated
Outgoing event.
8a）According to electing third state S3 as schools in electing the second state S2 as state Si to be verified and step 4 in step 3
State Sj is tested, and when finite state machine is in the second state S2 and third state S3, different outputs is produced to incoming event C
The situation of event, therefore selection event C is used as the incoming event to system under test (SUT)；
8b）Check the outgoing event of system under test (SUT)：
To system under test (SUT) incoming event C, the outgoing event of generation is probably Z or without response：
If outgoing event is Z, prove that state to be verified is not expected second state S2, state verification process knot
Beam；
If system under test (SUT) is not responded to incoming event C, the possibility that state to be verified is third state S3 is eliminated,
Third state S3 is deleted from verification state set N, verification state set N is empty set, and so far, eliminating state to be verified is
The possibility of first state S1 and third state S3, so state to be verified is exactly expected second state S2, and by the second state
S2 is deleted from state set M to be verified, and now state set M to be verified is sky, done state verification process.
Embodiment two：
The present embodiment with containing equivalent state and have two states with the absence of uio sequence state have identical input/
As a example by the communication protocol of output sequence, illustrate that the state for not existing uio sequence in the system under test (SUT) to operation communication protocol is carried out
The process of state verification.
The state transition diagram of the communication protocol such as Fig. 3, wherein representing state with circular, state is represented with the solid line with arrow
Transfer, what is identified on solid line is the condition of state transfer, i.e. input/output behavior represents four kinds not with alphabetical A, B, C and D
Same incoming event, four kinds of different outgoing events are represented with letter w, X, Y and Z.This finite state machine includes five states：The
One state S1, the second state S2, third state S3, the 4th state S4 and the 5th state S5.If the original state of finite state machine
It is first state S1.When finite state machine is in a certain state, if receiving certain incoming event, finite state chance is produced
Outgoing event, and its state in which accordingly can also be shifted.Reference picture 3, this finite state machine is directed to the input for receiving
Outgoing event and its state transfer case produced by event are：
When finite state machine is in first state S1, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is W, and its state in which is transferred to the second state S2.If the incoming event that it is received is B, C or D, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the second state S2, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to third state S3.If the incoming event that it is received is A, C or D, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in third state S3, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is Z, and its state in which is transferred to the 5th state S5.If the incoming event that it is received is B, finite state machine
The outgoing event of generation is X, and its state in which is transferred to third state S3.If the incoming event that it is received is C, limited
The outgoing event that state machine is produced is Y, and its state in which is transferred to the 4th state S4.If the incoming event that it is received is D,
The outgoing event that then finite state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the 4th state S4, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to the 4th state S4.If the incoming event that it is received is D, finite state machine
The outgoing event of generation is Z, and its state in which is transferred to first state S1.If the incoming event that it is received is A or C,
The outgoing event that finite state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the 5th state S5, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to third state S3.If the incoming event that it is received is A, C or D, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
Reference picture 3 is as follows the step of carry out state verification to this example：
Step one, the finite state machine of abbreviation communication protocol.
Because for any incoming event, the second state S2 and the 5th state S5 have identical outgoing event, and shape
State transfer case is also identical, so the second state S2 and the 5th state S5 is equivalent state, merges the second state S2 and the 5th shape
State S5, the state transition diagram after merging is as shown in figure 4, wherein：
When finite state machine is in first state S1, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is W, and its state in which is transferred to the second state S2.If the incoming event that it is received is B, C or D, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the second state S2, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to third state S3.If the incoming event that it is received is A, C or D, limited
The outgoing event that state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in third state S3, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is Z, and its state in which is transferred to the 5th state S2.If the incoming event that it is received is B, finite state machine
The outgoing event of generation is X, and its state in which is transferred to third state S3.If the incoming event that it is received is C, limited
The outgoing event that state machine is produced is Y, and its state in which is transferred to the 4th state S4.If the incoming event that it is received is D,
The outgoing event that then finite state machine is produced is that, without response, and its state in which is not shifted.
When finite state machine is in the 4th state S4, if its incoming event for receiving is B, what finite state machine was produced
Outgoing event is X, and its state in which is transferred to the 4th state S4.If the incoming event that it is received is D, finite state machine
The outgoing event of generation is Z, and its state in which is transferred to first state S1.If the incoming event that it is received is A or C,
The outgoing event that finite state machine is produced is that, without response, and its state in which is not shifted.
Step 2, the method using uio sequence is solved obtains the uio sequence of each state finite state machine Nei.
When finite state machine is in first state S1, if its incoming event for receiving is A, what finite state machine was produced
Outgoing event is W, because other states in finite state machine all do not have sequence A/W, so the uio sequence of first state S1
It is A/W；
The solution procedure of the uio sequence of the second state S2 includes following four kinds of situations：
When incoming event is A, the second state S2 and the 4th state S4 have identical outgoing event, and residing for finite state machine
State is not shifted；
When incoming event is B, the second state S2 and third state S3 has identical outgoing event, and residing for finite state machine
State is transferred to state S3；
When incoming event is C, the second state S2 and first state S1 has identical outgoing event, and residing for finite state machine
State is not shifted；
When incoming event is D, the second state S2 and first state S1 has identical outgoing event, and residing for finite state machine
State is not shifted, so the second state S2 does not exist uio sequence；
When finite state machine is in third state S3, if its incoming event for receiving is C, what finite state machine was produced
Outgoing event is Y, because other states in finite state machine all do not have sequence C/Y, so the uio sequence of third state S3
It is C/Y.
When finite state machine is in the 4th state S4, if its incoming event for receiving is D, what finite state machine was produced
Outgoing event is Z, because other states in finite state machine all do not have sequence D/Z, so the uio sequence of the 4th state S4
It is D/Z.
Step 3, uio sequence is whether there is according to each state in finite state machine, finds out the state in the absence of uio sequence,
State set M to be verified is constituted, to select state to be verified.
The uio sequence of each state tried to achieve from step 2, the second state S2 does not exist uio sequence, so the second shape
State S2 is separately formed state set M to be verified, and selects the second state S2 as state Si to be verified.
Step 4, finds out the state that verification state set N is included.
Input/output sequence B/the X of the second state S2 is selected, due in other states, third state S3 and the 4th shape
State S4 contains input/output sequence B/X, so verification state set N includes third state S3 and the 4th state S4.
Step 5, to system under test (SUT) incoming event A, makes system under test (SUT) state in which be transferred to state Si to be verified.
Step 6, to the incoming event B of the input/output sequence selected in system under test (SUT) input step four, checks tested
The outgoing event of system：
If outgoing event is not X, prove that state to be verified is not expected second state S2, state verification process knot
Beam；
If outgoing event is X, the possibility that state to be verified is first state S1 is eliminated, if because tested
System is in first state S1, and for incoming event B, its outgoing event should be without response.Perform step 7.
Step 7, event C, D and A are sequentially input to system under test (SUT), are transferred to system under test (SUT) state in which to be verified
State Si.
Step 8, selection check state, input, output behavior, selection according to state Si to be verified and verification state Sj
Incoming event, and check outgoing event.
8.1）Third state S3 is selected from verification state set N as verification state Sj；
8.2）The second state S2 is elected as state Si to be verified and step 8.1 according in step 3）It is middle by third state S3
Elect verification state Sj as, and when finite state machine is in the second state S2 and third state S3, incoming event C is produced not
With the situation of outgoing event, therefore selection event C is used as the incoming event to system under test (SUT)；
8.3）Check the outgoing event of system under test (SUT).
To system under test (SUT) incoming event C, the outgoing event of generation is probably Y or without response：
If the event of output is Y, prove that state to be verified is not expected second state S2, state verification process knot
Beam；
If system under test (SUT) is not responded to incoming event C, the possibility that state to be verified is third state S3 is eliminated,
Third state S3 is deleted from verification state set N, state set N is now verified and is only included the 4th state S4, so the 4th
State S4 is verification state Sj, performs step 9.
Step 9, state Si to be verified is transferred to by system under test (SUT) state in which.
System under test (SUT) state in which is transferred to state Si to be verified according in step 7, and to tested in step 8
System incoming event C, system under test (SUT) is not responded to, and the not situation of generating state transfer, it is known that system under test (SUT) state in which
It has been state Si to be verified, the status without retransferring system under test (SUT).
Step 10, input, output behavior according to state Si to be verified and verification state Sj, selects incoming event, and examine
Look into outgoing event.
10.1）The second state S2 is elected as state Si to be verified and step 8.3 according in step 3）It is middle by the 4th state S4
Elect verification state Sj as, and when finite state machine is in the second state S2 or the 4th state S4, incoming event D is produced
The different situation of outgoing event, therefore selection event D is used as the incoming event to system under test (SUT)；
10.2）Check the outgoing event of system under test (SUT).
To system under test (SUT) incoming event D, the outgoing event of generation is probably Z or without response：
If outgoing event is Z, prove that state to be verified is not expected second state S2, state verification process knot
Beam；
If system under test (SUT) is not responded to incoming event D, the possibility that state to be verified is the 4th state S4 is eliminated,
4th state S4 is deleted from verification state set N, it is empty set now to verify state set N, so far, has been eliminated to be tested
Card state is possible of first state S1, third state S3 and the 4th state S4, so state to be verified is expected second shape
State S2, the second state S2 is deleted from state set M to be verified, and now state set M to be verified is sky, done state checking
Process.
Above description is only one of the invention specific example, does not constitute any limitation of the invention, it is clear that for
For one of skill in the art, after present invention and principle has been understood, all may be without departing substantially from the principle of the invention, structure
In the case of, the various amendments and change in formalization and details are carried out, but these are based on the amendment of inventive concept and change
Become still within claims of the invention.
Claims (3)
1. a kind of method that finite state machine status are verified based on uio sequence method, is comprised the following steps：
(1) to the finite state machine of the communication protocol of uniformity test to be carried out, merge its equivalent state, make finite state machine most
Letter；
(2) uio sequence of each state in finite state machine is obtained, the state in the absence of uio sequence is found out, and constitute shape to be verified
State set M；
(3) from the state set M to be verified, a state is arbitrarily chosen as state Si to be verified；
(4) any input/output I/O sequences of state Si to be verified are selected, is found out and is contained this in addition to state Si to be verified
The institute of input/output I/O sequences is stateful, and constitutes verification state set N；
(5) system under test (SUT) state in which is set to state Si to be verified；
(6) to the incoming event sequence of the I/O sequences of selection in system under test (SUT) input step (4), and the defeated of system under test (SUT) is checked
Outgoing event sequence：
If 6a) outgoing event sequence is consistent with the outgoing event sequence under state Si to be verified that finite state machine specifies,
Then perform step (7)；
If 6b) the outgoing event sequence under state Si to be verified that outgoing event sequence specifies with finite state machine not phase
Symbol, then state to be verified is not expecting state, terminates this state verification process；
(7) system under test (SUT) state in which is set to state Si to be verified；
(8) from verification state set N an optional state as verification state Sj；
(9) an I/O sequence for selecting state Si to be verified to be differed with state Sj, the I/O sequences are input into system under test (SUT)
Incoming event sequence, and check the outgoing event sequence of system under test (SUT)：
If 9a) the outgoing event sequence under state Si to be verified that outgoing event sequence specifies with finite state machine not phase
Symbol, then state to be verified is not expecting state, terminates this state verification process；
If 9b) outgoing event sequence is consistent with the outgoing event sequence under state Si to be verified that finite state machine specifies,
State Sj is deleted from verification state set N, and judges whether verification state set N is empty：
If 9b1) verification state set N is not sky, step (7) is performed；
If 9b2) verification state set N is sky, prove that state to be verified, for expecting state, performs step (10)；
(10) above-mentioned state Si to be verified is deleted from state set M to be verified；
(11) repeat step (3) is verified to step (10) until the institute in state set M to be verified is stateful.
2. method according to claim 1, wherein the equivalent state in the step (1), refers in finite state machine
Two or more states, they for identical be input into, there is identical to export, and identical state can be transformed into.
3. method according to claim 1, wherein the UIO sequences for obtaining each state in finite state machine described in step (2)
Row, are carried out as follows：
(2a) from finite state machine institute it is stateful in appoint take a state Sa；
(2b) sets the set that state set P is the state that can be just reached by 1 step from Sa, checks the institute from Sa to state set P
Whether there is the unique path of I/O behaviors in 1 stateful step footpath：If so, then the I/O behaviors are exactly the uio sequence of Sa, perform
Step (2d)；Otherwise, step (2c) is performed；
(2c) sets the set that state set Q is the state that can be just reached by n steps from Sa, and n >=2 are checked from Sa to state set Q
Whether there is the unique path of I/O behaviors in middle stateful n steps footpath：If so, then the I/O sequences are exactly the uio sequence of Sa,
Perform step (2d)；Otherwise, whether n=n+1, reexamining in stateful n steps footpath from Sa to state set Q has I/
The unique path of O behaviors；
(2d) appoints the state for taking and not obtaining uio sequence yet from finite state machine, step (2b) is performed, until obtaining state set
In N untill stateful uio sequence.
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| CN110738384B (en) * | 2019-04-17 | 2022-09-23 | 北京航天飞行控制中心 | Event sequence checking method and system |
| CN110572296B (en) * | 2019-07-17 | 2021-01-08 | 国网江苏省电力有限公司电力科学研究院 | Internet of things terminal equipment communication protocol consistency safety detection method |
| CN111240883B (en) * | 2020-01-16 | 2023-08-29 | 北京工业大学 | System diagnosis method, device, equipment and storage medium based on finite state machine |
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