CN102916682B - Pulse width-adjustable NRZ/ R1 (non-return-to-zero/ return-to-1) code converting device - Google Patents
Pulse width-adjustable NRZ/ R1 (non-return-to-zero/ return-to-1) code converting device Download PDFInfo
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- CN102916682B CN102916682B CN201210427557.4A CN201210427557A CN102916682B CN 102916682 B CN102916682 B CN 102916682B CN 201210427557 A CN201210427557 A CN 201210427557A CN 102916682 B CN102916682 B CN 102916682B
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Abstract
The invention discloses a pulse width-adjustable NRZ/R1 (non-return-to-zero/ return-to-1) code converting device. The pulse width-adjustable NRZ/ R1 code converting device comprises a trigger synchronizing circuit, an inverted R1 code converting circuit and a pulse width control and R1 code output circuit, wherein firstly, an NRZ code data signal is synchronized to a system clock in the trigger synchronizing circuit; secondly, the NRZ code data signal is sent into the inverted R1 code converting circuit for phase inversion and then AND operation with an inverted system clock to obtain an inverted R1 code data signal; and finally, the inverted R1 code data signal is sent into the pulse width control and R1 code output circuit for pulse width adjustment to obtain an R1 code data signal with an adjustable pulse width. The pulse width-adjustable NRZ/R1 code converting device realizes conversion of the NRZ code data signal into the R1 code data signal and the pulse width adjustment through three simple circuits and the circuits are simple.
Description
Technical field
The invention belongs to high-speed data signal and produce technical field, more specifically say, relate to a kind of NRZ (Not Return to Zero, non-return-to-zero)/R1 (Return to One, normalizing) code converting apparatus of adjustable pulse width.
Background technology
High-speed data signal is the key factor of digital detecting system, test for various digital element device, parts, equipment and system is most important with development, all has a wide range of applications in each industries relevant to digitlization such as digital communication, radar, integrated circuit testing, computer bus tests.Meanwhile, in the universal testers such as high-speed data generator, pattern generator, code error tester, high-speed data signal source is all critical component.
Along with the develop rapidly of electronic technology and the extensive use of computer technology, electronic equipment and system intelligent, digitrend constantly strengthen.All types of digitization systems and the testing requirement of equipment constantly increase, diversified high-speed data generation technique progressively one of support technology becoming digital development.Wherein three kinds of conventional patterns exporting as data of NRZ, NRZ, normalizing code, are most widely used.
Because the speed of digitizer improves constantly, require that the output data rate of data signal source also improves constantly, take into account the generation of multiple conventional pattern simultaneously.But the generation of usual NRZ is relatively simple, and the generation of NRZ then needs again to change.
The generation of NRZ has two kinds of methods usually, comprises software editing method and hardware conversion method.Wherein software editing method is to sacrifice storage depth and data transfer rate simulates NRZ, and therefore the maximum data rate of NRZ is the half of NRZ usually, and pulse width control resolution limitations is in system clock cycle; The conversion of hardware NRZ is varied (application is with optical communication usually) then, but usual circuit all more complicated, and be difficult to realize adjustable pulse width, particularly for higher data rate applicable cases.Therefore, conventional method limits the raising of NRZ data transfer rate and is difficult to realize adjustable pulse width, and hardware circuit is complicated.
High-speed data produces has the advantages such as dark storage, two-forty, editor's convenience with synthesis, is widely used in digitizer test.But, also lack the simple NRZ with the adjustable pulse width/normalizing code converting apparatus of circuit at present.
Summary of the invention
The object of the invention is to overcome in prior art, provide a kind of circuit simple and the NRZ of adjustable pulse width/normalizing code converting apparatus.
For achieving the above object, the NRZ/normalizing code converting apparatus of adjustable pulse width of the present invention, is characterized in that, comprising:
One trigger synchronous circuits, for receiving system clock and the NRZ data-signal of data generating apparatus output, being synchronized to system clock by NRZ data-signal, exporting the NRZ data-signal with system clock synchronization;
One anti-phase normalizing code change-over circuit, for the NRZ data-signal that receiving system clock and trigger synchronous circuits export, and NRZ data-signal system clock, trigger synchronous circuits exported is anti-phase, then carries out and computing, obtains anti-phase normalizing code data signal;
Wherein, the time delay T of trigger synchronous circuits
pD1and in anti-phase normalizing code change-over circuit, anti-phase time delay T is carried out to the NRZ data-signal after synchronous
dD1sum is less than T/2+T
cDand T
pD1+ T
dD1>T
cD, T
cDfor carrying out anti-phase time delay to system clock in anti-phase normalizing code change-over circuit, T is system clock cycle; Can ensure so anti-phase after NRZ data-signal high level more anti-phase after system clock high level arrive in advance, realize the conversion of NRZ data-signal to anti-phase normalizing code data signal;
One pulse width control and normalizing code output circuit, pulse width control and normalizing code output circuit comprise a d type flip flop, a delay circuit and a not gate, the D termination high level of d type flip flop, the anti-phase normalizing code data signal that clock termination anti-phase normalizing code change-over circuit exports, when there is high level and rising edge in anti-phase normalizing code data signal, d type flip flop Q holds to export and becomes high level from low level, as d type flip flop reset signal after delay circuit, d type flip flop is exported reset, low level is become from high level, the output that d type flip flop Q holds connects not gate, after not gate is anti-phase, obtain the normalizing code data signal of adjustable pulse width, change the time of delay of delay circuit and the pulse duration of adjustable normalizing code data signal,
Wherein, high level representative data " 1 ", low level representative data " 0 ".
Goal of the invention of the present invention is achieved in that
NRZ/normalizing the code converting apparatus of adjustable pulse width of the present invention, comprise trigger synchronous circuits, anti-phase normalizing code change-over circuit and pulse width control and normalizing code output circuit, in trigger synchronous circuits, NRZ data-signal is synchronized to system clock, then send into carry out in anti-phase normalizing code change-over circuit anti-phase, carry out obtaining anti-phase normalizing code data signal with computing with anti-phase system clock again, finally anti-phase normalizing code data signal is sent in pulse width control and normalizing code output circuit and carry out pulse-width adjustment, obtain the normalizing code data signal of adjustable pulse width.NRZ/normalizing the code converting apparatus of adjustable pulse width of the present invention passes through three simple circuit realiration conversion of nonreturn to zero code data-signal to normalizing code data signal and the adjustment of pulsewidth, and circuit is simple.
Accompanying drawing explanation
Theory diagram when Fig. 1 is a kind of specific embodiment party of the NRZ/normalizing code converting apparatus of adjustable pulse width of the present invention;
Fig. 2 is the circuit diagram of the NRZ/normalizing code converting apparatus of dotted box portion and adjustable pulse width in Fig. 1;
Fig. 3 is the timing waveform of the NRZ/normalizing code converting apparatus of adjustable pulse width shown in Fig. 2.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.Requiring particular attention is that, in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these are described in and will be left in the basket here.
Theory diagram when Fig. 1 is a kind of specific embodiment party of the NRZ/normalizing code converting apparatus of adjustable pulse width of the present invention.
In the present embodiment, as shown in Figure 1, the NRZ/RZ code converting apparatus of adjustable pulse width of the present invention comprises trigger synchronous circuits 1, anti-phase normalizing code change-over circuit 2 and pulse width control and normalizing code output circuit 3.
Data generating apparatus 4 produces system clock CLK and NRZ data-signal D
iNbe sent in trigger synchronous circuits 1, by NRZ data-signal D in trigger synchronous circuits 1
iNbe synchronized to system clock CLK, export the NRZ data-signal D synchronous with system clock CLK
nRZ, concrete sequential relationship as shown in Figure 3.
The NRZ data-signal D that anti-phase normalizing code change-over circuit 2 receiving system clock CLK and trigger synchronous circuits 1 export
nRZ, and by the NRZ data-signal D of trigger synchronous circuits output
nRZand system clock CLK anti-phase be /D
nRZ,/CLK, then carries out and computing, obtains nrz data signal anti-phase normalizing code data signal D
/ R1, concrete sequential relationship as shown in Figure 3.
Wherein, the time delay T of trigger synchronous circuits 1
pD1and to the NRZ data-signal D after synchronous in anti-phase normalizing code change-over circuit
nRZcarry out anti-phase time delay T
dD1sum is less than T/2+T
cDand T
pD1+ T
dD1>T
cD, T
cDfor in anti-phase normalizing code change-over circuit, 2 couples of system clock CLK carry out anti-phase time delay, T is system clock cycle; Can ensure so anti-phase after NRZ data-signal D
nRZsystem clock after high level is more anti-phase/CLK high level arrives in advance, realizes the conversion of NRZ data-signal to anti-phase normalizing code data signal.
Pulse width control and normalizing code output circuit 3 comprise a d type flip flop, a delay circuit and a not gate, the D termination high level of d type flip flop, the D termination high level of d type flip flop, the anti-phase normalizing code data signal D that clock termination anti-phase normalizing code change-over circuit exports
/ R1, at anti-phase normalizing code data signal D
/ R1when there is high level and rising edge, d type flip flop Q holds to export and becomes high level from low level, as d type flip flop reset signal after delay circuit, d type flip flop is exported reset, low level is become from high level, the output that d type flip flop Q holds connects not gate, after not gate is anti-phase, obtains the normalizing code data signal D of adjustable pulse width
r1, change the time of delay of delay circuit and the pulse duration of adjustable normalizing code data signal;
Wherein, high level representative data " 1 ", low level representative data " 0 ".
In the present embodiment, digital generation device 4, control bus 5 and D/A circuit 6 is the NRZ/normalizing code converting apparatus external circuit of adjustable pulse width.The finished product instrument of numeral generation device 4 can be data generating module circuit also can be data generator or pattern generator, the NRZ/normalizing code converting apparatus for adjustable pulse width provides system clock and NRZ NRZ data-signal.Pulse width control in the NRZ that control bus 5 is adjustable pulse width/normalizing code converting apparatus and normalizing code output circuit 3 provide Time delay control data or provide control data for D/A circuit 6, realize the control of NRZ pulsewidth.The delay circuit that D/A circuit 6 controls for analog level provides control level, thus realizes the precise hard_drawn tuhes of NRZ pulsewidth.
Fig. 2 is the circuit diagram of the NRZ/normalizing code converting apparatus of dotted box portion and adjustable pulse width in Fig. 1.
In the present embodiment, as shown in Figure 2, trigger synchronous circuits 1 adopts d type flip flop to realize, NRZ data-signal D
iNconnect the D end of d type flip flop, system clock CLK connects the clock end of d type flip flop, and the Q end of d type flip flop is the output of trigger synchronous circuits 1.At NRZ data-signal D
iNfor high level, and when system clock CLK rising edge arrives, export high level, at NRZ data-signal D
iNfor low level, and when system clock CLK rising edge arrives, output low level, NRZ data-signal D
iNbe synchronized on system clock CLK, obtain the NRZ data-signal D synchronously
nRZ.Concrete sequential relationship as shown in Figure 3.
Utilize NRZ data-signal D
iNproduce relevant system clock CLK by d type flip flop U1 to NRZ data-signal D
iNcarry out re-synchronization, guarantee NRZ/normalizing code converting apparatus internal clock and the NRZ data-signal D of adjustable pulse width
iNbetween delay relation.Utilize d type flip flop U1 trigger delay T
pD1shorter feature, time delay T in design
pD1choose the d type flip flop being less than system clock cycle T half, thus ensure anti-phase after NRZ data-signal D
nRZeach rising edge always appear at reversed-phase system clock/CLK rising edge after, and time interval is less than half system clock cycle.
In the present embodiment, as shown in Figure 2, anti-phase normalizing code change-over circuit 2 comprises two not gates U2, U3 and one and door U4; The NRZ data-signal D that trigger synchronous circuits exports
nRZcarrying out anti-phase time delay at not gate U2 is T
dD1, it is T that system clock CLK carries out anti-phase time delay at not gate U3
cD, consider time delay T
cD, d type flip flop U1 trigger delay T
pD1and not gate U2 carries out anti-phase time delay T to the NRZ data-signal after synchronous
dD1sum is less than T/2+T
cDand T
pD1+ T
dD1>T
cD,
Can ensure so anti-phase after NRZ data-signal/D
nRZsystem clock after high level is more anti-phase/CLK high level arrives in advance, anti-phase rear NRZ data-signal/D
nRZcarrying out and computing with door U4 with the system clock/CLK after anti-phase, realizing NRZ data-signal/D
nRZto anti-phase normalizing code data signal D
/ R1conversion; The anti-phase normalizing code data signal D obtained
/ R1pulse duration be system clock CLK low level width.Concrete sequential relationship as shown in Figure 3.
In the present embodiment, as shown in Figure 2, pulse width control and normalizing code output circuit 3 utilize d type flip flop to complete collection and the maintenance of anti-phase normalizing code data, and after utilizing d type flip flop output to carry out controllable delay, feedback carries out the adjustment that d type flip flop reset realizes exporting nrz data signal pulse duration.
Pulse width control and normalizing decoding circuit 3 comprise a d type flip flop U5, a delay circuit and not gate U7, delay circuit is programmable delay line U6 in the present embodiment, the D termination high level of d type flip flop U5, clock end CLK meets the anti-phase normalizing code data signal D returning anti-phase normalizing code change-over circuit 2 to export
/ R1, at anti-phase normalizing code data signal D
/ R1when there is high level and rising edge, d type flip flop U5Q holds to export and becomes high level from low level, as d type flip flop U5 reset signal after programmable delay line U6, d type flip flop U5 is exported and resets, become low level from high level, the output that d type flip flop U5Q holds is anti-phase normalizing code data signal D '
r1, change time of delay and the adjustable anti-phase normalizing code data signal D ' of programmable delay line U5
r1pulse duration, its minimum pulse width depends on selected d type flip flop U5 reset delay T
rDwith the minimum delay time T of delay line
dD, within most I reaches 1ns.Anti-phase normalizing code data signal D '
r1after not gate U7 is anti-phase, obtain the normalizing code data signal D of adjustable pulse width
r1, change time of delay and the adjustable normalizing code data signal D of delay circuit
r1pulse duration.Concrete sequential relationship as shown in Figure 3.
It should be noted that, delay circuit not only optional peek control programmable delay line, also can choose the high accuracy controllable delay line that analog level controls in the present invention, or the selection of superposition switch etc.All relevant controlled delay circuits form the NRZ/RZ code converting apparatus of adjustable pulse width, all belong to the present invention.
Like this, NRZ data-signal D to be converted
iNits trigger synchronous circuits 1 is accessed, the NRZ data-signal D after synchronous with system clock CLK
nRZaccess anti-phase normalizing code change-over circuit 2 with system clock CLK, obtain anti-phase normalizing code data signal D
/ R1, after adjust through pulse width control and normalizing code output circuit 3 the nrz data signal D that pulse duration obtains adjustable pulse width
r1, this data rate can more than 1Gbps.
Fig. 3 is the timing waveform of the NRZ/normalizing code converting apparatus of adjustable pulse width shown in Fig. 2.Wherein T
aDfor in NRZ change-over circuit 2 with the transmission delay of door U4, T
pD2for the transmission delay of d type flip flop U5 in pulse width control circuit 3, T
pD2for the transmission delay that not gate U7 in pulse width control circuit 3 is anti-phase.
Although be described the illustrative embodiment of the present invention above; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various change to limit and in the spirit and scope of the present invention determined, these changes are apparent, and all innovation and creation utilizing the present invention to conceive are all at the row of protection in appended claim.
Claims (3)
1. NRZ/normalizing code converting apparatus of adjustable pulse width, is characterized in that, comprising:
One trigger synchronous circuits, for receiving system clock and the NRZ data-signal of data generating apparatus output, being synchronized to system clock by NRZ data-signal, exporting the NRZ data-signal with system clock synchronization;
One anti-phase normalizing code change-over circuit, for the NRZ data-signal that receiving system clock and trigger synchronous circuits export, and NRZ data-signal system clock, trigger synchronous circuits exported is anti-phase, then carries out and computing, obtains anti-phase normalizing code data signal;
Wherein, the time delay T of trigger synchronous circuits
pD1and in anti-phase normalizing code change-over circuit, anti-phase time delay T is carried out to the NRZ data-signal after synchronous
dD1sum is less than T/2+T
cDand T
pD1+ T
dD1>T
cD, T
cDfor carrying out anti-phase time delay to system clock in anti-phase normalizing code change-over circuit, T is system clock cycle; Can ensure so anti-phase after NRZ data-signal high level more anti-phase after system clock high level arrive in advance, realize the conversion of NRZ data-signal to anti-phase normalizing code data signal;
One pulse width control and normalizing code output circuit, pulse width control and normalizing code output circuit comprise a d type flip flop, a delay circuit and a not gate, the D termination high level of d type flip flop, the anti-phase normalizing code data signal that clock termination anti-phase normalizing code change-over circuit exports, when there is high level and rising edge in anti-phase normalizing code data signal, d type flip flop Q holds to export and becomes high level from low level, as d type flip flop reset signal after delay circuit, d type flip flop is exported reset, low level is become from high level, the output that d type flip flop Q holds connects not gate, after not gate is anti-phase, obtain the normalizing code data signal of adjustable pulse width, change the time of delay of delay circuit and the pulse duration of adjustable normalizing code data signal,
Wherein, high level representative data " 1 ", low level representative data " 0 ".
2. NRZ according to claim 1/normalizing code converting apparatus, it is characterized in that, described trigger synchronous circuits adopts d type flip flop to realize, NRZ data-signal connects the D end of d type flip flop, system clock connects the clock end of d type flip flop, and the Q end of d type flip flop is the output of trigger synchronous circuits;
Be high level at NRZ data-signal, and during the arrival of system clock rising edge, export high level, be low level at NRZ data-signal, and during the arrival of system clock rising edge, output low level, NRZ data-signal is synchronized on system clock, obtains the NRZ data-signal synchronously.
3. NRZ according to claim 1/normalizing code converting apparatus, it is characterized in that, described anti-phase normalizing code change-over circuit comprises two not gates and one and door, realize system clock respectively, the anti-phase and system clock of NRZ data-signal that trigger synchronous circuits exports, NRZ data-signal anti-phase after and calculation function.
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| CN201210427557.4A CN102916682B (en) | 2012-10-31 | 2012-10-31 | Pulse width-adjustable NRZ/ R1 (non-return-to-zero/ return-to-1) code converting device |
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| CN201210427557.4A CN102916682B (en) | 2012-10-31 | 2012-10-31 | Pulse width-adjustable NRZ/ R1 (non-return-to-zero/ return-to-1) code converting device |
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| CN102916682B true CN102916682B (en) | 2015-07-15 |
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| CN105072058B (en) * | 2015-08-25 | 2018-05-25 | 许继集团有限公司 | A kind of positive and negative phase coding method of data and data transmission method based on optical fiber transmission |
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| JPS61195017A (en) * | 1985-02-25 | 1986-08-29 | Matsushita Electric Works Ltd | Pulse generator |
| US8299833B2 (en) * | 2010-06-09 | 2012-10-30 | International Business Machines Corporation | Programmable control clock circuit including scan mode |
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| CN1396736A (en) * | 2001-07-11 | 2003-02-12 | 深圳市中兴通讯股份有限公司上海第二研究所 | Coder-decoder for return-to-zero code or mark inverse code |
| CN1536785A (en) * | 2003-04-09 | 2004-10-13 | 华为技术有限公司 | Duty ratio adjustable high-speed optical return-to-zero code generation method and its equipment |
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