CN102904584A - Gray code coding/decoding parallel circuit - Google Patents

Abstract

The invention discloses a Gray code coding/decoding parallel circuit which comprises N either-or selectors and N+1 nonequivalence operation units, wherein an either-or selector and an nonequivalence operation unit form a data selection and operative base unit; the either-or selectors are controlled by a control signal to select input data for the nonequivalence operation units, the Mth either-or selector receives external data and output data of the M+1th nonequivalence operation unit, the either-or selectors are controlled by the control signal to select data so as to output the corresponding nonequivalence operation unit, and M is less than or equal to N; the N+1 nonequivalence operation unit receives external data so as to carry out an nonequivalence operation to output an nonequivalence operation result; and the other nonequivalence operation units receive external data and output data of the respective corresponding either-or selector, and the nonequivalence operation result is output. The Gray code coding decoding parallel circuit provided by the invention has the advantages that the Gray code coding decoding parallel circuit is applied to a half-duplex circuit so as to realize a Gray code coding function or decoding function, and the area and power consumption of a chip are effectively reduced.

Description

A kind of Gray code encoding and decoding parallel circuit

Technical field

The present invention relates to a kind of coding-decoding circuit, particularly relate to a kind of Gray code encoding and decoding parallel circuit.

Background technology

Can only identify 0 and 1 in digital system, various data will be converted to binary code and just can process.Gray code (Gray code) is again cyclic binary code or reflected binary code, and it is a kind of non-weighted code, adopts absolute addressing mode.Typical case's Gray code is a kind of single step self-complementing code with reflection characteristic and cycle characteristics, and the possibility of significant error appears in its circulation, single step characteristic when having eliminated direct access, and its reflection, self-complementary characteristic are so that negate very convenient.Gray code belongs to Reliability codes, is the minimized coded system of a kind of mistake.

Natural binary code can directly convert analog signal to by D/A converter.But in some cases, for example all to become from metric 3 each that convert 4 o'clock binary codes to, make digital circuit produce very large peak current pulse.Gray code does not then have this shortcoming, and it is a kind of numeric sorting system, and the adjacent integer of wherein all only has a numeral different in their numeral.Therefore when it is changed between any two adjacent numbers, only have a numerical digit to change, logic obscures when having reduced widely by a state to next state.In addition because also only a number is different between maximum number and the minimum number, therefore usually be again Gray's reflected code or cyclic code.Based on this characteristic, Gray code is widely used in the circuit such as digital-to-analogue conversion and asynchronous FIFO at present.

Traditional gray code decoder adopts the mode of tabling look-up to realize, along with the increase of Gray code bit wide, its resource overhead that brings is increasing, badly influences area and the power consumption of chip design.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of Gray code encoding and decoding parallel circuit, can realize gray encoding or decode operation under the control of control signal, effectively reduces area and the power consumption of chip.

For solving the problems of the technologies described above Gray code encoding and decoding parallel circuit of the present invention, comprising:

N alternative selector and N+1 XOR unit, alternative selector and an XOR unit form that data are selected and the elementary cell of computing;

Alternative selector suspension control signal is controlled to be the XOR unit and selects the input data, M alternative selector receives the output data of external data and M+1 XOR unit, the alternative selector is selected data and is exported to its corresponding XOR unit, M≤N by control signal control;

XOR unit of N+1 receives external data, carries out XOR and exports the XOR result;

Other XOR unit receives the output data of external data and the self-corresponding alternative selector of Qi Ge, carries out XOR and exports the XOR result.

The bit wide of described circuit input data and output data is the S bit, and the pass of data bit width S and alternative selector number N is: S=N+2.

In traditional circuit, sending data path needs a gray encoding circuit, and the receive data path needs a gray code decoder circuit; Gray code encoding and decoding parallel circuit of the present invention is under the control of control signal, can carry out the gray encoding computing, can carry out the gray code decoder computing again, when being applied to half-duplex circuit, can substitute the gray encoding circuit of transmission data path and the gray code decoder circuit of receive data path, can save resources of chip, reduce area and the power consumption of chip.

Description of drawings

Fig. 1 is one embodiment of the invention structural representations

Description of reference numerals

XOR0 is that first XOR unit XOR1 is second XOR unit

XOR2 is that the 3rd XOR unit XOR3 is the 4th XOR unit

XOR4 is that the 5th XOR unit XOR5 is the 6th XOR unit

XOR6 is that the 7th XOR unit MUX0 is first alternative selector

MUX1 is that second alternative selector MUX2 is the 3rd alternative selector

MUX3 is that the 4th alternative selector MUX4 is the 5th alternative selector

MUX5 is the 6th alternative selector.

Embodiment

As shown in Figure 1, one embodiment of the invention comprise: seven XOR unit, be numbered XOR0 to XOR6, and six alternative selectors are numbered MUX0 to MUX5.Seven XOR unit receive the eight bit data of outside input, carry out simultaneously XOR and produce operation result.During work, with the data din[7:0 of outside input] respectively step-by-step be input to different XOR XOR unit.Wherein, din[0] expression din[7:0] in the 1st bit data, din[1] expression din[7:0] in the 2nd bit data, din[2] expression din[7:0] in the 3rd bit data, din[3] expression din[7:0] in the 4th bit data, din[4] expression din[7:0] in the 5th bit data, din[5] expression din[7:0] in the 6th bit data, din[6] expression din[7:0] in the 7th bit data, din[7] expression din[7:0] in the 8th bit data.Carry out XOR by the data that each self-corresponding alternative selector with it is exported, produce current this Output rusults, and pass through dout[7:0] output.Wherein, dout[0] expression dout[7:0] in the 1st bit data, dout[1] expression dout[7:0] in the 2nd bit data, dout[2] expression dout[7:0] in the 3rd bit data, dout[3] expression dout[7:0] in the 4th bit data, dout[4] expression dout[7:0] in the 5th bit data, dout[5] expression dout[7:0] in the 6th bit data, dout[6] expression dout[7:0] in the 7th bit data, dout[7] expression dout[7:0] in the 8th bit data.

When control signal (encode_decode) is true time, circuit carries out the gray encoding computing, at this moment, first alternative selector MUX0 selects the second din[1 of outer input data] export to first XOR unit XOR0, second alternative selector MUX1 selects the 3rd din[2 of outer input data] export to second XOR unit XOR1, the 3rd alternative selector MUX2 selects the 4th din[3 of outer input data] export to the 3rd XOR unit XOR2, the 4th alternative selector MUX3 selects the 5th din[4 of outer input data] export to the 4th XOR unit XOR3, the 5th alternative selector MUX4 selects the 6th din[5 of outer input data] export to the 5th XOR unit XOR4, the 6th alternative selector MUX5 selection is the 7th din[6 of outer input data] export to the 6th XOR unit XOR5;

When control signal (encode_decode) is fictitious time, circuit carries out the gray code decoder computing, at this moment, first alternative selector MUX0 selects second XOR unit XOR1 output data exported to first XOR unit XOR0, second alternative selector MUX1 selects the 3rd XOR unit XOR2 output data are exported to second XOR unit XOR1, the 3rd alternative selector MUX2 selects the 4th XOR unit XOR3 output data are exported to the 3rd XOR unit XOR2, the 4th alternative selector MUX3 selects the 5th XOR unit XOR4 output data are exported to the 4th XOR unit XOR3, the 5th alternative selector MUX4 selects the 6th XOR unit XOR5 output data are exported to the 5th XOR unit XOR4, and the 6th alternative selector MUX5 selects the 7th XOR unit XOR6 output data are exported to the 6th XOR unit XOR5.

Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (2)

1. Gray code encoding and decoding parallel circuit comprises:

N alternative selector and N+1 XOR unit, alternative selector and an XOR unit form that data are selected and the elementary cell of computing;

Alternative selector suspension control signal is controlled to be the XOR unit and selects the input data, M alternative selector receives the output data of external data and M+1 XOR unit, the alternative selector is selected data and is exported to its corresponding XOR unit, M≤N by control signal control;

N+1 XOR unit receives external data, carries out XOR and exports the XOR result;

Other XOR unit receives the output data of external data and the self-corresponding alternative selector of Qi Ge, carries out XOR and exports the XOR result.

2. parallel circuit as claimed in claim 1 is characterized in that: the bit wide of input data and output data is the S bit, and the pass of data bit width S and alternative selector number N is: S=N+2.

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