CN102904577A - NRZI (non-return-to-zero inverse) encoding and decoding parallel circuit - Google Patents
NRZI (non-return-to-zero inverse) encoding and decoding parallel circuit Download PDFInfo
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- CN102904577A CN102904577A CN2011102111132A CN201110211113A CN102904577A CN 102904577 A CN102904577 A CN 102904577A CN 2011102111132 A CN2011102111132 A CN 2011102111132A CN 201110211113 A CN201110211113 A CN 201110211113A CN 102904577 A CN102904577 A CN 102904577A
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Abstract
The invention discloses an NRZI (non-return-to-zero inverse) encoding and decoding parallel circuit which comprises N+1 alternative selectors and N inclusive-or operation units. The first alternative selector is controlled by a synchronous signal, receives an initial value of an NRZI encoding and decoding circuit and output data of the (N+1)th alternative selector, and outputs data to the first inclusive-or operation unit. The output data, which are selected under control of a control signal, of the (N+1)th alternative selector are directly output to the first alternative selector. The Mth alternative selector receives external data and output data of the (M-1)th inclusive-or operation unit, is controlled by the control signal to select output data, and then outputs the data to the corresponding inclusive-or operation units, wherein the M is not larger than N. The inclusive-or operation units receive the external data and the output data of the corresponding alternative selectors to perform inclusive-or operation and then output operation results. When the NRZI encoding and decoding parallel circuit is applied to a half-duplex circuit, NRZI encoding and decoding functions can be realized and power consumption of the circuit can be reduced effectively.
Description
Technical field
The present invention relates to a kind of coding-decoding circuit, particularly relate to a kind of NRZI encoding and decoding parallel circuit.
Background technology
Along with the development of electronic technology, USB device is widely used in the daily life.The USB technology adopts universal serial bus, and data transmit by turn successively.Transfer of data adopts NRZI (NonReturn to Zero Invert, oppositely non-return-to-zero) coded system in the USB system, and this coded system can guarantee the integrality that data transmit, and not needing again independently, clock signal and data send together.Nrzi encoding data flow generation saltus step when running into 0 level signal, and remain unchanged when running into 1 level signal.Saltus step in the data flow can keep synchronously with the data of receiving decoder, thereby independently clock signal needn't be provided.
In most cases, nrzi encoding fill to use with the position, because a lot of continuous 1 will cause without the level saltus step, thereby causes the final missed synchronization of receiver, and solution is to adopt a position filling technique.Namely in the situation of six 1 of continuous transmission, fill one 0, so that in the nrzi encoding data flow saltus step occurs, this just guarantees that receiver can detect a saltus step at least within per seven time interval from data flow, thereby the data of receiver and transmission are kept synchronously.UTMI (USB2.0 Transceiver Macrocell Interface) transmitting terminal is responsible for inserting in the data flow before nrzi encoding 0 level, i.e. filler operation; The UTMI receiving terminal must be in the decoded data of NRZI, after six continuous 1 level occurring, thereafter 0 level are abandoned the extraction operation of ascending the throne to extracting.If in the data that receive, six 1 continuous heels with be not 0 but 1, then produce mistake, produce error signal.
Traditional NRZI encoding and decoding adopt serial design to realize, because under the fast mode, the data transfer rate of USB is 480Mbps, when serial process NRZI decode operation, the work clock that needs is 480MHz, has greatly increased circuit power consumption.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of NRZI encoding and decoding parallel circuit, can realize the NRZI coding-decoding operation, effectively reduces circuit power consumption.
For solving the problems of the technologies described above, NRZI encoding and decoding parallel circuit of the present invention comprises:
N+1 alternative selector and N with the exclusive disjunction unit, and wherein, alternative selector and one form with the exclusive disjunction unit that data are selected and the elementary cell of computing;
First alternative selector is controlled by synchronizing signal, receives the initial value of NRZI coding-decoding circuit and the output data of N+1 alternative selector, and the output data give first with the exclusive disjunction unit;
The output data of N+1 alternative selector suspension control signal control selection directly output to first alternative selector;
M alternative selector receives external data and M-1 the output data with the exclusive disjunction unit, and suspension control signal control selects the output data, outputs to that each is self-corresponding with exclusive disjunction unit, M≤N;
With the exclusive disjunction unit, receive the output data of external data and the self-corresponding alternative selector of Qi Ge, carry out with exclusive disjunction and export operation result.
The bit wide of described circuit input data and output data is the S bit, and data bit width S is S=N with pass with exclusive disjunction unit number N.
In traditional circuit, sending data path needs a nrzi encoding circuit, and the receive data path needs a NRZI decoding circuit; NRZI encoding and decoding parallel circuit provided by the invention is under the control of control signal, can carry out the nrzi encoding computing, can carry out again NRZI decoding computing, when being applied to half-duplex circuit, can substitute the nrzi encoding circuit of transmission data path and the NRZI decoding circuit of receive data path, can save resources of chip, reduce circuit power consumption.
Description of drawings
Fig. 1 is the schematic diagram of NRZI encoding and decoding parallel circuit one embodiment of the present invention
Reference numeral
MUX0 is that first alternative selector MUX1 is second alternative selector
MUX2 is that the 3rd alternative selector MUX3 is the 4th alternative selector
MUX4 is that the 5th alternative selector MUX5 is the 6th alternative selector
MUX6 is that the 7th alternative selector MUX7 is the 8th alternative selector
MUX8 is that the 9th alternative selector XNOR0 is that first is with the exclusive disjunction unit
XNOR1 be second with exclusive disjunction unit XNOR2 be the 3rd with the exclusive disjunction unit
XNOR3 be the 4th with exclusive disjunction unit XNOR4 be the 5th with the exclusive disjunction unit
XNOR5 be the 6th with exclusive disjunction unit XNOR6 be the 7th with the exclusive disjunction unit
XNOR7 be the 8th with the exclusive disjunction unit.
Embodiment
As shown in Figure 1, in one embodiment of the invention, NRZI encoding and decoding parallel circuit comprises: eight same or XNOR arithmetic elements are numbered XNOR0 to XNOR7; Nine alternative selectors are numbered MUX0 to MUX8.
The initial value (ini_value) of first alternative selector MUX0 input NRZI decoding computing under the control of synchronous (sync) signal, other eight alternative selectors are selected the input data under the control of control (encode_decode) signal, eight with exclusive disjunction unit (XNOR) sampling outer input data and its output data of corresponding alternative selector separately, carry out with exclusive disjunction and export operation result.
When the transmission of data and signal was arranged, circuit at first judged by synchronous (sync) signal whether the data of current this byte are the first byte data.(sync) data bit width is 1 bit synchronously, represents whether current this byte data is the data that need carry out the NRZI decoding.Initially (ini_value) data bit width is 1 bit, and expression begins to carry out the initial value of NRZI decoding, is 1 ' b1 or 1 ' b0 according to concrete application settings.Input data (din) bit wide is 8 bits, and expression need be carried out the input data of NRZI decoding; Output data (dout) bit wide is 8 bits, and expression is through the decoded Output rusults of NRZI.
If synchrodata is true time, the data that show current this byte are first byte datas in current these bag data, and the primary data (in_value) that sets in advance or the outside is inputted is input to together or the XNOR0 arithmetic element by the alternative selector; Otherwise the data that then show current this byte are not the first byte datas, and the operation result of the 9th the alternative selector in last cycle is input to together or the XNOR0 arithmetic element by the alternative selector.
Meanwhile, the parallel data din[7:0 of outside input] respectively step-by-step be input to different same or XNOR arithmetic elements, wherein, din[0] expression din[7:0] in the 1st bit data, din[1] expression din[7:0] in the 2nd bit data, din[2] expression din[7:0] in the 3rd bit data, din[3] expression din[7:0] in the 4th bit data, din[4] expression din[7:0] in the 5th bit data, din[5] expression din[7:0] in the 6th bit data, din[6] expression din[7:0] in the 7th bit data, din[7] expression din[7:0] in the 8th bit data.
By produce current this Output rusults with exclusive disjunction, pass through dout[7:0] output is out; Dout[0 wherein] expression dout[7:0] in the 1st bit data, dout[1] expression dout[7:0] in the 2nd bit data, dout[2] expression dout[7:0] in the 3rd bit data, dout[3] expression dout[7:0] in the 4th bit data, dout[4] expression dout[7:0] in the 5th bit data, dout[5] expression dout[7:0] in the 6th bit data, dout[6] expression dout[7:0] in the 7th bit data, dout[7] expression dout[7:0] in the 8th bit data.
Judge that by control signal (encode_decode) current what do is nrzi encoding operation or NRZI decode operation;
When control signal (encode_decode) is true time, circuit carries out nrzi encoding work, at this moment, second alternative selector MUX1 selects first output data dout[0 with exclusive disjunction unit XNOR0] export to second with exclusive disjunction unit XNOR1, the 3rd alternative selector MUX2 selects second output data dout[1 with exclusive disjunction unit XNOR1] export to the 3rd with exclusive disjunction unit XNOR2, the 4th alternative selector MUX3 selects the 3rd the output data dout[2 with exclusive disjunction unit XNOR2] export to the 4th with exclusive disjunction unit XNOR3, the 5th alternative selector MUX4 selects the 4th the output data dout[3 with exclusive disjunction unit XNOR3] export to the 5th with exclusive disjunction unit XNOR4, the 6th alternative selector MUX5 selects the 5th the output data dout[4 with exclusive disjunction unit XNOR4] export to the 6th with exclusive disjunction unit XNOR5, the 7th alternative selector MUX6 selects the 6th the output data dout[5 with exclusive disjunction unit XNOR5] export to the 7th with exclusive disjunction unit XNOR6, the 8th alternative selector MUX7 selects the 7th the output data dout[6 with exclusive disjunction unit XNOR6] export to the 8th with exclusive disjunction unit XNOR7, the 9th alternative selector MUX8 selection is the 8th the output data dout[7 with exclusive disjunction unit XNOR7] export to first alternative selector MUX0;
When control signal (encode_decode) is fictitious time, circuit carries out NRZI decoding work, at this moment, second alternative selector MUX1 selects first din[0 of outer input data] export to second with exclusive disjunction unit XNOR1, the 3rd alternative selector MUX2 selects first din[1 of outer input data] export to the 3rd with exclusive disjunction unit XNOR2, the 4th alternative selector MUX3 selects first din[2 of outer input data] export to the 4th with exclusive disjunction unit XNOR3, the 5th alternative selector MUX4 selects first din[3 of outer input data] export to the 5th with exclusive disjunction unit XNOR4, the 6th alternative selector MUX5 selects first din[4 of outer input data] export to the 6th with exclusive disjunction unit XNOR5, the 7th alternative selector MUX6 selects first din[5 of outer input data] export to the 7th with exclusive disjunction unit XNOR6, the 8th alternative selector MUX7 selects first din[6 of outer input data] export to the 8th with exclusive disjunction unit XNOR7, the 9th alternative selector MUX8 selection is first din[7 of outer input data] export to first alternative selector MUX0.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (2)
1. NRXI encoding and decoding parallel circuit comprises:
N+1 alternative selector and N with the exclusive disjunction unit, and alternative selector and one form with the exclusive disjunction unit that data are selected and the elementary cell of computing;
First alternative selector is controlled by synchronizing signal, receives the initial value of NRZI coding-decoding circuit and the output data of N+1 alternative selector, and the output data give first with the exclusive disjunction unit;
The output data of N+1 alternative selector suspension control signal control selection directly output to first alternative selector;
M alternative selector receives external data and M-1 the output data with the exclusive disjunction unit, and suspension control signal control selects the output data, outputs to that each is self-corresponding with exclusive disjunction unit, M≤N;
With the exclusive disjunction unit, receive the output data of external data and the self-corresponding alternative selector of Qi Ge, carry out with exclusive disjunction and export operation result.
2. parallel circuit as claimed in claim 1 is characterized in that: the bit wide of input data and output data is the S bit, and data bit width S is S=N with pass with exclusive disjunction unit number N.
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| CN2011102111132A CN102904577A (en) | 2011-07-26 | 2011-07-26 | NRZI (non-return-to-zero inverse) encoding and decoding parallel circuit |
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| CN2011102111132A CN102904577A (en) | 2011-07-26 | 2011-07-26 | NRZI (non-return-to-zero inverse) encoding and decoding parallel circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1144378A (en) * | 1994-10-31 | 1997-03-05 | 三星电子株式会社 | Digital signal recording equipment |
| US5790058A (en) * | 1995-11-13 | 1998-08-04 | Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A. | Serializing-parallelizing circuit for high speed digital signals |
| CN1320865A (en) * | 2000-03-16 | 2001-11-07 | 精工爱普生株式会社 | Data transmission controlling device and electronic apparatus |
| CN101867430A (en) * | 2010-06-21 | 2010-10-20 | 苏州橙芯微电子科技有限公司 | Multiplexing/Demultiplexing Architecture for Low Power Serial Data Transmission |
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2011
- 2011-07-26 CN CN2011102111132A patent/CN102904577A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1144378A (en) * | 1994-10-31 | 1997-03-05 | 三星电子株式会社 | Digital signal recording equipment |
| US5790058A (en) * | 1995-11-13 | 1998-08-04 | Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A. | Serializing-parallelizing circuit for high speed digital signals |
| CN1320865A (en) * | 2000-03-16 | 2001-11-07 | 精工爱普生株式会社 | Data transmission controlling device and electronic apparatus |
| CN101867430A (en) * | 2010-06-21 | 2010-10-20 | 苏州橙芯微电子科技有限公司 | Multiplexing/Demultiplexing Architecture for Low Power Serial Data Transmission |
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Application publication date: 20130130 |