CN102684702A - Concurrent design circuit for NRZI (Non Return To Zero Inverse) code - Google Patents
Concurrent design circuit for NRZI (Non Return To Zero Inverse) code Download PDFInfo
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- CN102684702A CN102684702A CN2011100617173A CN201110061717A CN102684702A CN 102684702 A CN102684702 A CN 102684702A CN 2011100617173 A CN2011100617173 A CN 2011100617173A CN 201110061717 A CN201110061717 A CN 201110061717A CN 102684702 A CN102684702 A CN 102684702A
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Abstract
The invention provides a concurrent design circuit for a NRZI (Non Return To Zero Inverse) code. The concurrent design circuit comprises an alternative selector and eight XNOR operation units, wherein an input bit width is 8 bits; an initial value of an NRZI code operation is inputted by the alternative selector under the control of a synchronous signal sync; and the eight XNOR operation units are used for sampling the externally inputted eight-bit data, simultaneously performing XNOR operation and generating an operating result. According to the technical scheme provided by the invention, the work clock frequency of the circuit is reduced while the power consumption of the circuit is effectively reduced.
Description
Technical field
The present invention relates to a kind of nrzi encoding circuit, relate in particular to a kind of NRZI concurrent designing circuit.
Background technology
Along with development of electronic technology, USB device is widely used in the daily life.The USB technology adopts universal serial bus, and data transmit by turn successively.Transfer of data adopts reverse non-return-to-zero (Non Return to Zero Invert, be called for short " NRZI ") coded system in the USB system, and this coded system can guarantee the integrality that data transmit, and does not need again that independently clock signal and data are sent together.Nrzi encoding data flow generation saltus step when running into 0 level signal, and remain unchanged when running into 1 level signal.Saltus step in the data flow can keep synchronously decoder with the data of receiving, thereby independently clock signal needn't be provided.
In most cases, nrzi encoding fill to use with the position, because a lot of continuous 1 will cause not having the level saltus step, thereby causes the final missed synchronization of receiver, and solution is to adopt a position filling technique.Promptly under the situation of six 1 of continuous transmission, fill one 0; Make and saltus step takes place in the nrzi encoding data flow; This just guarantees that receiver can detect a saltus step at least in per seven time interval from data flow, thereby the data of receiver and transmission are kept synchronously.UTMI (USB2.0 Transceiver Macrocell Interface) transmitting terminal is responsible for inserting in the data flow before nrzi encoding one 0 level, i.e. filler operation; The UTMI receiving terminal must be in the decoded data of NRZI, after six continuous 1 level occurring, abandon the extraction operation of ascending the throne to thereafter one 0 level to extracting.If after six continuous 1, what follow is not 0 but 1, then produces mistake, produces error signal.
Traditional nrzi encoding adopts serial to design and realizes, because under the fast mode, the data transfer rate of USB is 480Mbps, when the serial process nrzi encoding was operated, the work clock that needs was 480MHz, has greatly increased the power consumption of circuit.For effectively reducing circuit power consumption, the present invention aims to provide a kind of parallel design method, reduces power consumption and can satisfy circuit requirements simultaneously.
Summary of the invention
The object of the invention provides a kind of concurrent designing circuit of nrzi encoding, is made up of with the exclusive disjunction unit combination alternative selector and a plurality of.Technical scheme of the present invention when reducing clock frequency, can effectively significantly reduce the power consumption of circuit, satisfies application demand.
A kind of concurrent designing circuit of nrzi encoding is made up of with the exclusive disjunction unit alternative selector and a plurality of.
The alternative selector is selected output valve according to the Different control signal;
With the exclusive disjunction unit, constitute with the exclusive disjunction unit by a plurality of, be used to carry out same exclusive disjunction;
The present invention adopts an alternative selector and eight with the exclusive disjunction unit, and the input bit wide is 8 bits.The alternative selector is imported the initial value of nrzi encoding computing under the control of synchronizing signal sync, eight eight bit data with the outside input of exclusive disjunction form unit sampling are carried out with exclusive disjunction simultaneously and produced operation result.Entire circuit is made up of each combinational circuit, and the data of parallel transmission can be accomplished computing simultaneously, and the output result.
Through content provided by the invention, when in the traditional circuit design, adopting high-speed transfer, its clock frequency can reduce by 1/8, and can reduce the power consumption in the circuit largely.
Description of drawings
The concurrent designing circuit structure diagram of Fig. 1 nrzi encoding provided by the invention
Embodiment
Below in conjunction with accompanying drawing, the content that the present invention proposes is carried out detailed description.
Fig. 1 has provided the basic block diagram of the concurrent designing circuit of nrzi encoding; As figure shown in, eight with or the XNOR arithmetic element be respectively with or XNOR0, with or XNOR1, with or XNOR2, with or XNOR3, with or XNOR4, with or XNOR5, with or XNOR6 and with or XNOR7.Alternative selector MUX imports the initial value of nrzi encoding computing under the control of synchronizing signal sync, by eight with or the eight bit data of the outside input of XNOR arithmetic element sampling, carry out with exclusive disjunction simultaneously and produce operation result.
When data and signal input, circuit at first judges through synchronizing signal sync whether the data of current this byte are first byte data.If sync is 1 ' b1; The data that then show current this byte are first byte datas; Be input to the initial value that is provided with in advance or the outside is imported together or the XNOR0 unit; If not, the data that then show current this byte are not first byte datas, are input to last cycle operation result dout7 together or the XNOR0 unit.Meanwhile, the parallel data din [7:0] of outside input respectively step-by-step be input to different same or XNOR unit.Wherein, din0 representes the 1st bit data among the din [7:0], and din1 representes the 2nd bit data among the din [7:0]; Din2 representes the 3rd bit data among the din [7:0]; Din3 representes the 4th bit data among the din [7:0], and din4 representes the 5th bit data among the din [7:0], and din5 representes the 6th bit data among the din [7:0]; Din6 representes the 7th bit data among the din [7:0], and din7 representes the 8th bit data among the din [7:0]; Output result through with last position carries out same exclusive disjunction, produces current this output result, and through dout [7:0] output.Wherein dout7 feeds back to alternative selector MUX, being used for doing nrzi encoding computing next time, thereby makes parallel data can accomplish computing and produce output result simultaneously; Wherein, dout0 representes the 1st bit data among the dout [7:0], and dout1 representes the 2nd bit data among the dout [7:0]; Dout2 representes the 3rd bit data among the dout [7:0]; Dout3 representes the 4th bit data among the dout [7:0], and dout4 representes the 5th bit data among the dout [7:0], and dout5 representes the 6th bit data among the dout [7:0]; Dout6 representes the 7th bit data among the dout [7:0], and dout7 representes the 8th bit data among the dout [7:0].
Claims (4)
1. the concurrent designing circuit of a nrzi encoding is characterized in that said circuit is made up of with the exclusive disjunction unit alternative selector and a plurality of.
2. the concurrent designing circuit of a kind of nrzi encoding as claimed in claim 1 is characterized in that said circuit input bit wide is eight bits, is eight with the exclusive disjunction unit.
3. according to claim 1 or claim 2 a kind of concurrent designing circuit of nrzi encoding is characterized in that said eight eight bit data with the outside input of exclusive disjunction unit sampling, carries out with exclusive disjunction simultaneously and produces operation result.
4. the concurrent designing circuit of a kind of nrzi encoding as claimed in claim 1 is characterized in that the initial value of said alternative selector through synchronizing signal control input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100617173A CN102684702A (en) | 2011-03-15 | 2011-03-15 | Concurrent design circuit for NRZI (Non Return To Zero Inverse) code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100617173A CN102684702A (en) | 2011-03-15 | 2011-03-15 | Concurrent design circuit for NRZI (Non Return To Zero Inverse) code |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102684702A true CN102684702A (en) | 2012-09-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100617173A Pending CN102684702A (en) | 2011-03-15 | 2011-03-15 | Concurrent design circuit for NRZI (Non Return To Zero Inverse) code |
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| CN (1) | CN102684702A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5790058A (en) * | 1995-11-13 | 1998-08-04 | Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A. | Serializing-parallelizing circuit for high speed digital signals |
| CN1320865A (en) * | 2000-03-16 | 2001-11-07 | 精工爱普生株式会社 | Data transmission controlling device and electronic apparatus |
| CN101867430A (en) * | 2010-06-21 | 2010-10-20 | 苏州橙芯微电子科技有限公司 | Multiplexing/demultiplexing structure for serial data transmission of low power consumption |
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2011
- 2011-03-15 CN CN2011100617173A patent/CN102684702A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5790058A (en) * | 1995-11-13 | 1998-08-04 | Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A. | Serializing-parallelizing circuit for high speed digital signals |
| CN1320865A (en) * | 2000-03-16 | 2001-11-07 | 精工爱普生株式会社 | Data transmission controlling device and electronic apparatus |
| CN101867430A (en) * | 2010-06-21 | 2010-10-20 | 苏州橙芯微电子科技有限公司 | Multiplexing/demultiplexing structure for serial data transmission of low power consumption |
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Application publication date: 20120919 |