CN102903611A - Metal-dielectric-metal capacitor and manufacturing method thereof - Google Patents
Metal-dielectric-metal capacitor and manufacturing method thereof Download PDFInfo
- Publication number
- CN102903611A CN102903611A CN2012103495632A CN201210349563A CN102903611A CN 102903611 A CN102903611 A CN 102903611A CN 2012103495632 A CN2012103495632 A CN 2012103495632A CN 201210349563 A CN201210349563 A CN 201210349563A CN 102903611 A CN102903611 A CN 102903611A
- Authority
- CN
- China
- Prior art keywords
- metal
- medium layer
- dielectric
- dielectric layer
- layer pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a metal-dielectric-metal capacitor and a manufacturing method thereof. Through the capacitor and the manufacturing method thereof provided by the invention, capacitance of a dielectric layer with a higher dielectric constant can be integrated into a subsequent interconnection technology which adopts a dielectric with a conventional or lower dielectric constant so that the RC parasitic delay of metal wiring cannot be affected or reduced simultaneously when improving the area utilization rate and electric capacity of the capacitor in large-capacity integration of capacitance.
Description
Technical field
The invention belongs to integrated circuit fields, be specifically related to a kind of metal-dielectric-metal capacitance and manufacture method thereof.
Background technology
In integrated circuit, electric capacity is widely used as electronic devices and components unit commonly used.Usually, in semiconductor integrated circuit, integrated capacitance and transistor circuit are produced on the same chip.At present, the capacitive form that extensively adopts in the chip comprises metal-dielectric-metal capacitance.
Traditional metal-dielectric-metal capacitance, can adopt at same metal level and insert finger, and utilize mode larger electric capacity of making capacity on the area of less of multiple layer metal layer laminate, therefore the designer more favors this class electric capacity when the large capacity integrated capacitance of design.
This above-mentioned class electric capacity has utilized the layer inner medium layer electric capacity (also claiming sidewall capacitance) of same metal level and the inter-level dielectric layer capacitance (also claiming layer capacitance) of upper/lower layer metallic layer simultaneously, has improved widely area utilization and capacitance.Wherein the electric capacity of the former generation is directly proportional with a dielectric constant (dielectric constant is called for short the k value), the metal level degree of depth and the metal polar plate length (for example every finger length of finger-like pole plate) of medium in the layer, is inversely proportional to the metal polar plate spacing; The electric capacity that the latter produces is directly proportional with the k value of interlayer dielectric layer, the overlapping area of upper/lower layer metallic pole plate, is inversely proportional to the thickness of interlayer dielectric layer.
In same metal level, the dielectric constant k value that improves medium is to improve one of the area utilization of electric capacity and method of capacitance.
Yet, in the subsequent interconnection technique of the chip manufacturing of routine, be that the parasitic RC that reduces metal connecting line postpones, the k value of rear road metal level medium generally should not be too high; Particularly in the high-order processing procedure, the parasitic RC that adopts low-k (low-k) dielectric layer to reduce metal connecting line in the rear road metal level postpones.
Therefore, how can reduce or not increase parasitic RC and postpone in the area utilization and capacitance that improve electric capacity, be that those skilled in the art want the technical problem that solves always.
Summary of the invention
The invention provides a kind of manufacture method of metal-dielectric-metal capacitance, it comprise substrate is provided and after making one deck at least on the substrate step of metal level unit, road,
Metal level unit, described rear road comprises metal connecting line zone and capacitor regions; Described capacitor regions has the capacitance structure of metal-dielectric-metal;
The manufacturing process of metal level unit, described rear road comprises following steps:
On substrate, deposition first medium layer;
Define the first medium layer pattern at formed body structure surface, and etch away the first medium layer of described first medium layer pattern other All Rangeses in addition by the first etching technics;
Formed body structure surface deposition second medium layer behind described the first etching technics;
Define the second medium layer pattern at formed body structure surface, and etch away described first medium layer pattern and second medium layer pattern second medium layer in addition by the second etching technics;
Formed body structure surface depositing metal layers behind described the second etching technics again;
In metal level unit, described rear road: described first medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described second medium layer pattern is the figure of the dielectric layer in described metal connecting line zone; Perhaps, described second medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described first medium layer pattern is the figure of the dielectric layer in described metal connecting line zone;
The dielectric layer of described capacitor regions adopts the material of High-K; The dielectric layer in described metal connecting line zone adopts the material of Low-K.
By manufacture method of the present invention, electric capacity with dielectric layer of high dielectric constant can be integrated into and adopt in conventional or the subsequent interconnection technique than medium with low dielectric constant, thereby when can be implemented in large capacity integrated capacitance, in the time of the area utilization of raising electric capacity and capacitance, do not affect or reduce the RC stray delay of metal connecting line.
Metal-dielectric-the metal capacitance that adopts above-mentioned manufacture method to obtain, in metal level unit, rear road, adopted the material with high dielectric constant in the dielectric layer of capacitor regions, area utilization and the capacitance of electric capacity have been improved, and the dielectric layer in metal connecting line zone adopts conventional or than the material of low-k, do not affect or reduces the parasitic RC delay in metal connecting line zone.
Described metal-dielectric-metal capacitance, its medium also claims dielectric, can adopt the dielectric that can be used in electric capacity well-known to those skilled in the art, such as insulator or semiconductor etc.; Oxide or the nitride that preferably can be used for more specifically, electric capacity; Wherein said metal can adopt the metallics that can be used in electric capacity well-known to those skilled in the art, the preferably copper metal.
Described metal-dielectric-metal capacitance, it can only comprise layer of metal layer unit, also can be multiple layer metal layer element stack structure.
The capacitance structure of metal-dielectric-metal can adopt all kinds well-known to those skilled in the art, such as plate, finger-inserting type etc.Preferred employing can take full advantage of the structure type of sidewall capacitance.In a specific embodiment of the present invention, capacitance structure adopts finger-inserting type.The preferred better type of capacitance structure symmetry that adopts can reduce parasitic RC and postpone.In addition, for improving area utilization and the capacitance of electric capacity, the dielectric layer of all capacitor regions of described metal-dielectric-metal capacitance all adopts the higher material of dielectric constant.
The laminated construction of described metal level unit also can adopt all kinds well-known to those skilled in the art.Preferred employing can take full advantage of the structure type of layer capacitance.Identical and the alignment in metal polar plate zone of preferred adjacent metal unit.
In described metal-dielectric-metal capacitance, it comprises one or more layers rear metal level unit, road, and metal level unit, described rear road comprises metal connecting line zone and capacitor regions.In one embodiment, the metal level unit, rear road of the superiors has comprised capacitor regions and metal connecting line zone simultaneously.
Described substrate can be the substrate that the surface has formed semiconductor device layer; Described substrate also can be formed after described substrate surface has been made at least one deck metal level unit.
The operation of described deposition first medium layer and second medium layer can be adopted method well-known to those skilled in the art, for example adopts the method for gas ions enhanced chemical vapor deposition (PECVD) or ald (ALD) or spin coating.
After the described electroless copper deposition operation, can adopt method well-known to those skilled in the art to make the flattening surface that forms after the electroless copper deposition operation, for example adopt the method for chemico-mechanical polishing to grind the surface that forms after the electroless copper deposition operation.
The described first medium layer pattern that defines can adopt method well-known to those skilled in the art.In one embodiment, adopt photoetching process to define the first medium layer pattern at the body structure surface that forms, particularly, spin coating photoresist on first medium layer surface, photoetching forms the first medium layer pattern.
Etch away the first medium layer of described first medium layer pattern other All Rangeses in addition by the first follow-up etching technics.
The described second medium layer pattern that defines can adopt method well-known to those skilled in the art.In one embodiment of the invention, adopt photoetching process to define the second medium layer pattern at the body structure surface that forms, particularly, spin coating photoresist on second medium layer surface, photoetching forms the second medium layer pattern, and after defining the second medium layer pattern or simultaneously, described first medium layer pattern is carried out lithography alignment.
Etch away the second medium layer of other All Rangeses beyond described first medium layer pattern and the second medium layer pattern by the second etching technics, formed the medium groove.
Formed body structure surface depositing metal layers behind described the second etching technics again.In a specific embodiments, behind described the second etching technics, fill metal in the formed groove, can adopt method well-known to those skilled in the art to fill, the mode of for example electroplating.
In addition, the medium groove in the first medium layer pattern can be filled different metals with the medium groove in the second medium layer pattern.In a specific embodiment, adopt the mode of electroplating behind described the second etching technics, all to fill the copper metal in the formed groove.
In a specific embodiments, in metal level unit, described rear road: described first medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described second medium layer pattern is the figure of the dielectric layer in described metal connecting line zone; That is, the dielectric layer in first deposited capacitances zone, behind the first etching technics, the dielectric layer in plated metal line zone again.The dielectric layer of described capacitor regions adopts k value greater than 7 high-k material, and namely the first first medium layer of deposition employing k value is greater than 7 high-k material; The dielectric layer in described metal connecting line zone (namely after deposition second medium layer) adopts the k value less than 4 material, and for example conventional media (the k value is about 3.9) or low-k(k value are less than 3) material.
In another embodiment, in metal level unit, described rear road: the second medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described first medium layer pattern is the figure of the dielectric layer in described metal connecting line zone; Namely, the dielectric layer in elder generation plated metal line zone, behind the first etching technics, the dielectric layer in deposited capacitances zone again, the dielectric layer of described capacitor regions adopts the k value greater than 7 high-k material, the second medium layer of deposition adopts k value greater than the medium of 7 high-k material namely, and the dielectric layer in described metal connecting line zone (namely first the first medium layer of deposition) employing k value is less than 4 material, and for example conventional media (the k value is about 3.9) or low-k(k value are less than 3) material.
Therein in specific embodiments, the dielectric layer of described capacitor regions adopts the k value greater than the material of 7 high-k, such as Al
2O
3(k ~ 9), Si
3N
4(k ~ 7.8), ZrO
2(k ~ 25), TiO
2In (k ~ 80) any one.Therein in preferred embodiment, it is 9 Al that the dielectric layer of its capacitor regions adopts dielectric constant
2O
3Material.In a further preferred embodiment, the dielectric layer of described capacitor regions all adopts the material of the larger oxide material of k value, and is preferred, and the employing dielectric constant is 80 TiO
2Material.
In a specific embodiments, all capacitor regions in the metal-dielectric-metal capacitance of manufacturing all adopt the k value greater than the material of 7 high-k.
In specific embodiments, the described capacitor cell that also includes the metal connecting line zone, the dielectric layer in its metal connecting line zone adopt conventional media (the k value is about 3.9) or low-k(k value less than 3 therein) material of material.In preferred embodiment, the dielectric layer in its metal connecting line zone adopts the earth silicon material of k value about 3.9 therein.In another embodiment, the described capacitor cell that also includes the metal connecting line zone, the dielectric layer in its metal connecting line zone adopt the k value to be about 2.4 the amorphous carbon of fluoridizing.
In a specific embodiments, after described deposition first medium layer step, before the definition first medium layer pattern step, also have one on described first medium layer the step of the hard mask dielectric layer of deposition; Described the first etching technics etches away first medium layer and the hard mask dielectric layer of other All Rangeses beyond the described first medium layer pattern; Described hard mask dielectric layer can stop the second etching technics.
In the manufacture method of the described metal-dielectric-metal capacitance of employing such scheme, increased the step of the hard mask dielectric layer of deposition on the first medium layer, and but this hard mask dielectric layer stops the second etching technics does not stop that or not first etching stops technique, thereby omitted the step of the accurate aligning that need to carry out forming photoetching offset plate figure on to described first medium layer pattern before the second etching technics, particularly, when described first medium tomographic image zone hour, overcome the difficulty that is difficult to lithography registration.This technical scheme has adopted Self-aligned etching technique, has therefore reduced again defining the lithography registration precision problem that photoetching offset plate figure brings on existing graphics.
In a preferred specific embodiments, described first medium layer pattern is positioned at described capacitor regions, and described second medium layer pattern is positioned at described metal connecting line zone; That is, the dielectric layer in first deposited capacitances zone deposits hard mask dielectric layer again, behind the first etching technics, the dielectric layer in plated metal line zone before the second etching technics, need not the first medium layer pattern of capacitor regions is carried out accurately lithography registration afterwards again.
In a preferred specific embodiments, described hard mask dielectric layer adopts silicon nitride material.
Description of drawings
Fig. 1 is the schematic top plan view of the metal-dielectric-metal capacitance of the embodiment of the invention 1;
Fig. 2 is along the cutaway view of A-A ' direction among Fig. 1;
Fig. 3-Fig. 7 show the metal-dielectric-metal capacitance of the embodiment of the invention 1 manufacturing process (with among Fig. 1 along the signal that is as the criterion of analysing and observe of A-A ' direction).
Embodiment
As shown in Figure 1, the schematic top plan view of a metal-dielectric-metal capacitance Figure 2 shows that among Fig. 1 the cutaway view along A-A ' direction.
The wafer substrate of this electric capacity comprises that substrate 1(can be simple silicon substrate, also can be that the surface has formed the substrate of semiconductor device layer) and be produced on one or more layers metal level unit 2 on the substrate 1;
The step of road metal level is as follows after this wafer substrate is made one deck:
Metal connecting line zone 101, rear road and capacitor regions 102 are produced in the same rear road metal level, as shown in Figure 1, capacitor regions 102 has the metal-dielectric-metal structure of slotting finger-like, and capacitor regions 102 comprises the first electrode (male or female), the second electrode (negative electrode or anode).The first electrode together connects a bonding jumper (electrode 13) by several finger-like pole plates 11 that are parallel to each other and their homonymy end points and forms, and the second electrode connects another bonding jumper (electrode 14) by several finger-like pole plates 12 that are parallel to each other and their opposite side end points and forms.The first electrode and the second electrode mutually form to insert and refer to structure, and the first medium layer 3(by curved structure exists only in the capacitor regions 102 between the two) separate.Metal connecting line zone 101 comprises each metal wire of metal level 6, is present in the metal connecting line zone 101 and the second medium layer 5 between metal connecting line regional 101 and the capacitor regions 102.
The material that first medium layer 3 adopts high dielectric constant for example can adopt Al as insulating medium layer
2O
3(k ~ 9), Si
3N
4(k ~ 7.8), ZrO
2(k ~ 25), TiO
2Materials such as (k ~ 80), present embodiment adopts Al
2O
3Material.
The material that second medium layer 5 adopts conventional or lower dielectric constant adopts the Normal silica material as buffer layer in the present embodiment.
As shown in Figure 3, method by plasma enhanced chemical vapor deposition (PECVD) or ald (ALD) on wafer substrate deposits one deck first medium layer 3, the hard mask dielectric layer of deposition one deck 4(adopts the hard mask dielectric layer of silicon nitride material in the present embodiment as hard mask dielectric layer on first medium layer 3 again).
Define the first medium layer pattern (namely at hard mask dielectric layer 4 surperficial spin coating photoresists by photoetching process, photoetching forms the first medium layer pattern, the graphics field of overlooking referring to first medium layer shown in Figure 1), and etch away unnecessary first medium layer 3 and hard mask dielectric layer 4 by the first etching technics, formed haply the medium groove of capacitor regions 102, as shown in Figure 4.
As shown in Figure 5, the crystal circle structure surface deposition one deck second medium layer 5 by chemical vapour deposition (CVD) or spin coating technique form behind the first etching technics grinds second medium layer 5 by the method for chemico-mechanical polishing, makes its flattening surface.
Define the second medium layer pattern by photoetching process, concrete, at second medium layer 5 surperficial spin coating photoresist, and by photoetching formation second medium layer pattern, as shown in Figure 6, need the graphics field of the second medium layer of reservation to cover photoresist layer 7, photoresist layer 7 stops the second etching technics.
The first medium layer pattern that needs to keep has covered the hard mask dielectric layer 4 that can stop the second etching technics, therefore, before the second etching technics, need not on the first medium layer pattern, to form photoetching offset plate figure, avoided working as the difficulty of the lithography registration of hour existence of first medium layer pattern.
Behind the second etching technics, except first medium layer pattern and second medium layer pattern were retained, other regional second medium layers all had been etched away, and referring to Fig. 7, have formed the medium groove.
Formed body structure surface electro-coppering metal level behind described the second etching technics will all be filled the copper metal in the formed medium groove again.Carry out planarization by CMP (Chemical Mechanical Polishing) process at last, remove the unnecessary copper metal in surface and hard mask dielectric layer 4, in this course, also can remove simultaneously the second medium layer 5 of very little thickness, form at last metal-dielectric-metal capacitance as depicted in figs. 1 and 2.
Between each bonding jumper of metal connecting line zone 101 inner metal layers 6, and between metal connecting line zone 101 and the capacitor regions 102 with second medium layer 5 as buffer layer.
Between two electrodes in the capacitor regions 102 with first medium layer 3 as insulating medium layer.
By above-mentioned manufacture method, electric capacity with insulating medium layer of high dielectric constant can be integrated into and adopt in conventional or the subsequent interconnection technique than medium with low dielectric constant, thereby not affect the RC stray delay of metal connecting line when can be implemented in large capacity integrated capacitance.
It should be noted that for a person skilled in the art the capacitive junctions composition that understanding that can be very clear is above-mentioned and manufacture process schematic diagram are as just the signal explanation, actual conditions can be inconsistent with illustrated ratio.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (6)
1. the manufacture method of a metal-dielectric-metal capacitance, it comprise substrate is provided and after making one deck at least on the substrate step of metal level unit, road,
Metal level unit, described rear road comprises metal connecting line zone and capacitor regions; Described capacitor regions has the capacitance structure of metal-dielectric-metal;
The manufacturing process of metal level unit, described rear road comprises following steps:
On substrate, deposition first medium layer;
Define the first medium layer pattern at formed body structure surface, and etch away the first medium layer of described first medium layer pattern other All Rangeses in addition by the first etching technics;
Formed body structure surface deposition second medium layer behind described the first etching technics;
Define the second medium layer pattern at formed body structure surface, and etch away described first medium layer pattern and second medium layer pattern second medium layer in addition by the second etching technics;
Formed body structure surface depositing metal layers behind described the second etching technics again;
In metal level unit, described rear road: described first medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described second medium layer pattern is the figure of the dielectric layer in described metal connecting line zone; Perhaps, described second medium layer pattern is the figure of the dielectric layer of described capacitor regions, and described first medium layer pattern is the figure of the dielectric layer in described metal connecting line zone;
The dielectric layer of described capacitor regions adopts the material of High-K; The dielectric layer in described metal connecting line zone adopts the material of Low-K.
2. method as claimed in claim 1 is characterized in that: the dielectric layer of described capacitor regions adopts dielectric constant greater than 7 material; The dielectric layer in described metal connecting line zone adopts dielectric constant less than 4 material.
3. method as claimed in claim 1, it is characterized in that: the dielectric layer of described capacitor regions adopts Al
2O
3, Si
3N
4, ZrO
2, TiO
2In any one material.
4. method as claimed in claim 3, it is characterized in that: the dielectric layer of described capacitor regions adopts Al
2O
3Material.
5. such as the described method of any one among the claim 1-4, it is characterized in that: after described deposition first medium layer step, before the definition first medium layer pattern step, also have one on described first medium layer the step of the hard mask dielectric layer of deposition;
Described the first etching technics etches away first medium layer and the hard mask dielectric layer of other All Rangeses beyond the described first medium layer pattern;
Described hard mask dielectric layer can stop the second etching technics.
6. method according to claim 5 is characterized in that: described hard mask dielectric layer employing silicon nitride material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210349563.2A CN102903611B (en) | 2012-09-19 | 2012-09-19 | A kind of Metal-dielectric-metcapacitor capacitor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210349563.2A CN102903611B (en) | 2012-09-19 | 2012-09-19 | A kind of Metal-dielectric-metcapacitor capacitor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102903611A true CN102903611A (en) | 2013-01-30 |
| CN102903611B CN102903611B (en) | 2018-06-22 |
Family
ID=47575795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210349563.2A Active CN102903611B (en) | 2012-09-19 | 2012-09-19 | A kind of Metal-dielectric-metcapacitor capacitor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102903611B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107078710A (en) * | 2014-11-07 | 2017-08-18 | 高通股份有限公司 | Variable high pressure radio frequency attenuator |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254183A (en) * | 1998-11-13 | 2000-05-24 | 国际商业机器公司 | Self-alignment process capable of making subcritical contact with wire |
| US6638830B1 (en) * | 2002-09-18 | 2003-10-28 | United Microelectronics Corp. | Method for fabricating a high-density capacitor |
| US20030213990A1 (en) * | 2002-05-17 | 2003-11-20 | United Microelectronics Corp. | Embedded capacitor structure applied to logic integrated circuit |
| US20050042835A1 (en) * | 2003-08-19 | 2005-02-24 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
| CN101308331A (en) * | 2007-05-16 | 2008-11-19 | 上海华虹Nec电子有限公司 | Two time graph exposure method utilizing developing filler material |
| CN102420104A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Manufacturing method of MIM (Metal-Insulator-Metal) capacitor |
| CN102427054A (en) * | 2011-06-17 | 2012-04-25 | 上海华力微电子有限公司 | Manufacturing method of metal-oxide-metal with high performance |
| CN102446709A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Production method of metal-silicon nitride-metal capacitor |
| CN102522370A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | Formation method of contact hole |
| CN102592968A (en) * | 2011-11-15 | 2012-07-18 | 上海华力微电子有限公司 | Method for producing multilayer metal-silicon nitride-metal capacitor |
-
2012
- 2012-09-19 CN CN201210349563.2A patent/CN102903611B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254183A (en) * | 1998-11-13 | 2000-05-24 | 国际商业机器公司 | Self-alignment process capable of making subcritical contact with wire |
| US20030213990A1 (en) * | 2002-05-17 | 2003-11-20 | United Microelectronics Corp. | Embedded capacitor structure applied to logic integrated circuit |
| US6638830B1 (en) * | 2002-09-18 | 2003-10-28 | United Microelectronics Corp. | Method for fabricating a high-density capacitor |
| US20050042835A1 (en) * | 2003-08-19 | 2005-02-24 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
| CN101308331A (en) * | 2007-05-16 | 2008-11-19 | 上海华虹Nec电子有限公司 | Two time graph exposure method utilizing developing filler material |
| CN102420104A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Manufacturing method of MIM (Metal-Insulator-Metal) capacitor |
| CN102427054A (en) * | 2011-06-17 | 2012-04-25 | 上海华力微电子有限公司 | Manufacturing method of metal-oxide-metal with high performance |
| CN102446709A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Production method of metal-silicon nitride-metal capacitor |
| CN102592968A (en) * | 2011-11-15 | 2012-07-18 | 上海华力微电子有限公司 | Method for producing multilayer metal-silicon nitride-metal capacitor |
| CN102522370A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | Formation method of contact hole |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107078710A (en) * | 2014-11-07 | 2017-08-18 | 高通股份有限公司 | Variable high pressure radio frequency attenuator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102903611B (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102569250B (en) | High-density capacitor and electrode leading-out method thereof | |
| CN1113401C (en) | Capacitors in integrated circuits | |
| US20210375760A1 (en) | Metal Line Structure and Method | |
| CN100539016C (en) | MIM capacitor and manufacture method thereof | |
| CN104241249A (en) | Silicon through hole interconnection structure and manufacturing method thereof | |
| CN101819922A (en) | Metal-insulator-metal capacitor and preparation method thereof | |
| CN103811310B (en) | Electric resistance structure and forming method thereof | |
| CN106997878A (en) | The silicon capacitor and its manufacture method of double-decker | |
| US20150140778A1 (en) | Method for manufacturing metal-insulator-metal capacitor structure | |
| CN104377191A (en) | Capacitive structure compatible with integrated circuit process and preparation method thereof | |
| CN202905470U (en) | Multilayer silicon-based capacitor electrode connection structure | |
| CN101378057B (en) | Metal-insulator-metal capacitor and method for manufacturing the same | |
| CN102110638B (en) | Method and structure for overcoming discharge shortcoming of semiconductor device during manufacturing process | |
| CN102903611A (en) | Metal-dielectric-metal capacitor and manufacturing method thereof | |
| CN102446709B (en) | A kind of manufacture method of metal-silicon nitride-metal capacitor | |
| KR100977924B1 (en) | Stacted structure of MIM capacitor for high density and manufacturing method thereof | |
| US20090256238A1 (en) | Capacitor of Semiconductor Device and Method of Fabricating the Same | |
| CN104103574B (en) | The preparation method of semiconductor devices | |
| CN102446915B (en) | Novel metal-insulator-metal (MIM) capacitor structure and manufacturing method thereof | |
| CN102420103B (en) | Copper Damascus process MIM (metal-insulator-metal) capacitor structure and manufacturing process | |
| CN101097912A (en) | Capacitance structure for enhancing capacitance of flat capacitance | |
| CN1469463A (en) | Method of forming molten through hole structure | |
| US11916100B2 (en) | Multi-layer trench capacitor structure | |
| CN210443583U (en) | High-reliability MIM capacitor | |
| CN102903612A (en) | Manufacture method of metal-oxide-metal capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |