CN102893419A - 应力被调节的半导体装置及其相关方法 - Google Patents

应力被调节的半导体装置及其相关方法 Download PDF

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CN102893419A
CN102893419A CN2011800061052A CN201180006105A CN102893419A CN 102893419 A CN102893419 A CN 102893419A CN 2011800061052 A CN2011800061052 A CN 2011800061052A CN 201180006105 A CN201180006105 A CN 201180006105A CN 102893419 A CN102893419 A CN 102893419A
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layer
carbon
coating
diamond
radiator
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宋健民
甘明吉
胡绍中
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LAIZUAN TECHNOLOGY Co Ltd
RiteDia Corp
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LAIZUAN TECHNOLOGY Co Ltd
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Abstract

本发明涉及一种应力被调节的半导体装置及其相关方法。在一种实施方式中，一应力被调节的半导体装置例如可以包括：一半导体层；一应力调节界面层，其包括一形成于半导体层上的碳层；以及一散热器，其耦合至相对于半导体层的碳层。该应力调节界面层可用来降低在半导体层及散热器之间的热膨胀系数差异至小于或等于约10ppm/℃。

Description

应力被调节的半导体装置及其相关方法
技术领域
本发明属于电子学及材料学技术领域，具体涉及一种半导体装置及其相关方法。
背景技术
在许多发达国家中，普遍认为电子装置与生活息息相关，而对于电子装置的小型化且快速化的需求，随着对电子装置的使用度及依赖度的增加而增加。在电子电路的速度增加以及体积缩减的同时，电子装置的冷却将成为问题。
一般来说，电子装置是由多个电子元件所连接组成的电路板，以使该装置具有完整的功能，其中，电子元件例如为处理器、晶体管、电阻器、电容器、发光二极管(LED)等。在完整的电子装置中，会因为其中的电子元件而产生各种与热能相关的问题，而由于电子元件所产生的显著热能，可能影响电子装置的可用性，甚至导致其无法使用，最终影响电子装置的寿命，例如电子元件以及印刷电路板表面之间发生烧毁或短路。而上述问题特别会发生于高功率及高电流需求的电子元件，以及用来支持这些电子元件的印刷电路板。
目前，有很多冷却装置可用来解决上述电子装置的散热问题，如风扇、散热片、珀尔帖(Peltier)及水冷装置等。而这些冷却装置大多需要增大其体积，以达到有效冷却电子装置的效果，但其所伴随加速的能量消耗，则会增加热能的产生。例如，增加风扇体积及加速其运转，以增加空气流动、增加散热片体积，以增加其表面积与热承载量。然而，对于电子装置的小型化需求，不仅使冷却装置所需增加的体积受到限制，也可能使需要显著缩小体积的电子装置受到限制。
发明内容
本发明提供一种应力被调节的半导体装置及其相关方法，例如在一种实施方式中，一种应力被调节的半导体装置可包含一半导体层；一应力调节界面层，其包含一碳层，通过一碳化物形成物键合至该半导体层；以及一散热器，其耦合至相对于该半导体层的应力调节界面层。此应力调节界面层用于降低在该半导体层及该散热器之间的热膨胀系数差异，使其小于或等于约10ppm/℃。在另一实施方式中，其应力调节界面层用于降低在半导体层及该散热器之间的热膨胀系数差异，使其小于或等于约5ppm/℃。
根据本发明的一种实施方式，各种半导体材料可用来形成本发明装置的结构。在一种实施方式中，半导体材料并无限制，可包括：硅、碳化硅、硅锗、砷化镓、氮化镓、锗、硫化锌、磷化镓、锑化镓、磷砷镓化铟、磷化铝、砷化铝、砷化铝镓、氮化镓、氮化硼、氮化铝、砷化铟、磷化铟、锑化铟、氮化铟、及包含其复合的类似物。在一具体实施方式中，半导体材料可包括氮化镓、氮化铝、及其组合。
根据本发明的一种实施方式，各种碳材料也可用来形成该碳层。该碳层材料并无限制，包括：类钻碳、掺杂硼钻石、非晶钻石、结晶性钻石、多晶钻石、石墨、及包含其组合的类似物。在一具体实施方式中，碳层具有一非晶原子结构。在另一具体实施方式中，碳层为类钻碳。又在另一具体实施方式中，碳层掺杂硼钻石。
根据本发明的一种实施方式，各种材料可用来形成散热器层，其材料并无限制，包括铝、铜、锡、钨、镍、钛、金、银、铂、Al2O3、AlN、Si3N4、Si、玻璃、及其组合与其合金、及包括合金及其混合物的类似物。在一具体实施方式中，散热器包含铜。
在另一实施方式中，一反射层设置于碳层及半导体层之间。在再一实施方式中，一碳化物形成物层可设置于碳层及反射层间。在另一实施方式中，一碳化物形成物层可设置于碳层及散热器层间。
本发明另一实施方式提供一种应力被调节的半导体装置，此装置包括一半导体层及一形成于半导体层上的一散热器，其中，此散热器包括均匀设置于一金属基质中的钻石颗粒。而此钻石颗粒用于降低在半导体层以及金属基质之间的热膨胀系数差异，使其小于或等于约10ppm/℃。在另一实施方式中，钻石颗粒用于降低在半导体层以及金属基质之间的热膨胀系数差异，使其小于或等于约5ppm/℃。
本发明另一实施方式提供一种应力被调节的半导体装置，此装置包括：一半导体层；形成于该半导体层上的一导电氮化硼层；以及一散热器，此散热器是耦合至相对于该半导体层的氮化硼层。该氮化硼层用于降低在半导体层及该散热器之间的热膨胀系数差异，使其小于或等于约10ppm/℃。
本发明再一种实施方式提供一种降低导致半导体装置内缺陷的应力的方法，此方法可包括：形成一含有碳层的应力调节界面层至一半导体层上、以及将一散热器层耦合至相对于该半导体层的碳层。于部份实施方式中，将该散热器耦合至应力调节界面层，包括将散热器形成于应力调节界面层。于此，应力调节界面层用于降低在半导体层及散热器之间的热膨胀系数差异，使其小于或等于约10ppm/℃。在另一实施方式中，此方法还包括：于应力调节界面层及半导体层间形成一反射层。在另一具体实施方式中，此方法可还包括于碳层及反射层间形成一碳化物形成物层。在再一实施方式中，该方法可包括于碳层及金属散热器层间形成一碳化物形成物层。
本发明的另一实施方式提供一种应力被调节的发光半导体装置。此装置可包括：一发光半导体材料、一形成于半导体材料的碳层、以及一耦合至该碳层的金属散热器，其中，此碳层用于降低在半导体层及该金属散热器之间的热膨胀系数差异，使其小于或等于10ppm/℃。在一种实施方式中，此金属散热器形成于碳层上。
附图说明
图1是本发明的一个实施例的应力被调节的半导体装置的横截面图。
图2是本发明的另一实施例的应力被调节的半导体装置的横截面图。
图3是本发明再一实施例的应力被调节的半导体装置的横截面图。
图4是本发明的另一实施例的应力被调节的半导体装置的横截面图。
图5是本发明再一实施例的应力被调节的半导体装置的横截面图。
图6是本发明的另一实施例的应力被调节的半导体装置的横截面图。
图7是本发明的另一实施例的应力被调节的半导体装置的横截面图。
图8是本发明的再一实施例的应力被调节的半导体装置的横截面图。
图9是本发明的另一实施例的应力被调节的半导体装置的横截面图。
图10是本发明的再一实施例的应力被调节的半导体装置的横截面图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
定义
本发明的说明书及权利要求书中使用的用语应解释为如下定义。
量词“一”、以及定语“该“、“所述”并不是用于限制其修饰的项目或元件的个数为一个，而是可以为多个，除非文中有其他清楚的说明。因此，例如，“一掺杂”包括一种或多种掺杂物、“该钻石层”包括一层或多层钻石层。
在此，“气相沉积(vapor deposited)”表示使用气相沉积技术而使材料形成。“气相沉积物(vapor deposition)”表示以气相方式将材料形成或沉积在一基板上。气相沉积法可包括任何方式，例如：化学气相沉积法(chemicalvapor deposition，CVD)以及物理气相沉积法(physical vapor deposition，PVD)，但不限于此。各种气相沉积法可通过所属技术领域的普通技术人员实施。气相沉积法例如包括：热灯丝化学气相沉积法(hot filament CVD)、射频电浆化学气相沉积法(rf-CVD)、激光化学气相沉积法(LCVD)、激光剥离法(laser ablation)、表面钻石涂布法(conformal diamond coating process)、金属-有机化学气相沉积法(metal-organic CVD，MOCVD)、溅镀、热蒸镀物理气相沉积法(thermal evaporation PVD)、离子化金属物理气相沉积法(ionized metal PVD，IMPVD)、电子束物理气相沉积法(electron beam PVD，EBPVD)、反应物理气相沉积法、阴极电弧(cathodic arc)，及其类似方法。
在此，“化学气相沉积”或“CVD”表示利用任一种化学方法，以气相型态形成或沉积于钻石颗粒表面。于该领域中，有多种CVD的公知技术。
在此，“物理气相沉积法”或“PVD”表示利用任一种物理方法，以气相型态形成或沉积于钻石颗粒表面。于该领域中，有多种PVD的公知技术。
在此，“钻石”表示碳原子与碳原子结合形成的一种四面体晶型的晶体结构，其中，碳原子是以sp3键合，具体是指每一碳原子由四个碳原子围绕键合，而每一碳原子位于一四面体结构的顶角。此外，任两个碳原子之间的键距是1.54埃(于环境温度状态)，而任两个碳原子之间的角度是109度28分16秒(即使环境具有微小变化)。具有此物理及电特性的钻石的结构及种类为所属技术领域的技术人员所熟知。
在此，“扭曲四面体配位(distorted tetrahedral coordination)”表示一种由碳原子形成的不规则四面体结构，或如上述钻石规则四面体结构的偏离。此扭曲结构一般是部分键的延长和其它键的缩短，以及在键之间形成不同键合角度。此外，扭曲四面体会改变碳的特性及性质，使其有效地位于sp3碳键合形态(如钻石)以及sp2碳键合形态(如石墨)之间。例如，具有扭曲四面体键合的碳原子键合是非晶钻石(amorphous diamond)。
在此，“类钻碳(diamond-like carbon)”表示一种以碳原子为主要成分的含碳材料，且大多碳原子以扭曲四面体键合。即使CVD或其它工艺可用于其气相沉积，但类钻碳(DLC)基本上都是通过PVD方式所形成。值得注意的是，DLC材料中含有其它成分的不纯物或掺杂物，如：氢、硫、磷、溴、氮、硅、钨等，并无特别限制。
在此，“非晶钻石(amorphous diamond)”表示一种具有以碳原子为主要成份的类钻碳，其具有大量的碳原子键合于扭曲四面体配位中。在一种实施方式中，该非晶钻石中的碳含量可达到至少约90％，其中至少约20％的碳键合于扭曲四面体配位中，且非晶钻石也具有比钻石(176原子/cm3)高的原子密度。此外，非晶钻石以及钻石材料会于熔融时会发生收缩。
术语“热转移(heat transfer)”、“热移动(heat movement)”、以及“热传送(heat transmission)”可相互转用，均表示热量由高温处往低温处移动。热量移动包括任一所属技术领域所了解的热量传送机制，例如，传导、对流、辐射等，其并无特别限制。
在此，“发光表面(light-emitting surface)”表示光线由一装置或物体的表面所发出，该光线可包括可见光以及在紫外线光谱内的光。一发光表面的实施例可包括：一LED的氮化物层、或一半导体层合并至LED，并由此发光，并无特别限制。
在此，“基板(substrate)”表示一支撑表面，其中，可结合各种材料，以形成一半导体或钻石底半导体的装置。该基板可具有任何形状、厚度、或材料，视要达到的结果而定，其包括：金属、合金、陶瓷、及其混合，但不限制于此。再则，在一些实施方式中，基板是现有的半导体装置或晶圆，也可以是一种能够结合到适合装置的材料。
在此，术语“实质上(substantially)”表示动作、特征、特性、状态、结构、项目、或结果具有完全的或接近完全的范围或程度。例如，一“实质上”封闭的物体意指该物体不是完全地封闭，就是接近完全地封闭。相比于绝对的完全，其确切的允许误差程度可视具体上下文而定。然而，一般谈到“接近完全”可视为“如同绝对”及“全部完全”所具有相同的整体结果。“实质上”同样可应用于一负面含意，其意指一动作、特征、特性、状态、结构、项目、或结果为完全的或接近完全的缺乏。例如，一组成物为“实质上没有”颗粒意指该组成物不是完全地缺乏颗粒，就是接近完全地缺乏颗粒，其效果如同完全地缺乏颗粒一样。换言之，“实质上没有”一成分或元素的组成物，只要不具有重要的效果，实际上可仍包括此项目(指该成分或元素)。
在此，术语“约(about)”是指提供一数值范围端点的弹性，即一给定值可以“稍微高于”或“稍微低于”此数值端点。
在此，个数为多个的项目、结构元件、组成元件和/或材料为了方便而以一般的列举呈现。然而，这些列举中应解释为每个列举元件可视为单独且独特的元件。因此，基于一般呈现而没有相对的其它描述的集合内，此列举的单独元件不需要单独地被解释为事实上相等于其它相同列举出的元件。
在此，浓度、含量或其它数据可以用一范围形式以表达或呈现。应了解所述范围形式仅是为了方便和简洁而使用，因此应被弹性地解释，数值不仅包括明确列举的范围界限，而且包括所述范围内包含的所有独立数值或子范围，如同各数值和子范围被明确列举一样。例如，“大约1到大约5”的数值范围应被解释为不仅包括大约1到大约5的明确列举数值，而且也包括所指范围内的独立数值和子范围。于是，所述数值范围中包括的为诸如2、3和4的独立数值以及诸如从1-3、从2-4、与从3-5等的子范围，以及1、2、3、4、及5。
相同原理适用于仅列举一个数值的范围的最小或最大值。此外，不管被描述范围的幅度或特性，此解释都将适用。
发明
本发明提供一种应力被调节的装置以及其相关方法。相比于公知装置，本发明所提供的装置更能达到冷却的功效，且可在较高运作功率上操作。在一种实施方式中，本发明可应用于垂直式设计的半导体装置，举例来说，一垂直式设计的半导体是一垂直式堆叠LED。以下许多讨论均涉及垂直式堆叠LED，但应该了解的是，其仅是为了方便的目的，而任一型态的半导体装置及/或半导体结构或设计都应被认定为本发明的范畴之内。
一种冷却垂直式堆叠LED的可能技术是将铜涂布于晶圆以提供作为散热器，并与半导体材料紧密结合。然而，问题在于，铜与多种半导体材料之间的热膨胀系数(coefficient of thermal expansion，CTE)存有差异，且铜相比于半导体材料(例如硅)的CTE具有三倍的差异。当一LED在高温操作下，在温度变化时，相对于半导体材料，铜会较大程度的膨胀及收缩，且会导致微裂痕、分层，以及在铜和半导体材料间界面的其它缺陷。而这些微裂痕会导致LED随时间而破坏。
除了操作上的破坏之外，在某些情况下，在制造过程中，缺陷会被导入半导体装置。例如，在某种制造技术中，金属散热器通过焊料而耦合至半导体材料。而硬焊过程中，在材料间热不匹配时，即会发生或即将发生缺陷、裂痕、分层、及其类似情形。
本申请的发明人已发现许多材料可被用来调节在散热材料(如铜)与半导体之间的CTE不匹配，故可降低在制造及/或使用过程中由于温度循环所导致的界面应力。而此材料包括各种形式的钻石、石墨、氮化硼及其类似材料，并无特别限制。另一个优点是这些材料有好的热传导性，能促进来自半导体装置的热量移动。以下许多针对钻石材料的讨论仅是为了方便，需注意的是，任一能够在不同材料间调节CTE的材料皆属于本发明的范畴。
根据本发明的实施方式的半导体装置，其具有许多种应用，包括：LED、激光二极管、p-n结装置(junction device)、p-i-n结装置、SAW以及BAW滤波器及其类似应用。在一种实施方式中，半导体装置是一种LED装置。在另一具体实施方式中，半导体装置是一种具有垂直式堆叠结构的LED装置。
在一种实施方式中，如图1所示，一应力被调节的半导体装置10可包括一半导体层12、一形成于半导体层12上的碳层14，以及耦合至相对于半导体层12的碳层14的一散热器16。此碳层14可降低在半导体层12与散热器16之间的CTE差异，使其小于或等于约10ppm/℃。在另一实施方式中，碳层可降低在半导体层与散热器之间的CTE差异，使其小于或等于约5ppm/℃。此外，该碳层可为导体、非导体、或半导体，取决于装置的设计。值得注意的是，图1以及所有随后的附图中，其半导体层12可为一层或多层的结或其它结构。
碳层可为单层碳层或多层碳层，且可包括其它材料或材料层，例如碳化物形成物(carbide formers)。术语“应力调节界面层(stress regulatinginterface layer)”可被用于描述一层或多层碳层以及任一与其连接的材料或材料层。例如，在一种实施方式中，应力调节界面层可包括一碳层以及一碳化物形成物。
一垂直式堆叠设计的优点与半导体电接点(electrical contact)的配置相关，相对于许多传统设计，一垂直式堆叠LED的电接点位于半导体一端及与其相对应的另一端，可提供电流由一电接点至另一电接点的线性流动。如图2所示，一垂直式堆叠装置20可包括一半导体层12、一形成于半导体层上的碳层14、以及一散热器层16，其形成至相对于半导体层的碳层。此外，一电接点18可耦合至相对于散热器层16的半导体层。在此情况下，碳层是导体，可使碳层及/或散热器层作为另一电接点，以使电流可由一电接点线性流动至另一电接点。值得注意的是，在部分实施方式中，除了碳层及/或散热器层外，一第二电接点可耦合至该装置。
根据本发明的实施方式，可考虑将各种附加层并入装置中，举例来说，于许多应用中(包括光产生装置)，可包括一反射层，以利于聚焦及/或引导光线位置。如图3所示的例子中，一LED装置30可包括一设置于碳层14与半导体层12的反射层32。由垂直式堆叠LED装置的半导体层所产生的光，可以发射至多个方向。一部分的光线可通过半导体层12而向前发射，并由散热器层16的方向离开装置；另一部分的光线可由半导体层朝向散热器层16以及碳层14方向发射。因此，该反射层32具有反射部分光线的作用，使其通过半导体层而离开LED。依照钻石层特有的光学特性而使用，该反射层可设置于半导体层与碳层之间(如图所示)，或者可设置于碳层与散热器层之间(图未示)。
在部分实施方式中，将一夹层设置于碳层及碳层键合的另一层间，可具有良好的特性。例如，一碳化物形成物能够改善一碳材料(例如钻石)及各种其它材料之间的键合。举例来说，如图4所示，一碳化物形成物42可设置于碳层14及反射层32之间，以改善碳层与反射层的耦合。在另一实施方式中，如图5所示，一碳化物形成物42可设置于碳层14及散热器层16之间，以改善散热器层与碳层的耦合。此外，一碳化物形成物层亦可应用于一碳层以及一半导体层之间(图未示)。
再则，CTE的不匹配还可以通过使用多层碳层而改善。在部分实施方式中，将多层碳层之间以其它材料层交替设置可具有助益，举例来说，在一多层碳层堆叠的实施方式中，可包括分散于碳层之间的碳化物形成物层。在一种具体实施方式中，一应力调节界面层可包括多层碳层，且钛层分散于其间，以改善在散热器及半导体层之间的CTE匹配。在另一具体实施方式中，一应力调节界面层可包括DLC及碳化物形成物(例如Ti)的替换层，以改善CTE匹配。
除了钻石层之外，钻石颗粒64也可用来降低在金属散热器及半导体层之间的CTE不匹配。如图6所示，一种应力被调节的半导体装置60可包括一半导体层12以及一形成于半导体层12的散热器62。钻石颗粒64均匀地设置于金属散热器62内，该钻石颗粒的存在可降低在半导体层及散热器层之间的CTE不匹配。如图7所示，钻石颗粒64亦可排列成一单层。在一种实施方式中，该钻石颗粒可用于降低在半导体层及金属基质之间的CTE差异至小于或等于约10ppm/℃。在另一实施方式中，钻石颗粒可用于降低在半导体层以及金属基质之间的CTE差异，使其小于或等于约5ppm/℃。故相比于分别地形成一钻石单层/金属散热装置，在半导体装置的制备过程中，将含有钻石颗粒的散热器形成于半导体层上，可不需经过焊接步骤。
于本发明另一实施方式中，一应力被调节的半导体装置可由以下方法所制备。如图8所示，一碳层82形成于一具有基板86(蓝宝石)的半导体层84上。在一具体实施方式中，半导体层可包括GaN。在部分实施方式中，一碳化物形成物层可设置于碳层82及半导体层84之间，以改善上述所提及的键合。如图9所示，一散热器层92形成于碳层82上。在部分实施方式中，一碳化物形成物层可设置于一碳层82，以改善如上所述的与散热器92之间的键合(图未显示)。此外，该散热器层增厚，可改善装置的热传导性及/或物理稳定性。在部分实施方式中，如图10的基板86可被移除，而其后的半导体结构可设置于裸露的半导体层84上。基板可通过各种公知方法移除，包括激光分离(laser splitting)、机械移除、化学蚀刻、及其类似方法。在部分实施方式中，其半导体的裸露表面可通过平面化或平坦化，以改善后续在该表面上的其它设置。需注意的是，图10所示的装置可旋转180°以清楚表示。
在本发明另一实施方式中，提供一种用于降低在半导体装置内导致缺陷的应力的方法，包括在半导体层上形成一钻石层，并将一散热器层耦合至相对于该半导体层的该钻石层。该钻石层会降低在半导体层及散热器之间的热膨胀系数差异，使其小于或等于约10ppm/℃。在一种实施方式中，此方法还包括在钻石层以及半导体层之间形成一反射层，如上所述，在部分实施方式中，一碳化物形成物层可形成于钻石层以及反射层之间。在另一实施方式中，一碳化物形成物层可形成于钻石层以及散热器层之间，在再一实施方式中，将散热器耦合至钻石层包括形成散热器于钻石层上。
根据本发明的一种实施方式，多种碳材料可用于碳层，包括非晶钻石、类钻碳、多晶钻石、结晶钻石、单晶钻石、石墨及其类似物，其并无限制。在一种实施方式中，碳层可为一非晶钻石层。在另一实施方式中，碳层可为一类钻碳层。需注意的是，任何碳层型式可用于形成于一半导体层。
在一种实施方式中，利用一应力调节界面层(具有非晶原子结构的碳层)可改善CTE的匹配性。在非晶材料的例子有类钻碳、非晶钻石、及其类似物。在不考虑科学理论情况下，非晶材料，例如类钻碳，由于其具有非结晶结构，故具有高的弹性或屈服点(yield limit)。因此，当非晶材料设置于两个刚性结构中(例如散热器及半导体)，于加热或冷却情况下，该材料(例如类钻碳)的非晶原子结构可吸收这些材料以不同速率膨胀及收缩时所导致这些材料间膨胀及收缩的差异。
如在本发明的实施方式中，碳层可具有任一厚度，以容许半导体装置的加热冷却及调节CTE的不匹配。碳层可具有不同的厚度，取决于其应用及半导体装置的结构，例如，具有较多冷却需求的，可能需要较厚的碳层。另外，其厚度也会根据碳层所用的材料而不同。在部分实施方式中，特别指那些需要薄形化的装置，优选使用几乎无厚度的碳层。也就是说，在一种实施方式中，一碳层的厚度可由约10μm至约300μm。在另一实施方式中，一碳层的厚度可低于或等于约10μm。在再一实施方式中，一碳层的厚度可由约50μm至约100μm。在再另一实施方式中，一碳层厚度可更大于约50μm。在再一实施方式中，该碳层厚度可由约1μm至约30μm。在再另一实施方式中，该碳层厚度可由约5μm至约30μm。在再一实施方式中，该碳层厚度低于约1μm。在一种实施方式中，该碳层厚度可由约0.1μm至约10μm。在另一实施方式中，该碳层厚度可由约0.5μm至约2μm。
在一种实施方式中，该碳层可为钻石材料，例如结晶钻石、非晶钻石、类钻碳及其类似物。钻石材料具有优异的热传导特性，以使其应用于半导体装置。通过钻石材料的使用，可增加半导体装置的热传导效果。需注意的是，本发明并不限制于特定的热传导理论。例如在一种实施方式中，由于热量移动及通过钻石层，而至少部分地增加装置内的热量移动。由于钻石的热传导特性，热量可以通过钻石层在横向快速地分散，并分散至半导体装置的边缘。装置边缘的热能会快速消散至空气中或是至周围结构，例如散热器或支撑装置。此外，由于该钻石层可使热量传递至与其连结的金属散热器层，且钻石的热传导性高于与其热耦合的半导体层的热传导性，故散热片可通过钻石层设置，由此，由半导体层产生的热量可借此传递至钻石层，并通过横向分散而转移至金属散热器，使半导体装置通过热转移的促进而更易冷却。此外，上述对热转移的促进不仅可用来冷却半导体装置，更可以用来降低许多半导体装置附近的电子元件的热承载。
需了解的是，以下是关于各种钻石沉积技术的讨论，其可适用或不适用于一特定的层或应用，且此技术可视本发明的各种实施方式而变化。上述提及的其它材料，例如氮化硼及石墨，皆包含于本发明的范畴内，而以下的沉积技术可适当地应用于这些材料。一般而言，钻石层可通过公知技术来形成，包括各种气相沉积技术。任何一种公知的气相沉积技术可用于形成钻石层。一般的气相沉积技术包括化学气相沉积法(chemical vapordeposition，CVD)以及物理气相沉积法(physical vapor deposition，PVD)，只要有相似的特性及产生相似的结果，任何一种类似的方法皆可使用。在一种实施方式中，CVD技术，如热灯丝(hot filament)、微波电浆、氧乙炔焰，射频电浆化学气相沉积法(rf-CVD)、激光化学气相沉积法(LCVD)、金属-有机化学气相沉积法(metal-organic CVD，MOCVD)、激光剥离法(laserablation)、表面钻石涂布法(conformal diamond coating process)，以及直流电弧技术(direct current arc techniques)都可被使用。典型的CVD技术是使用气体反应物以在一层或一薄膜上沉积钻石或类钻碳。这些气体一般包含少量(即少于约5％)的含碳物质(例如甲烷)，并稀释于氢气中。各种特定的CVD工艺(包括仪器及条件)可用来形成半导体层，其皆为本技术领域所熟知。在另一实施方式中，PVD技术，例如溅镀、阴极电弧(cathodic arc)、以及热蒸镀皆可使用。此外，分子束磊晶(MBE)，原子层沉基(ALD)，及其类似方法都可附加地使用。此外，为了调整沉积材料的类型(无论是DLC、非晶钻、或纯钻石)，可使用特定的沉积条件。
在部分实施方式中，一成核增强层(nucleation enhancer layer)或碳化物形成物层可形成于基板的生长表面，以改善钻石层的品质及沉积时间。如前所述，钻石层可设置于不同材料层上，例如半导体层或反射层。在一种实施方式中，一钻石层可通过沉积适当的核心(nuclei)(例如钻石核心)于基板的钻石生长表面上，接着，利用气相沉积技术使该核心生长为一薄膜或层。在本发明另一实施方式中，一成核增强层可涂布于基板上，以促进钻石层的生长。将钻石核心设置于成核增强层上，通过CVD而生长为钻石层。
本领域的普通技术人员可了解有多种适合的材料可作为成核增强物(nucleation enhancer)。在本发明的一种实施方式中，该成核增强物的材料选自金属、金属合金、金属化合物、碳化物、碳化物形成物、以及其混合所组成的集合。在另一实施方式中，该成核增强层可为一包含碳化物形成材料的碳化物形成物层。碳化物形成物的材料可包括钨(W)、钽(Ta)、钛(Ti)、锆(Zr)、铬(Cr)、钼(Mo)、硅(Si)、以及锰(Mn)，并无限制。此外，碳化物形成物包括碳化钨(WC)、碳化硅(SiC)、碳化钛(TiC)、碳化锆(ZrC)、及其混合物。在一种具体实施方式中，该碳化物形成物可为钛(Ti)。在另一具体实施方式中，该碳化物形成物可为铬(Cr)。需了解的是，一碳化物形成物层可被用来促进钻石层、碳层、氮化硼层、或附加材料(如堆叠于前述一或多层上的散热材料)的沉积。此外，碳化物形成物层可被用来改善层与层之间的键合，然而在所有情况下，不见得都需要包括成核增强物。在一种具体实施方式中，优选的的碳化物形成物可包括Ti、W、TiW、Cr、Pt、Zr、V及其类似的材料。
成核增强层或碳化物形成物层的厚度需要相当薄才不会影响到装置的热传递性质。在一种实施方式中，这些层的厚度可小于约0.5μm。在另一实施方式中，其厚度可小于约10nm。在再一实施方式中，其厚度小于约5nm。在本发明的再一实施方式中，其厚度小于约3nm。
钻石材料具有高比例sp3键合与较高的热传导性，用来调节在散热器及半导体层间CTE不匹配。在通过气相沉积技术所产生的钻石层中，有许多方法可被用来影响钻石层中钻石的sp3含量。举例来说，在钻石沉积的初期中，降低甲烷流动速率及增加整体气压可减少碳的裂解速度，并增加氢原子的含量，因而沉积出较高百分比的sp3键合构型的碳，及增加所形成的钻石核心品质。此外，可增加钻石颗粒沉积于基板的生长表面或成核增强层的成核速率，以减少生长钻石颗粒之间的间隙。而增加成核速率的方法并无特别限制，包括施以一适当的负偏压(一般约100伏特)至生长表面；利用微细钻石膏或粉末抛光该生长表面，其可能部份地残留于生长表面；且通过以PVD或PECVD离子植入C、Si、Cr、Mn、Ti、Zr、W、Mo、Ta及其类似物，以控制生长表面的组成。PVD法通常都较CVD法的温度低，部份情况下可低于约250℃，例如大约150℃。而其它增加钻石成核的公知方法也可被使用。
在本发明的一种实施方式中，一碳层可形成一表面钻石层(conformaldiamond layer)，与传统钻石薄膜工艺比较，表面钻石涂布方法具有较多优点，其中，表面钻石涂布可广泛地用于各种基板，包括非平面基板。基板的表面生长可先于缺乏偏压的钻石生长条件中进行前处理，以形成碳膜。该钻石生长条件即为传统钻石的CVD沉积条件(未使用偏压)，以形成小于100埃的薄碳膜。前述的前处理步骤可在一生长温度中进行，例如由约200℃到约900℃，或者低于约500℃亦可进行。在不受任何理论限制前提下，碳膜可在短时间出现(如少于1小时)，且形成一氢末端基的非晶钻石。
在形成薄碳膜之后，再提供基板生长表面适当的钻石生长的条件，以形成表面钻石层。其中，钻石生长条件可为一般传统的以CVD法进行钻石生长的条件，然而，不同于传统钻石薄膜的生长，通过上述前处理步骤所产生的钻石薄膜会在无限制的生长时间下，在整个基板的生长表面上形成一表面钻石层。此外，一连续薄膜(如基本上没有晶粒边界)可生长为80nm以内。基本上无晶粒边界的钻石层，其热移动的效率比具有晶粒边界的好。
此外，在部分实施方式中，碳层可为一导电碳层，例如钻石层。许多公知多技术可形成一钻石导电层，例如将各种掺杂物掺杂于钻石层的晶格中，而此掺杂物可包括Si、B、P、N、Li、Al、Ga等元素。例如在一种实施方式中，掺杂B于钻石层中。该掺杂物也可包括含有晶格的金属粒子，以避免其影响装置的功能，例如遮蔽由LED放出的光。
各种半导体材料都可以使用于本发明的装置中。该半导体层可包括任何适合形成电子装置、半导体装置或其类似的材料。许多半导体以硅、镓、铟以及锗为材料。该半导体层的适合材料，包括：硅、碳化硅、锗化硅、砷化镓(gallium arsenide)、氮化镓(gallium nitride)、锗(germanium)、硫化锌(zinc sulfide)、磷化镓(gallium phosphide)、锑化镓(gallium antimonide)、磷化砷镓铟(gallium indium arsenide phosphide)、磷化铝(aluminum phosphide)、砷化铝(aluminum arsenide)、铝镓砷化物(aluminum gallium arsenide)、氮化镓(gallium nitride)、氮化硼(boron nitride)、氮化铝(aluminum nitride)、砷化铟(indium arsenide)、磷化铟(indium phosphide)、锑化铟(indium antimonide)、氮化铟(indium nitride)、铟镓氮化物(indium gallium nitride)及其组合，并无特别限制。然而，在一种实施方式中，半导体层可包括硅、碳化硅、砷化镓(gallium arsenide)、氮化镓(gallium nitride)、磷化镓(gallium phosphide)、氮化铝(aluminum nitride)、氮化铟(indium nitride)、铟镓氮化物(indiumgallium nitride)、铝镓氮化物(aluminum gallium nitride)或其组合的材料。在一种具体实施方式中，该半导体材料包括氮化镓。在另一具体实施方式中，该半导体材料包括氮化铝。在再一种实施方式中，半导体材料包括氮化铟。在再一种实施方式中，半导体包括(Al、Ga、In)N。
再则，半导体材料可以由公知的任何结构而构成，例如：四面体(氮化硼镓或闪锌矿)、纤维锌矿(wurtzitic)、斜方六面体(rhombohedral)、石墨(graphitic)、乱层结构(turbostratic)、热裂解(pyrolytic)、六角形(hexagonal)、非晶(amorphous)或其组合，但无特别限制。半导体层可由所属技术领域的普通技术人员通过公知方法而形成，而前述各种公知的气相沉积法可应用于此。另外，在每一沉积步骤之间，可进行表面处理方法，以使表面平坦化，以利后续的沉积，而此表面处理方法可由任何公知方法所达成，例如化学蚀刻、抛光、细磨(buffing)、研磨(grinding)等。
各种材料都可用于散热层，根据本发明的一种实施方式，在不超出本发明范畴情况下，任何材料皆可使用，可包括：铝、铜、锡、钨、镍、钛、金、银、铂、Al2O3、AlN、Si3N4、Si、玻璃及其组合与其合金、和其类似材料，包括其混合物及其合金，并无限制于此。在一种实施方式中，散热器包含铜。在另一实施方式中，散热器包含包覆镍的钻石颗粒。此外，该散热器材料可通过任何沉积技术而形成于装置上，例如在一种实施方式中，通过溅镀法将该层形成于装置上。
在形成散热层后，该层的厚度可通过增厚方法(thickening process)而增加，而此增厚方法可增加装置的热传导性，并对半导体材料提供额外的结构支撑、促进装置与其它基板的运作及附着、及其类似作用。举例来说，当散热器层增厚至能够提供适当的支撑时，则一暂时支撑基板即可由半导体装置而移除。如此，在一种实施方式中，一散热器具有可支撑半导体材料的最小厚度，以避免发生弯曲。虽然，任何增厚的方法都可以被考虑。在一种实施方式中，该金属散热器可进一步通过散热器材料及/或其它金属材料的溅镀而增厚。在另一实施方式中，该金属散热层可通过电镀一附加的金属材料于其上而增厚。该金属材料可使用原本溅镀于装置上的相同或不同的金属材料在部份实施方式中，一单层钻石颗粒可沉积于已溅镀的金属散热器层。随后，可通过溅镀增厚该金属散热器层，以使钻石颗粒嵌入至金属材料中。
【实施方式】
以下实施例是根据本发明的一种实施方式以说明制备半导体装置的各种技术。然而，需了解的是，以下实施例仅为示范或说明本发明的原理，在不违背本发明的精神及范畴下，其组成、方法以及系统的多种修改或选择可由所属领域的技术人员而设计。本发明附加的权利要求书均已涵盖此修改及配置。因此，尽管本发明已由以上所述，以下实施例将进一步详细说明本发明。
实施例1
以MOCVD法(金属有机化学气相沉积)将磊晶GaN形成于一两时蓝宝石晶圆上。接着，以三甲基镓作为Ga的来源气体，并加入氨以提供氮原子，并可以加入氢气以稀释该气体，并气化不稳定排列于晶格的Ga或N原子。一由含硅的n型掺杂物形成的多层半导体结构与由含Mg的p型掺杂物形成的蓝宝石基板形成结。该量子阱及本征层(intrinsic layer)可设于p型掺杂层及n型掺杂层之间。接着，于p型掺杂层的顶面溅镀一厚度约200nm的Ag反射层，再于此反射层上溅镀一厚度约50nm的Ti成核增强物层。
紧接着，以阴极电弧沉积法(cathodic arc deposition)将厚度约1μm的非晶钻石沉积于成核增强物层上。溅镀另一厚度约50nm的Ti成核增强物层于非晶钻石上，再溅镀一Cu金属层于其上。接着，将该装置由沉积室移出，并将其浸入一电解液中，以电镀法增厚该Cu层。之后，利用激光照射，使蓝宝石晶圆自GaN层分离，并将新裸露出的n型掺杂GaN表面溅镀Au，以作为电极。由上述方法，可形成一具有顶部及底部电极的垂直式堆叠LED装置。
实施例2
由MOCVD法(金属有机化学气相沉积法)将磊晶GaN形成于一两时蓝宝石晶圆上。以三甲基镓最为Ga的来源气体，并加入氨以供应氮原子，并可以加入氢气以稀释该气体，并气化不稳定排列于晶格中的Ga或N原子。一由含硅的n型掺杂物形成的多层半导体结构与由含Mg的p型掺杂物形成的蓝宝石晶圆形成结。该量子阱及本征层则可设于p型掺杂层及n型掺杂层之间。
在p型掺杂层的顶面，将石墨及Au共溅镀形成一反射层，其中，石墨用于降低反射层的CTE。而在此情况下，CTE可通过控制Ag/C的比例而形成分级。接着，继续涂布不含石墨的Ag于反射层，并由电镀Cu或Ag的方式以增厚Ag层。
实施例3
由MOCVD法(金属有机化学气相沉积法)将磊晶GaN形成于一两时蓝宝石晶圆上。以三甲基镓最为Ga的来源气体，并加入氨以供应氮原子，并可以加入氢气以稀释该气体，并气化不稳定排列于晶格中的Ga或N原子。一由含硅的n型掺杂物形成的多层半导体结构与由含Mg的p型掺杂物形成的蓝宝石晶圆形成结。该量子阱及本征层则可设于p型掺杂层以及n型掺杂层之间。
在p型掺杂层的顶面，将石墨及Au共溅镀形成一反射层，其中，石墨用于降低反射层的CTE。而在此情况下，CTE可通过控制Ag/C的比例而形成分级。接着，继续涂布不含石墨的Ag于反射层。将一微米级的单层钻石颗粒涂布于Ag层上，接着，再以电镀法形成一Cu层于钻石颗粒层上，而单层钻石颗粒用于更进一步减少CTE的不匹配与增加其热传导性。
实施例4
由MOCVD法(金属有机化学气相沉积法)将磊晶GaN形成于一两时蓝宝石晶圆上。以三甲基镓最为Ga的来源气体，并加入氨以供应氮原子，并可以加入氢气以稀释该气体，并气化不稳定排列于晶格中的Ga或N原子。一由含硅的n型掺杂物形成的多层半导体结构与由含Mg的p型掺杂物形成的蓝宝石晶圆形成结。该量子阱及本征层则可设于p型掺杂层及n型掺杂层之间。
在p型掺杂层的顶面溅镀一厚度为200nm的Ag反射层，接着再溅镀一Cu金属层于其上。一微米级的单层钻石颗粒形成于Cu层上，并以电镀法增厚该Cu层，以使钻石颗粒嵌入其中，降低CTE的不匹配与增加其热传导性。
实施例5
在一蓝宝石上具有GaN的LED晶圆，其利用金层(gold layer)形成金属化。再将一乙醇稀释的蜡质层涂布于该金层的顶部，接着，将尺寸为约150μm的钻石颗粒挤压于腊质层，并将未黏着于该层上的过量钻石颗粒移除。该晶圆作为一阴极，而浸于含铜的液态电解液作为阳极，接着，以电镀方式将铜覆盖于钻石颗粒上。通过激光照射将蓝宝石层移除，并将ITO电极涂布于GaN裸露表面上，除了一小部份涂布金的区域作为阳极，而该铜层作为阴极。因而该垂直式堆叠LED将电极形成于相对两侧。
实施例6
在一蓝宝石上具有多层掺杂型GaN的LED晶圆，其溅镀一Ag反射层，再形成一Ti成核增强物层。接着，利用阴极电弧法沉积一导电性的非晶钻石层于Ti层上，再于非晶钻石溅镀Cr，接着再溅镀Cu，以形成金属化。以公知电镀法增厚该Cu层，以形成铜键合的GaN。
实施例7
以MOCVD法将磊晶GaN形成在一两时蓝宝石晶圆上。接着，以三甲基镓作为Ga的来源气体，并加入氨以提供氮原子，并可以加入氢气以稀释该气体，并气化不稳定排列于晶格中的Ga或N原子。一由含硅的n型掺杂物形成的多层半导体结构与由含Mg的p型掺杂物形成的蓝宝石晶圆形成结。该量子阱及本征层可设于p型掺杂层及n型掺杂层之间。接着，于p型掺杂层的顶面溅镀一厚度约200nm的Ag反射层，再于此反射层上溅镀一厚度约50nm的Ti成核增强物层。
接着，利用阴极电弧沉积法，于成核增强物层上形成一厚度约1μm的非晶钻石，再于该非晶钻石层上溅镀形成一厚度约50nm的Ti成核增强物层，并接着溅镀Cu金属层。将该装置由沉积室中移出，将其浸于含有Ni及钻石颗粒的电解液中，并以电镀形成Ni-钻石层，其中，钻石的含量约为30Vol％。之后，由激光照射GaN层，使蓝宝石晶圆自GaN层分离。接着，将Au溅镀于新裸露出的n型掺杂GaN表面，以在一角落形成电极。由以上方法，可形成具有上端及下端电极的垂直式堆叠LED装置。
当然，应了解上述配置仅为图解本发明原理的应用。在不偏离本发明精神和范围情况下，该领域的技术人员可设计许多修饰和替代配置，且所附权利要求书将包含这些修饰和配置。于是，前文尽管已使用当前认为是本发明最实际且优选的实施例来特定地详细地在上面描述了本发明，但是显然对该领域的技术人员来说，在不违背本说明书所阐明的原理和概念的情况下可进行许多修饰，所述修饰包括尺寸、材料、形状、形式、功能和操作方式、装配和用途的变化，但不限于此。

Claims (23)

1.一种应力被调节的半导体装置，包括：
一半导体层；
一应力调节界面层，其包含一碳层，其通过一碳化物形成物键合至该半导体层；以及
一散热器，其耦合至相对于该半导体层的应力调节界面层，
其中，该应力调节界面层用于降低在该半导体层及该散热器之间的热膨胀系数差异，使其小于或等于10ppm/℃。
2.如权利要求1所述的装置，其中，该应力调节界面层用于降低在该半导体层与该散热器之间的散热系数差异，使其小于或等于5ppm/℃。
3.如权利要求1所述的装置，其中，该半导体的材料选自由硅、碳化硅、硅锗、砷化镓、氮化镓、锗、硫化锌、磷化镓、锑化镓、磷砷镓化铟、磷化铝、砷化铝、砷化铝镓、氮化镓、氮化硼、氮化铝、砷化铟、磷化铟、锑化铟、氮化铟、及其组合所组成的集合。
4.如权利要求1所述的装置，其中，该半导体的材料选自由：氮化镓、氮化铝、氮化铟、及其组合所组成的集合。
5.如权利要求1所述的装置，其中，该碳层选自由类钻碳、掺杂硼钻石、非晶钻石、结晶性钻石、多晶钻石、石墨、及其组合所组成的集合。
6.如权利要求5所述的装置，其中，该碳层具有一非晶原子结构。
7.如权利要求6所述的装置，其中，该碳层为类钻碳。
8.如权利要求1所述的装置，其中，该碳层具有导电性。
9.如权利要求1所述的装置，其中，该散热器选自由铝、铜、锡、钨、镍、钛、金、银、铂、Al2O3、AlN、Si3N4、Si、玻璃、及其组合、及其合金所组成的集合。
10.如权利要求1所述的装置，其中，该散热器包含铜。
11.如权利要求1所述的装置，还包括一反射层，其耦合至该应力调节界面层。
12.如权利要求1所述的装置，还包括一碳化物形成物，其设置于该应力调节碳层与该散热器层之间。
13.一种应力被调节的半导体装置，包括：
一半导体层；以及
一散热器，其形成于该半导体层上，该散热层包括均匀地设置在一金属基质中的多个钻石颗粒，其中，该钻石颗粒用于降低在该半导体层以及该金属基质之间的热膨胀系数差异，使其小于或等于10ppm/℃。
14.如权利要求13所述的装置，其中，该钻石颗粒用于降低在该半导体层以及该金属基质之间的热膨胀系数差异，使其小于或等于5ppm/℃。
15.如权利要求13所述的装置，其中，该钻石颗粒是以一单层设置于该金属基质中。
16.如权利要求13所述的装置，其中，该钻石颗粒以小于或等于60体积百分比的比例均匀地分散于该金属基质中。
17.一种应力被调节的半导体装置，包括：
一半导体层；
一导电氮化硼层，其形成于该半导体层上；以及
一散热器，其耦合至相对于该半导体层的该氮化硼层，其中，该氮化硼层用于降低在该半导体层及该散热器之间的热膨胀系数差异，使其小于或等于10ppm/℃。
18.一种降低导致半导体装置内缺陷的应力的方法，包括：
形成包含一碳层的一应力调节界面层至一半导体层上；
将一散热器层耦合至相对于该半导体层的该碳层，其中，该应力调节界面层用于降低在该半导体层及该散热器之间的热膨胀系数差异，使其小于或等于10ppm/℃。
19.如权利要求18所述的方法，还包括在该碳层及该半导体层之间形成一碳化物形成物层。
20.如权利要求18所述的方法，还包括在该碳层及该散热层之间形成一碳化物形成物。
21.如权利要求18所述的方法，其中，该散热器耦合至该碳层的方法包括将该散热器形成至该碳层上。
22.一种应力被调节的发光半导体装置，包括：
一发光半导体材料；
一碳层，其形成于该半导体材料上；以及
一金属散热器，其耦合至该碳层，其中，该碳层用于降低在该半导体层及该金属散热器之间的热膨胀系数差异，使其小于或等于10ppm/℃。
23.如权利要求22所述的装置，其中，该金属散热器形成在该碳层上。
CN2011800061052A 2010-10-29 2011-10-29 应力被调节的半导体装置及其相关方法 Pending CN102893419A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105322063A (zh) * 2014-06-30 2016-02-10 新世纪光电股份有限公司 半导体结构
CN108417672A (zh) * 2018-02-01 2018-08-17 华灿光电(苏州）有限公司 一种发光二极管外延片及其制备方法
US10229977B2 (en) 2016-09-19 2019-03-12 Genesis Photonics Inc. Nitrogen-containing semiconductor device
CN112087859A (zh) * 2019-06-12 2020-12-15 钰桥半导体股份有限公司 具有防渗基座及嵌入构件的线路板及其半导体组体

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2789972B1 (de) 2013-04-12 2017-08-16 Hexagon Technology Center GmbH Vermessungsgerät mit verformbarem optischem Element
SG10201503260YA (en) * 2015-04-24 2016-11-29 Wangi Ind Co Pte Ltd A Substantially Transparent Coating
JP7240511B2 (ja) * 2019-09-02 2023-03-15 株式会社東芝 接合体

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020023733A1 (en) * 1999-12-13 2002-02-28 Hall David R. High-pressure high-temperature polycrystalline diamond heat spreader
US20050287766A1 (en) * 2004-06-24 2005-12-29 Chrysler Gregory M Wafer-level diamond spreader
US20070269964A1 (en) * 2006-05-22 2007-11-22 Chien-Min Sung Semiconductor-on-diamond devices and associated methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100634538B1 (ko) * 2005-02-05 2006-10-13 삼성전자주식회사 효율적인 냉각 구조를 갖는 반도체 발광 소자 및 그 제조방법
TWI298555B (en) * 2006-06-05 2008-07-01 Epistar Corp Light emitting device
JP2008263126A (ja) * 2007-04-13 2008-10-30 Oki Data Corp 半導体装置、該半導体装置の製造方法、ｌｅｄヘッド、及び画像形成装置
JP4458116B2 (ja) * 2007-05-30 2010-04-28 住友電気工業株式会社 エピタキシャル層成長用ｉｉｉ族窒化物半導体層貼り合わせ基板および半導体デバイス
EP2398081B1 (en) * 2009-02-13 2018-05-09 Denka Company Limited Composite substrate for led light emitting element, method of production of same, and led light emitting element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020023733A1 (en) * 1999-12-13 2002-02-28 Hall David R. High-pressure high-temperature polycrystalline diamond heat spreader
US20050287766A1 (en) * 2004-06-24 2005-12-29 Chrysler Gregory M Wafer-level diamond spreader
US20070269964A1 (en) * 2006-05-22 2007-11-22 Chien-Min Sung Semiconductor-on-diamond devices and associated methods

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105322063A (zh) * 2014-06-30 2016-02-10 新世纪光电股份有限公司 半导体结构
CN105322063B (zh) * 2014-06-30 2019-06-04 新世纪光电股份有限公司 半导体结构
US10229977B2 (en) 2016-09-19 2019-03-12 Genesis Photonics Inc. Nitrogen-containing semiconductor device
CN108417672A (zh) * 2018-02-01 2018-08-17 华灿光电(苏州）有限公司 一种发光二极管外延片及其制备方法
CN108417672B (zh) * 2018-02-01 2019-07-19 华灿光电(苏州）有限公司 一种发光二极管外延片及其制备方法
CN112087859A (zh) * 2019-06-12 2020-12-15 钰桥半导体股份有限公司 具有防渗基座及嵌入构件的线路板及其半导体组体
CN112087859B (zh) * 2019-06-12 2024-08-30 钰桥半导体股份有限公司 具有防渗基座及嵌入构件的线路板及其半导体组体

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