CN102882514B - AND logic circuit and chip - Google Patents
AND logic circuit and chip Download PDFInfo
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- CN102882514B CN102882514B CN201210380759.8A CN201210380759A CN102882514B CN 102882514 B CN102882514 B CN 102882514B CN 201210380759 A CN201210380759 A CN 201210380759A CN 102882514 B CN102882514 B CN 102882514B
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Abstract
The embodiment of the invention discloses an AND logic circuit and a chip. The circuit comprises a resistance change memristor array and comparators; the non-inverting input ends of the same line of resistance change memristors in the resistance change memristor array are connected with one another, so that the non-inverting input ends of the same line of the resistance change memristors serve as a signal input end or an auxiliary signal input end of the AND logic circuit; the auxiliary signal input end is connected to a low level when working; inverting input ends of the same row of resistance change memristors in the resistance change memristor array are connected with the input end of a comparator, so that the output end of the comparator serves as a signal output end of the AND logic circuit; when the voltage received by the input end of the comparator is greater than a threshold voltage, the output end of the comparator outputs a high level; and when the voltage received by the input end of the comparator is lower than the threshold voltage, the output end of the comparator outputs the low level. By the embodiment of the invention, the area occupied by the AND logic circuit is saved and simultaneously the programmable performance of the AND logic circuit is realized.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to and logical circuit and chip.
Background technology
With logical circuit usually based on Metal-oxide-semicondutor (MOS; Metal-Oxide-Semiconductor) pipe memory device; along with the requirement of chip integration is more and more higher; with the size of logical circuit also in continuous reduction; but due to the restriction of the size of metal-oxide-semiconductor memory device own, the therefore technology node that there is minimum dimension with logical circuit of the prior art.
Summary of the invention
Provide in the embodiment of the present invention and logical circuit and chip, in order to solve the problem that there is the technology node of minimum dimension with logical circuit existed in prior art.
For solving the problem, the embodiment of the invention discloses following technical scheme:
On the one hand, provide one and logical circuit, comprising: resistive memristor array and comparator; In described resistive memristor array, the normal phase input end of same row resistive memristor is connected, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level; Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator, to make the output of described comparator as the described signal output part with logical circuit; When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator.
Preferably, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
Preferably, described resistive memristor comprises: resistance-variable storing device (RRAM, Resistive Random AccessMemory) or phase transition storage (PRAM, Phase-Change Random Access Memory) or ferroelectric memory (FRAM, ferroelectric Random Access Memory) or magnetic memory (MRAM, Magnetic RandomAccess Memory).
On the one hand, provide a kind of chip, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit; Describedly to comprise with logical circuit: resistive memristor array and comparator; In described resistive memristor array, the normal phase input end of same row resistive memristor is connected by described top electrode bonding jumper, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level; Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator by described hearth electrode bonding jumper, to make the output of described comparator as the described signal output part with logical circuit; When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator.
Preferably, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
Preferably, described resistive memristor comprises: RRAM or PRAM or FRAM or MRAM.
That the embodiment of the present invention provides and logical circuit, traditional metal-oxide-semiconductor memory device is not adopted completely in its circuit is formed, but part have employed this novel memory devices part with two-end structure of resistive memristor, due to resistive memristor has can good, the feature such as storage density is high, low in energy consumption, read or write speed fast, repeatable operation tolerance is strong, data hold time is long of contractility, therefore effectively saving and while logical circuit area occupied, achieving the programmable performance with logical circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 be in one embodiment of the invention with the schematic diagram of logical circuit;
Fig. 2 is that the resistance state of resistive memristor array in one embodiment of the invention arranges schematic diagram;
Fig. 3 a is the curve chart that the conductivity of monopole type resistive memristor increases with voltage;
Fig. 3 b is the curve chart that the conductivity of monopole type resistive memristor reduces with voltage;
Fig. 4 is the curve chart of conductivity with change in voltage of ambipolar resistive memristor.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, carry out clear, complete description to the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, in one embodiment of the invention with the schematic diagram of logical circuit.
Can should comprise with logical circuit, resistive memristor array 10 and comparator 11.In resistive memristor array 10, the normal phase input end of same row resistive memristor 101 is connected, to make the normal phase input end of same row resistive memristor 101 as the signal input part or auxiliary signal input with logical circuit, low level is connected to during the work of auxiliary signal input, signal input part is for receiving low level or high level signal, specifically may be used for receiving in a predetermined number N bit digital input signal (Din), N is positive integer, above-mentioned predetermined number can set as the case may be, be only that example is described for what realize that two N bit digital input signals carry out step-by-step phase and computing with logical circuit in the embodiment of the present invention, be connected with the input of a comparator 11 with the inverting input of a line resistive memristor 101 in resistive memristor array 10, to make the output of comparator 11 as the signal output part with logical circuit, this signal output part is used for output low level or high level signal, specifically may be used for exporting in N bit digital output signal (Dout).
Wherein, resistive memristor 101 is two terminal device, and with reference to Fig. 1, the upper end of resistive memristor 101 is normal phase input end, and the lower end of resistive memristor 101 is inverting input.
In the embodiment of the present invention, when the voltage that the input of comparator 11 receives is greater than threshold voltage, the output of comparator 11 exports high level, correspondingly, exports high level with the signal output part of logical circuit, i.e. digital signal " 1 "; When the voltage that the input of comparator 11 receives is less than threshold voltage, the output output low level of comparator 11, correspondingly, with the signal output part output low level of logical circuit, i.e. digital signal " 0 ".Wherein, comparator 11 can be realized by various ways, and the present invention is not specifically limited.
When with logical circuit be used for realizing two N bit digital input signals carry out step-by-step phase and computing time, it is N that resistive memristor array 10 can form line number, columns is the array of 3N, the normal phase input end of each row resistive memristor 101 is as an input port, total 3N input port, wherein, be 2N with the signal input part of logical circuit, be N number of with the auxiliary signal input of logical circuit, in advance two signal input parts and an auxiliary signal input are divided into one group, two signal input parts of same group are for receiving the same position of two digital input signals, in the embodiment of the present invention with logical circuit for realize two digital input signals step-by-step phases and function, such as, Din1 and Din2 is respectively with two digital input signals of logical circuit, digital output signal is Dout, digital input signals and everybody corresponding relation of digital output signal can be as shown in Table 1.
Table one:
| Din1 | A1 | A2 | … | AN |
| Din2 | B1 | B2 | … | BN |
| Dout | A1 and B1 | A2 and B2 | … | AN and BN |
With reference to Fig. 1, in the embodiment of the present invention, can every three input ports be divided in one group, each input port order can be divided into N group thus, an input port often in group is as auxiliary signal input, such as, using first input port in every group as auxiliary signal input, when working with logical circuit, auxiliary signal input is connected low level, be specifically as follows digital signal " 0 ", often in group all the other two input ports as signal input part, for receiving the same position of two digital input signals, such as, for first B1 of first A1 and digital input signals Din2 that receive digital input signals Din1.
The resistive memristor 101 that the embodiment of the present invention adopts can have two kinds of resistance states: high value resistance state and low resistance resistance state.With there being three resistive memristors being in low resistance resistance state in the resistive memristor 101 of a line in resistive memristor array 10, and, in resistive memristor array 10 same row resistive memristor 101 in have a resistive memristor being in low resistance resistance state.Can be specifically in resistive memristor array 10 position at the (n+1)th row 3n+1, 3n+2, the resistive memristor of 3n+3 row is in low resistance resistance state, wherein n value from 0, such as, as n=0, known position arranges at the 1st row the 1st, 1st row the 2nd arranges and three resistive memristors of the 1st row the 3rd row are in low resistance resistance state, specifically can with reference to arranging schematic diagram with the resistance state of logical circuit and carry out resistance state setting to each resistive memristor shown in Fig. 2, wherein, the resistive memristor that resistance state is in low resistance resistance state represents with inner blank rectangle frame, to distinguish over the resistive memristor that resistance state is in high value resistance state.
With logical circuit work before, can according to the grouping of input port, first each resistive memristor 101 in resistive memristor array 10 is programmed, above-mentioned programming is set to low resistance resistance state or high value resistance state by each resistive memristor 101, by programming resistive memristor 101 low resistance resistance state or high value resistance state can be set to due to of the present invention with logical circuit, therefore of the present inventionly able to programme and logical circuit can be called with logical circuit.
Resistive memristor 101 has resistance state memory function, when the voltage of resistive memristor 101 two ends applying is lower than threshold voltage, the resistance state of resistive memristor 101 remains unchanged, when the voltage of resistive memristor 101 two ends applying is higher than threshold voltage, the resistance state of resistive memristor 101 just may change.Therefore the operating voltage of resistive memristor 101 should be less than threshold voltage; Correspondingly, the program voltage of resistive memristor 101 should be greater than threshold voltage, and above-mentioned program voltage refers to the voltage applied at resistive memristor 101 two ends when programming to resistive memristor 101.
Of the present inventionly can to comprise with the using forestland of logical circuit: programming mode and mode of operation.When being in programming mode with logical circuit, the size of the program voltage applied at the two ends of resistive memristor 101 should exceed the threshold voltage of resistive memristor 101, because the number of the resistive memristor 101 comprised in resistive memristor array 10 may be a lot, such as, when with logical circuit for realize two 8 bit digital input signal step-by-step phases and function time, resistive memristor array 10 has 8 auxiliary signal inputs, 16 signal input parts and 8 signal output parts, 112 resistive memristors 101 can be included in resistive memristor array 10, when programming respectively to each resistive memristor 101 in resistive memristor array 10, efficiency is lower, and, in resistive memristor array 10, most of resistive memristor 101 all should be arranged to high value resistance state, therefore first programming can be unified to all resistive memristors 101 in resistive memristor array 10, namely all resistive memristors 101 are made all to be in high value resistance state by unified programming, and then the resistive memristor 101 should being arranged to low resistance resistance state of minority is individually programmed, namely the part resistive memristor 101 after unified programming is made to be in low resistance resistance state by programming separately.
Above-mentioned to resistive memristor 101 unify programming time, can using with the input port of the logical circuit normal phase input end as program voltage, using the inverting input of the inverting input of each resistive memristor 101 as program voltage, such as, can using the inverting input of the reserved port of a row in left side in Fig. 1 as program voltage.
It is above-mentioned when resistive memristor 101 is programmed separately, can using the normal phase input end of the input port of this resistive memristor 101 column as program voltage, using the inverting input of the inverting input of this resistive memristor 101 as program voltage, also the inverting input of inverting input as program voltage of each resistive memristor 101 of same a line can be in resistive memristor array 10 with this resistive memristor 101, such as, the reserved port this resistive memristor 101 in Fig. 1 can be expert at is as the inverting input of program voltage.
In the embodiment of the present invention, resistive memristor 101 can be monopole type resistive memristor, also can be ambipolar resistive memristor, when programming to resistive memristor 101, the size of program voltage can be chosen according to the single, double pole characteristic of resistive memristor 101.
With reference to the curve chart of monopole type resistive memristor conductivity in Fig. 3 a and Fig. 3 b with change in voltage, when resistive memristor 101 is monopole type resistive memristor, low resistance resistance state threshold voltage Vset and high value resistance state threshold voltage Vreset is positive voltage, when unifying programming to resistive memristor 101, owing to all resistive memristors 101 will be set to high value resistance state, therefore the first program voltage V1 should meet: Vset>V1>Vreset, in such resistive memristor array 10, all resistive memristors 101 are all set to high value resistance state, when then programming separately respectively for each resistive memristor 101 that should be set to low resistance resistance state in resistive memristor array 10, the second program voltage V2 should meet: V2>Vset.
With reference to the curve chart of ambipolar resistive memristor conductivity in Fig. 4 with change in voltage, when resistive memristor 101 is ambipolar resistive memristor, low resistance resistance state threshold voltage Vset is positive voltage, high value resistance state threshold voltage Vreset is negative voltage, when unifying programming to resistive memristor 101, owing to all resistive memristors 101 will be set to high value resistance state, therefore can by the positive input end grounding of program voltage, and anti-phase input termination the 3rd program voltage V3 of program voltage, V3 should meet: V3>|Vreset|, in such resistive memristor array 10, all resistive memristors 101 are all set to high value resistance state, when then programming separately respectively for each resistive memristor 101 that should be set to low resistance resistance state in resistive memristor array 10, can by the reverse inter-input-ing ending grounding of program voltage, and the normal phase input end of program voltage meets the 4th program voltage V4, and V4>Vset.
Corresponding function can be selected as required to logical circuit, except the step-by-step phase for realizing two digital input signals with, the step-by-step phase that can also be used for realizing more digital input signals with, because specific implementation is similar, repeat no more in the embodiment of the present invention.
There are high value and low resistance two kinds of resistance states in resistive memristor 101, when the resistance difference under two kinds of resistance states is larger, resistive memristor 101 can be regarded as there is open and close two states, when resistive memristor 101 two ends that two are in different resistance state apply the voltage of formed objects, be in the resistive memristor of low resistance resistance state and have very large electric current, be in the resistive memristor of high value resistance state and almost do not have electric current, therefore resistive memristor 101 has the characteristic selecting conducting; Resistive memristor 101 also has an important characteristic, resistive memristor 101 has good resistance consistency when being in low resistance resistance state, namely the resistance approximately equal of two resistive memristors of low resistance resistance state is in, such as, the resistance of a low resistance resistance state resistive memristor 101 is represented with Ron1, the resistance of another low resistance resistance state resistive memristor 101 is represented, then Ron1 ≈ Ron2 with Ron2.In the embodiment of the present invention, make use of above-mentioned two kinds of characteristics of resistive memristor 101, then the step-by-step phase achieving two digital input signals in conjunction with comparator 11 with.
For convenience, in the embodiment of the present invention, the voltage that the input of comparator receives is called input voltage, represent with Vin, the threshold voltage of comparator represents with Vref, if Vin>Vref, then the output of comparator exports high level, i.e. digital signal " 1 ", if Vin<Vref, then the output output low level of comparator, i.e. digital signal " 0 ", Vref here can be set to 1/2 of operating voltage VDD.
Below in conjunction with Fig. 2, the operation principle of the present invention and logical circuit is analyzed: time in running order with logical circuit, in resistive memristor array, every a line only has three resistive memristors to be in low resistance resistance state (i.e. ON state), such as, in Fig. 2, the first row of resistive memristor array only has resistive memristor 201, resistive memristor 202 and resistive memristor 203 are in low resistance resistance state, all the other resistive memristors are in high value resistance state (i.e. OFF state), so the input voltage vin of signal to the comparator that this row connects on the input port only having these three the resistive memristors being in low resistance resistance state to connect has contribution.In the first row of resistive memristor array, resistive memristor 201 connects auxiliary signal input, when working with logical circuit, auxiliary signal input connects digital signal " 0 ", i.e. low level VL, resistive memristor 202 and resistive memristor 203 connection signal input, signal input part needs to carry out the same position with two of computing digital input signals for receiving.For convenience of description, resistive memristor 201, resistive memristor 202 and resistive memristor 203 and resistance thereof are represented with Ron1, Ron2 and Ron3 respectively, the operating voltage supposing this and logical circuit is VDD, i.e. high level VH=VDD, the input voltage of comparator represents with Vin.Two digits input signal A1 and B1 received when signal input part is " 1 ", namely during high level VH, connect with Ron1 after being equivalent to Ron2 and Ron3 parallel connection, Vin is Ron2//Ron3 and Ron1 partial pressure value, wherein, symbol " Ron2//Ron3 " represents the resistance after Ron2 and Ron3 parallel connection, by Ron1 ≈ Ron2 ≈ Ron3, obtain Ron2//Ron3 ≈ 1/2Ron1, Vin ≈ 2/3VDD>Vref=1/2VDD, so comparator goes out high level, i.e. digital signal " 1 "; Two input signal A1 and B1 received when signal input part are " 0 ", namely, during low level VL, three resistive memristors Ron1, Ron2 and Ron3 are equivalent in parallel, Vin ≈ VL ≈ 0<Vref=1/2VDD, comparator output low level, i.e. digital signal " 0 "; When having one in two digits input signal A1 and B1 that signal input part receives for " 1 ", i.e. high level VH, another is " 0 ", namely during low level VL, such as, signal B1 on Ron3 is high level, signal A1 on Ron2 is low level, connect with Ron3 after being equivalent to Ron2 and Ron1 parallel connection, Vin is Ron1//Ron2 and Ron3 partial pressure value, by Ron1 ≈ Ron2 ≈ Ron3, obtain Ron1//Ron2 ≈ 1/2Ron1, Vin ≈ 1/3VDD<Vref=1/2VDD, so comparator output low level, i.e. digital signal " 0 ".As from the foregoing, only have when A1 and B1 is high level, corresponding signal output part just exports high level, thus realize with logical circuit to two input signal step-by-step phases and function.Identical with the operation principle of the first row with the operation principle of all the other each row in logical circuit, in the embodiment of the present invention, this is no longer analyzed.
In addition, above-mentioned resistive memristor can be any one in RRAM, PRAM, FRAM and MRAM.
That the embodiment of the present invention provides and logical circuit, traditional metal-oxide-semiconductor memory device is not adopted completely in its circuit is formed, but have employed this novel memory devices part with two-end structure of resistive memristor, due to resistive memristor has can good, the feature such as storage density is high, low in energy consumption, read or write speed fast, repeatable operation tolerance is strong, data hold time is long of contractility, therefore effectively saving and while logical circuit area occupied, achieving the programmable performance with logical circuit.
The embodiment of the present invention additionally provides a kind of chip, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit.Comprise with logical circuit: resistive memristor array and comparator, wherein, in resistive memristor array, the normal phase input end of same row resistive memristor is connected by top electrode bonding jumper, to make the normal phase input end of same row resistive memristor as the signal input part or auxiliary signal input with logical circuit, low level is connected to during the work of auxiliary signal input, be connected by the input of hearth electrode bonding jumper with a comparator with the inverting input of a line resistive memristor in resistive memristor array, to make the output of comparator as the signal output part with logical circuit.
Wherein, when the voltage that the input of comparator receives is greater than threshold voltage, the output of comparator exports high level, when the voltage that the input of comparator receives is less than threshold voltage, and the output output low level of comparator.
Preferably, two signal input parts and an auxiliary signal input as one group, to make same group two signal input parts for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state; With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor; And described resistive memristor comprises: RRAM or PRAM or FRAM or MRAM.
In the embodiment of the present invention, in order to reduce the size of chip as far as possible, top electrode bonding jumper and hearth electrode bonding jumper can arrange in square crossing, a resistive memristor is formed at each crosspoint place, such as, resistive memristor is adopt to be formed in the mode of top electrode bonding jumper and hearth electrode bonding jumper crosspoint place filling resistive medium.
In addition, top electrode bonding jumper can be arranged at metal levels different in chip respectively from hearth electrode bonding jumper, such as, and adjacent two metal layers.
In the embodiment of the present invention, due to resistive memristor and complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal Oxide Semiconductor) process compatible, therefore the manufacture craft of chip is simple.
The chip that the embodiment of the present invention provides, include top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit, traditional metal-oxide-semiconductor memory device is not adopted completely in its circuit is formed, but part have employed this novel memory devices part with two-end structure of resistive memristor, due to resistive memristor have can contractility good, storage density is high, low in energy consumption, read or write speed is fast, repeatable operation tolerance is strong, the features such as data hold time is long, therefore while effective saving with logical circuit area occupied, achieve the programmable performance with logical circuit, reduce the size of chip accordingly, and improve the performance of chip.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the embodiment of the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the embodiment of the present invention, can realize in other embodiments.Therefore, the embodiment of the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
The foregoing is only the preferred embodiment of the embodiment of the present invention; not in order to limit the embodiment of the present invention; within all spirit in the embodiment of the present invention and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the embodiment of the present invention.
Claims (8)
1. and a logical circuit, it is characterized in that, comprising: resistive memristor array and comparator;
In described resistive memristor array, the normal phase input end of same row resistive memristor is connected, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level;
Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator, to make the output of described comparator as the described signal output part with logical circuit;
When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator;
Wherein, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.
2. as claimed in claim 1 and logical circuit, it is characterized in that, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.
3. as claimed in claim 1 and logical circuit, it is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
4. as claimed in claim 1 and logical circuit, it is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.
5. a chip, is characterized in that, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit;
Describedly to comprise with logical circuit: resistive memristor array and comparator;
In described resistive memristor array, the normal phase input end of same row resistive memristor is connected by described top electrode bonding jumper, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level;
Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator by described hearth electrode bonding jumper, to make the output of described comparator as the described signal output part with logical circuit;
When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator;
Wherein, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.
6. chip as claimed in claim 5, it is characterized in that, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.
7. chip as claimed in claim 5, it is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
8. chip as claimed in claim 5, it is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.
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| WO2015139207A1 (en) | 2014-03-18 | 2015-09-24 | 华为技术有限公司 | Method, apparatus and device for operating logical operation array of resistive random access memory |
| GB2554861B (en) * | 2016-10-04 | 2021-09-15 | Univ Oxford Brookes | Sensor |
| EP4133599A4 (en) * | 2020-04-07 | 2024-05-15 | Technion Research & Development Foundation Limited | Logic gates and stateful logic using phase change memory |
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| CN101783183A (en) * | 2009-01-21 | 2010-07-21 | 中国科学院微电子研究所 | Current limiting circuit for testing performance index of resistive random access memory |
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| CN102882514A (en) | 2013-01-16 |
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