CN102882514A - AND logic circuit and chip - Google Patents
AND logic circuit and chip Download PDFInfo
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- CN102882514A CN102882514A CN2012103807598A CN201210380759A CN102882514A CN 102882514 A CN102882514 A CN 102882514A CN 2012103807598 A CN2012103807598 A CN 2012103807598A CN 201210380759 A CN201210380759 A CN 201210380759A CN 102882514 A CN102882514 A CN 102882514A
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Abstract
The embodiment of the invention discloses an AND logic circuit and a chip. The circuit comprises a resistance change memristor array and comparators; the non-inverting input ends of the same line of resistance change memristors in the resistance change memristor array are connected with one another, so that the non-inverting input ends of the same line of the resistance change memristors serve as a signal input end or an auxiliary signal input end of the AND logic circuit; the auxiliary signal input end is connected to a low level when working; inverting input ends of the same row of resistance change memristors in the resistance change memristor array are connected with the input end of a comparator, so that the output end of the comparator serves as a signal output end of the AND logic circuit; when the voltage received by the input end of the comparator is greater than a threshold voltage, the output end of the comparator outputs a high level; and when the voltage received by the input end of the comparator is lower than the threshold voltage, the output end of the comparator outputs the low level. By the embodiment of the invention, the area occupied by the AND logic circuit is saved and simultaneously the programmable performance of the AND logic circuit is realized.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to and logical circuit and chip.
Background technology
With logical circuit usually based on Metal-oxide-semicondutor (MOS; Metal-Oxide-Semiconductor) pipe memory device; along with the requirement of chip integration is more and more higher; also constantly reducing with the size of logical circuit; but because the restriction of metal-oxide-semiconductor memory device size itself, therefore of the prior art and logical circuit exists the technology node of minimum dimension.
Summary of the invention
Provide in the embodiment of the invention and logical circuit and chip, in order to solve exist in the prior art exist the problem of the technology node of minimum dimension with logical circuit.
For addressing the above problem, the embodiment of the invention discloses following technical scheme:
On the one hand, provide a kind of and logical circuit, having comprised: resistive memristor array and comparator; The normal phase input end of same row resistive memristor is connected in the described resistive memristor array, so that the normal phase input end of described same row resistive memristor as described and signal input part or auxiliary signal input logical circuit, is connected to low level during described auxiliary signal input work; Inverting input with delegation's resistive memristor in the described resistive memristor array is connected with the input of a described comparator, so that the output of described comparator is as described and signal output part logical circuit; The voltage that the input of described comparator receives is during greater than threshold voltage, and the output of described comparator output high level, the voltage that the input of described comparator receives be during less than threshold voltage, the output output low level of described comparator.
Preferably, two described signal input parts and a described auxiliary signal input are as one group, so that two described signal input parts of same group are used for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor with delegation in the described resistive memristor array; And, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor of same row in the described resistive memristor array.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
Preferably, described resistive memristor comprises: resistance-variable storing device (RRAM, Resistive Random AccessMemory) or phase transition storage (PRAM, Phase-Change Random Access Memory) or ferroelectric memory (FRAM, ferroelectric Random Access Memory) or magnetic memory (MRAM, Magnetic Random Access Memory).
On the one hand, provide a kind of chip, having comprised: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit; Described and logical circuit comprises: resistive memristor array and comparator; The normal phase input end of same row resistive memristor is connected by described top electrode bonding jumper in the described resistive memristor array, so that the normal phase input end of described same row resistive memristor as described and signal input part or auxiliary signal input logical circuit, is connected to low level during described auxiliary signal input work; Inverting input with delegation's resistive memristor in the described resistive memristor array is connected with the input of a described comparator by described hearth electrode bonding jumper, so that the output of described comparator is as described and signal output part logical circuit; The voltage that the input of described comparator receives is during greater than threshold voltage, and the output of described comparator output high level, the voltage that the input of described comparator receives be during less than threshold voltage, the output output low level of described comparator.
Preferably, two described signal input parts and a described auxiliary signal input are as one group, so that two described signal input parts of same group are used for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor with delegation in the described resistive memristor array; And, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor of same row in the described resistive memristor array.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
Preferably, described resistive memristor comprises: RRAM or PRAM or FRAM or MRAM.
That the embodiment of the invention provides and logical circuit, in consisting of, its circuit do not adopt traditional metal-oxide-semiconductor memory device fully, but part has adopted this novel memory device with two-end structure of resistive memristor, but contractility is good, storage density is high because the resistive memristor has, low in energy consumption, the characteristics such as read or write speed fast, the repeatable operation tolerance is strong, data hold time length, therefore in effective saving and logical circuit area occupied, realized and the programmable performance of logical circuit.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use among the embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is in the one embodiment of the invention and schematic diagram logical circuit;
Fig. 2 is that the resistance state of the resistive memristor array in the one embodiment of the invention arranges schematic diagram;
Fig. 3 a is the curve chart that the conductivity of monopole type resistive memristor increases with voltage;
Fig. 3 b is the curve chart that the conductivity of monopole type resistive memristor reduces with voltage;
Fig. 4 is that the conductivity of ambipolar resistive memristor is with the curve chart of change in voltage.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is carried out clear, complete description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
As shown in Figure 1, be in the one embodiment of the invention and schematic diagram logical circuit.
Resistive memristor array 10 and comparator 11 should can be comprised with logical circuit.The normal phase input end of same row resistive memristor 101 is connected in the resistive memristor array 10, so that the normal phase input end of same row resistive memristor 101 as with signal input part or the auxiliary signal input of logical circuit, be connected to low level during the work of auxiliary signal input, signal input part is used for receiving low level or high level signal, specifically can be for of a reception predetermined number N bit digital input signal (Din), N is positive integer, above-mentioned predetermined number can be set as the case may be, in the embodiment of the invention only take describing as example with logical circuit of be used for realizing that two N bit digital input signals carry out step-by-step phase and computing, inverting input with delegation's resistive memristor 101 in the resistive memristor array 10 is connected with the input of a comparator 11, so that the output of comparator 11 as with the signal output part of logical circuit, this signal output part is used for output low level or high level signal, specifically can be used for of output N bit digital output signal (Dout).
Wherein, resistive memristor 101 is two terminal device, and with reference to Fig. 1, the upper end of resistive memristor 101 is normal phase input end, and the lower end of resistive memristor 101 is inverting input.
In the embodiment of the invention, the voltage that the input of comparator 11 receives is during greater than threshold voltage, the output of comparator 11 output high level, correspondingly, with signal output part output high level, the i.e. digital signal " 1 " of logical circuit; The voltage that the input of comparator 11 receives is during less than threshold voltage, the output output low level of comparator 11, correspondingly, and with the signal output part output low level of logical circuit, i.e. digital signal " 0 ".Wherein, comparator 11 can be realized that by various ways the present invention is not specifically limited.
When being used for realizing that two N bit digital input signals carry out step-by-step phase and computing with logical circuit, it is N that resistive memristor array 10 can form line number, columns is the array of 3N, the normal phase input end of each row resistive memristor 101 is as an input port, total 3N input port, wherein, with the signal input part of logical circuit be 2N, with the auxiliary signal input of logical circuit be N, in advance two signal input parts and an auxiliary signal input are divided into one group, two signal input parts of same group are used for receiving the same position of two digital input signals, in the embodiment of the invention with logical circuit be used for to realize two digital input signals step-by-step phases and function, for example, be respectively Din1 and Din2 with two digital input signals of logical circuit, digital output signal is Dout, and everybody corresponding relation of digital input signals and digital output signal can be as shown in Table 1.
Table one:
| Din1 | A1 | A2 | … | AN |
| Din2 | B1 | B2 | … | BN |
| Dout | A1 and B1 | A2 and B2 | … | AN and BN |
With reference to Fig. 1, in the embodiment of the invention, per three input ports can be divided in one group, each input port sequentially can be divided into thus the N group, an input port in every group is as the auxiliary signal input, for example, with first input port in every group as the auxiliary signal input, the auxiliary signal input is connected low level when working with logical circuit, be specifically as follows digital signal " 0 ", all the other two input ports are used for receiving the same position of two digital input signals as signal input part in every group, for example, be used for to receive first A1 of digital input signals Din1 and first B1 of digital input signals Din2.
The resistive memristor 101 that the embodiment of the invention adopts can have two kinds of resistance states: high value resistance state and low resistance resistance state.Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor 101 with delegation in the resistive memristor array 10, and, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor 101 of same row in the resistive memristor array 10.Specifically can be in the resistive memristor array 10 position at the capable 3n+1 of n+1,3n+2, the resistive memristor of 3n+3 row is in the low resistance resistance state, wherein n is since 0 value, for example, when n=0, the position is at the 1st row the 1st row as can be known, three resistive memristors of the 1st row the 2nd row and the 1st row the 3rd row are in the low resistance resistance state, specifically can with resistance state logical circuit schematic diagram be set and come each resistive memristor is carried out the resistance state setting with reference to shown in Figure 2, wherein, the resistive memristor that resistance state is in the low resistance resistance state represents with inner blank rectangle frame, is in the resistive memristor of high value resistance state to distinguish over resistance state.
With logical circuit work before, can be according to the grouping of input port, first each the resistive memristor 101 in the resistive memristor array 10 is programmed, above-mentioned programming is about to each resistive memristor 101 and is set to low resistance resistance state or high value resistance state, because of the present invention and logical circuit can be set to low resistance resistance state or high value resistance state with resistive memristor 101 by programming, therefore of the present invention and logical circuit can be called able to programme and logical circuit.
Of the present invention and use pattern logical circuit can comprise: programming mode and mode of operation.When being in programming mode with logical circuit, the size of the program voltage that applies at the two ends of resistive memristor 101 should surpass the threshold voltage of resistive memristor 101, because the number of the resistive memristor 101 that comprises in the resistive memristor array 10 may be a lot, for example, when with logical circuit be used for to realize two 8 bit digital input signal step-by-step phases and function the time, resistive memristor array 10 has 8 auxiliary signal inputs, 16 signal input parts and 8 signal output parts, can include 112 resistive memristors 101 in the resistive memristor array 10, efficient was lower when each the resistive memristor 101 in the resistive memristor array 10 was programmed respectively, and, most of resistive memristors 101 all should be arranged to the high value resistance state in the resistive memristor array 10, therefore can unify programming to all the resistive memristors 101 in the resistive memristor array 10 first, namely make all resistive memristors 101 all be in the high value resistance state by unified programming, and then to the respectively separately programming of the resistive memristor that should be arranged to the low resistance resistance state 101 of minority, namely make through the part resistive memristor 101 after the unified programming by independent programming to be in the low resistance resistance state.
It is above-mentioned when resistive memristor 101 is unified to programme, can with the input port of the logical circuit normal phase input end as program voltage, with the inverting input of each resistive memristor 101 inverting input as program voltage, for example, a row in left side among Fig. 1 can be reserved port as the inverting input of program voltage.
It is above-mentioned when resistive memristor 101 is programmed separately, can be with the input port of these resistive memristor 101 columns normal phase input end as program voltage, with the inverting input of this resistive memristor 101 inverting input as program voltage, also can will be in the inverting input of each resistive memristor 101 of the delegation inverting input as program voltage with this resistive memristor 101 in the resistive memristor array 10, for example, the reservation port that this resistive memristor 101 among Fig. 1 can be expert at is as the inverting input of program voltage.
In the embodiment of the invention, resistive memristor 101 can be monopole type resistive memristor, also can be ambipolar resistive memristor, when resistive memristor 101 was programmed, the size of program voltage can be chosen according to the single, double utmost point characteristic of resistive memristor 101.
With reference to monopole type resistive memristor conductivity among Fig. 3 a and Fig. 3 b with the curve chart of change in voltage, when resistive memristor 101 is monopole type resistive memristor, low resistance resistance state threshold voltage Vset and high value resistance state threshold voltage Vreset are positive voltage, when resistive memristor 101 is unified to programme, owing to all resistive memristors 101 will be set to the high value resistance state, therefore the first program voltage V1 should satisfy: Vset〉V1〉Vreset, all resistive memristors 101 all are set to the high value resistance state in the resistive memristor array 10 like this; When then programming separately respectively for each resistive memristor 101 that should be set to the low resistance resistance state in the resistive memristor array 10, the second program voltage V2 should satisfy: V2〉Vset.
With reference to ambipolar resistive memristor conductivity among Fig. 4 with the curve chart of change in voltage, when resistive memristor 101 is ambipolar resistive memristor, low resistance resistance state threshold voltage Vset is positive voltage, high value resistance state threshold voltage Vreset is negative voltage, when resistive memristor 101 is unified to programme, owing to all resistive memristors 101 will be set to the high value resistance state, therefore can be with the positive input end grounding of program voltage, and anti-phase input termination the 3rd program voltage V3 of program voltage, V3 should satisfy: V3〉| Vreset|, all resistive memristors 101 all are set to the high value resistance state in the resistive memristor array 10 like this; When then programming separately respectively for each resistive memristor 101 that should be set to the low resistance resistance state in the resistive memristor array 10, can be with the reverse inter-input-ing ending grounding of program voltage, and the normal phase input end of program voltage meets the 4th program voltage V4, and V4〉Vset.
Can select as required corresponding function with logical circuit, except the step-by-step phase that be used for to realize two digital input signals with, the step-by-step phase that can also be used for realizing more digital input signals with because specific implementation is similar, repeat no more in the embodiment of the invention.
For convenience, the voltage that in the embodiment of the invention input of comparator is received is called input voltage, represent that with Vin the threshold voltage of comparator represents with Vref, if Vin〉Vref, then the output of comparator is exported high level, be digital signal " 1 ", if Vin＜Vref, then the output output low level of comparator, be digital signal " 0 ", the Vref here can be set to 1/2 of operating voltage VDD.
Below in conjunction with Fig. 2 the operation principle of the present invention and logical circuit is analyzed: when in running order with logical circuit, every delegation only has three resistive memristors to be in low resistance resistance state (being ON state) in the resistive memristor array, for example, the first row of resistive memristor array only has resistive memristor 201 among Fig. 2, resistive memristor 202 and resistive memristor 203 are in the low resistance resistance state, all the other resistive memristors are in high value resistance state (being OFF state), so only have the input voltage vin of the comparator that the signal on the input port that these three the resistive memristors that are in the low resistance resistance state connect connects this row that contribution is arranged.In the first row of resistive memristor array, resistive memristor 201 connects the auxiliary signal input, when working with logical circuit, the auxiliary signal input connects digital signal " 0 ", be low level VL, resistive memristor 202 is connected with the resistive memristor and is connected signal input part, and signal input part is used for receiving the same position that need to carry out with two digital input signals of computing.For convenience of description, resistive memristor 201, resistive memristor 202 and resistive memristor 203 and resistance thereof are represented with Ron1, Ron2 and Ron3 respectively, the operating voltage of supposing this and logical circuit is VDD, i.e. high level VH=VDD, and the input voltage of comparator represents with Vin.The two digits input signal A1 and the B1 that receive when signal input part are " 1 ", when being high level VH, be equivalent to connect with Ron1 after Ron2 and the Ron3 parallel connection, Vin is Ron2//Ron3 and Ron1 partial pressure value, wherein, resistance after symbol " Ron2//Ron3 " represents Ron2 and Ron3 is in parallel, by Ron1 ≈ Ron2 ≈ Ron3, obtain Ron2//Ron3 ≈ 1/2Ron1, Vin ≈ 2/3VDD〉Vref=1/2VDD, so comparator goes out high level, i.e. digital signal " 1 "; Two the input signal A1 and the B1 that receive when signal input part are " 0 ", when being low level VL, it is in parallel to be equivalent to three resistive memristor Ron1, Ron2 and Ron3, Vin ≈ VL ≈ 0＜Vref=1/2VDD, comparator output low level, i.e. digital signal " 0 "; In two digits input signal A1 that signal input part receives and B1, there is one and is " 1 ", be high level VH, another is " 0 ", when being low level VL, for example, signal B1 on the Ron3 is high level, signal A1 on the Ron2 is low level, be equivalent to connect with Ron3 after Ron2 and the Ron1 parallel connection, Vin is Ron1//Ron2 and Ron3 partial pressure value, by Ron1 ≈ Ron2 ≈ Ron3, obtain Ron1//Ron2 ≈ 1/2Ron1, so Vin ≈ 1/3VDD＜Vref=1/2VDD is comparator output low level, i.e. digital signal " 0 ".As from the foregoing, only have when A1 and B1 are high level, corresponding signal output part is just exported high level, thus realize with logical circuit to two input signal step-by-step phases and function.Identical with the operation principle of the operation principle of all the other each row in the logical circuit and the first row, in the embodiment of the invention, this is no longer analyzed.
In addition, above-mentioned resistive memristor can be among RRAM, PRAM, FRAM and the MRAM any one.
That the embodiment of the invention provides and logical circuit, in consisting of, its circuit do not adopt traditional metal-oxide-semiconductor memory device fully, but adopted this novel memory device with two-end structure of resistive memristor, but contractility is good, storage density is high because the resistive memristor has, low in energy consumption, the characteristics such as read or write speed fast, the repeatable operation tolerance is strong, data hold time length, therefore in effective saving and logical circuit area occupied, realized and the programmable performance of logical circuit.
The embodiment of the invention also provides a kind of chip, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit.Comprise with logical circuit: resistive memristor array and comparator, wherein, the normal phase input end of same row resistive memristor is connected by the top electrode bonding jumper in the resistive memristor array, so that the normal phase input end of same row resistive memristor as with signal input part or the auxiliary signal input of logical circuit, be connected to low level during the work of auxiliary signal input, inverting input with delegation's resistive memristor in the resistive memristor array is connected by the input of hearth electrode bonding jumper with a comparator so that the output of comparator as with the signal output part of logical circuit.
Wherein, the voltage that the input of comparator receives is during greater than threshold voltage, and the output of comparator output high level, the voltage that the input of comparator receives be during less than threshold voltage, the output output low level of comparator.
Preferably, two signal input parts and an auxiliary signal input are as one group, so that two signal input parts of same group are used for receiving the same position of two digital input signals.
Preferably, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state; Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor with delegation in the described resistive memristor array; And, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor of same row in the described resistive memristor array.
Preferably, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor; And described resistive memristor comprises: RRAM or PRAM or FRAM or MRAM.
In the embodiment of the invention, in order to reduce the size of chip as far as possible, top electrode bonding jumper and hearth electrode bonding jumper can be arranged in square crossing, form a resistive memristor at each place, crosspoint, for example, the resistive memristor is for adopting the mode at top electrode bonding jumper and place, hearth electrode bonding jumper crosspoint filling resistive medium to form.
In addition, the top electrode bonding jumper can be arranged at respectively metal levels different in the chip from the hearth electrode bonding jumper, for example, and adjacent two metal layers.
In the embodiment of the invention, because resistive memristor and complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal Oxide Semiconductor) process compatible, so the manufacture craft of chip is simple.
The chip that the embodiment of the invention provides, comprised the top electrode bonding jumper, the hearth electrode bonding jumper and and logical circuit, in consisting of, its circuit do not adopt traditional metal-oxide-semiconductor memory device fully, but part has adopted this novel memory device with two-end structure of resistive memristor, since the resistive memristor but to have contractility good, storage density is high, low in energy consumption, read or write speed is fast, the repeatable operation tolerance is strong, the characteristics such as data hold time is long, therefore in effective saving and logical circuit area occupied, realized and the programmable performance of logical circuit, dwindled accordingly the size of chip, and the performance that has improved chip.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the embodiment of the invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation of the spirit or scope that do not break away from the embodiment of the invention, realize in other embodiments.Therefore, the embodiment of the invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
The above only is the preferred embodiment of the embodiment of the invention; not in order to limit the embodiment of the invention; all within the spirit and principle of the embodiment of the invention, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection range of the embodiment of the invention.
Claims (10)
1. one kind and logical circuit is characterized in that, comprising: resistive memristor array and comparator;
The normal phase input end of same row resistive memristor is connected in the described resistive memristor array, so that the normal phase input end of described same row resistive memristor as described and signal input part or auxiliary signal input logical circuit, is connected to low level during described auxiliary signal input work;
Inverting input with delegation's resistive memristor in the described resistive memristor array is connected with the input of a described comparator, so that the output of described comparator is as described and signal output part logical circuit;
The voltage that the input of described comparator receives is during greater than threshold voltage, and the output of described comparator output high level, the voltage that the input of described comparator receives be during less than threshold voltage, the output output low level of described comparator.
2. as claimed in claim 1 and logical circuit is characterized in that, two described signal input parts and a described auxiliary signal input are as one group, so that two described signal input parts of same group are used for receiving the same position of two digital input signals.
3. as claimed in claim 1 or 2 and logical circuit is characterized in that, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor with delegation in the described resistive memristor array; And, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor of same row in the described resistive memristor array.
4. as claimed in claim 1 and logical circuit is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
5. as claimed in claim 1 and logical circuit is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.
6. a chip is characterized in that, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit;
Described and logical circuit comprises: resistive memristor array and comparator;
The normal phase input end of same row resistive memristor is connected by described top electrode bonding jumper in the described resistive memristor array, so that the normal phase input end of described same row resistive memristor as described and signal input part or auxiliary signal input logical circuit, is connected to low level during described auxiliary signal input work;
Inverting input with delegation's resistive memristor in the described resistive memristor array is connected with the input of a described comparator by described hearth electrode bonding jumper, so that the output of described comparator is as described and signal output part logical circuit;
The voltage that the input of described comparator receives is during greater than threshold voltage, and the output of described comparator output high level, the voltage that the input of described comparator receives be during less than threshold voltage, the output output low level of described comparator.
7. chip as claimed in claim 6 is characterized in that, two described signal input parts and a described auxiliary signal input are as one group, so that two described signal input parts of same group are used for receiving the same position of two digital input signals.
8. such as claim 6 or 7 described chips, it is characterized in that the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;
Three resistive memristors that are in the low resistance resistance state are arranged in the resistive memristor with delegation in the described resistive memristor array; And, a resistive memristor that is in the low resistance resistance state is arranged in the resistive memristor of same row in the described resistive memristor array.
9. chip as claimed in claim 6 is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.
10. chip as claimed in claim 6 is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.
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| CN103716038A (en) * | 2013-12-25 | 2014-04-09 | 华中科技大学 | Nonvolatile logic gate circuit based on phase change memories |
| US9767900B2 (en) | 2014-03-18 | 2017-09-19 | Huawei Technologies Co., Ltd. | Method, apparatus and device for operating logical operation array of resistive random access memory |
| CN109791119A (en) * | 2016-10-04 | 2019-05-21 | 牛津布鲁克斯大学 | Sensor based on memristor |
| WO2021205456A1 (en) * | 2020-04-07 | 2021-10-14 | Technion Research & Development Foundation Limited | Logic gates and stateful logic using phase change memory |
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| CN103716038A (en) * | 2013-12-25 | 2014-04-09 | 华中科技大学 | Nonvolatile logic gate circuit based on phase change memories |
| CN103716038B (en) * | 2013-12-25 | 2016-05-25 | 华中科技大学 | A kind of non-volatile logic gate circuit based on phase transition storage |
| US9767900B2 (en) | 2014-03-18 | 2017-09-19 | Huawei Technologies Co., Ltd. | Method, apparatus and device for operating logical operation array of resistive random access memory |
| CN109791119A (en) * | 2016-10-04 | 2019-05-21 | 牛津布鲁克斯大学 | Sensor based on memristor |
| CN109791119B (en) * | 2016-10-04 | 2021-11-19 | 牛津布鲁克斯大学 | Memristor-based sensor |
| WO2021205456A1 (en) * | 2020-04-07 | 2021-10-14 | Technion Research & Development Foundation Limited | Logic gates and stateful logic using phase change memory |
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