CN102034535B - Three-value resistance variable storage unit with control circuit and read-write implementation method thereof - Google Patents

Three-value resistance variable storage unit with control circuit and read-write implementation method thereof Download PDF

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CN102034535B
CN102034535B CN 201010598114 CN201010598114A CN102034535B CN 102034535 B CN102034535 B CN 102034535B CN 201010598114 CN201010598114 CN 201010598114 CN 201010598114 A CN201010598114 A CN 201010598114A CN 102034535 B CN102034535 B CN 102034535B
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transfer tube
nmos transfer
connected
transmission gate
write
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CN 201010598114
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CN102034535A (en
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贾泽
徐建龙
王林凯
任天令
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清华大学
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Abstract

The invention discloses a three-value resistance variable storage unit with a control circuit and a read-write implementation method thereof. On the premise that a resistive random access memory (RRAM) has an enough window between a value 0 and a value 1, the current value of a resistance variable element is controlled at 0 to 1 in a SET or RESET process so as to define a third state, and the storage density is improved to 1.5bit/ resistance variable element in corresponding read-out and coding modes to meet the requirement of actual storage density.

Description

Three value type resistance-change memory unit and implementing reading and writing methods thereof with control circuit

Technical field

The present invention relates to a kind of memory cell technologies field, be specifically related to a kind of three value type resistance-change memory unit and implementing reading and writing methods thereof with control circuit.

Background technology

Resistance-variable storing device is that a kind of resistive element that utilizes can realize that between high-impedance state and low resistance state reversible transformation is for basic functional principle and as memory style, take the bipolarity resistance-variable storing device as example, what adopt at present all is to reach " 1 " with the high-impedance state of resistive element and low resistance state two Resistance states as binary data " 0 " to realize memory function, the resistive element is applied suitable voltage drive, can become low resistance SET or become high resistance RESET by low resistance by high resistance, realize the erasable of information.Then can not change resistance states in the time of the sensing resistor state with an enough little voltage, realize sense information, and the storage density of the resistance-variable storing device of employing 1T1R structure is 1bit/ resistive element.

Compare with legacy memory such as FLASH, resistance-variable storing device all shows excellent properties at speed, power consumption, the aspect such as low voltage operated.Angle from device property and heat dissipation, resistance-variable storing device is best suited for a kind of structure of scaled down (Scaling-down), but the storage density of using at present traditional 1T1R structure resistance-change memory unit can not satisfy the requirement of actual storage density far away, if can promote its storage density from circuit design is integrated scale, then can under the prerequisite that does not change technique, improve the storage density of resistance-variable storing device, have important practical application meaning.

Summary of the invention

The deficiency that exists in order to overcome above-mentioned prior art, the object of the present invention is to provide a kind of three value type resistance-change memory unit and implementing reading and writing methods thereof with control circuit, have under the prerequisite of enough windows between 0 value and 1 value at resistance-variable storing device, thereby be in the definition third state between the two by flowing through resistive element current value in control SET or the RESET process, again through corresponding reading and coded system, realize the 3bit storage by three value type resistance-change memory unit, and storage density is increased to 1.5bit/ resistive element, satisfied the demand of actual storage density.

In order to achieve the above object, the technical solution adopted in the present invention is:

A kind of three value type resistance-change memory unit with control circuit, comprise three value type resistance-change memory unit, the input end group of described three value type resistance-change memory unit is connected with the output terminal group with the output terminal group of intermediateness write circuit and is connected the corresponding connection of input end group with sensing circuit.

Described three value type resistance-change memory unit comprise a 1T1R structure and the 2nd 1T1R structure, and a 1T1R structure is by the first resistive element R 0With drain electrode and this first resistive element R 0The NMOS transfer tube M that one end is connected 0Form, the 2nd 1T1R structure is by the second resistive element R 1With drain electrode and this second resistive element R 1The 2nd NMOS transfer tube M that one end is connected 1Form the first resistive element R 0The other end and the first bit line BL 0Be connected the second resistive element R 1The other end and the second bit line BL 1Be connected a NMOS transfer tube M 0Source electrode and the 2nd NMOS transfer tube M 1Source electrode receive respectively the first source line SL 0With the second source line SL 1On, and word line WL is through the first transmission gate T 0With the second transmission gate T 1Be connected to respectively a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid, described the first transmission gate T 0Control end, the second transmission gate T 1Control end, a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid consisted of the input end group of three value type resistance-change memory unit, and described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1The end that is connected has consisted of the output terminal group of three value type resistance-change memory unit.

Described intermediateness write circuit comprises the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5, the 3rd NMOS transfer tube N 4Drain electrode and the 4th NMOS transfer tube N 5Drain electrode and the intermediateness voltage V of described three value type resistance-change memory unit MBe connected the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Respectively with the 3rd NMOS transfer tube N 4Grid and the 4th NMOS transfer tube N 5Grid be connected other the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Also respectively with the first phase inverter inv 0Input end and the second phase inverter inv 1Input end be connected the first phase inverter inv 0Output terminal, the second phase inverter inv 1Output terminal, the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode consisted of the output terminal group of intermediateness write circuit and the first phase inverter inv 0Output terminal and the second phase inverter inv 1Output terminal respectively with described the first transmission gate T 0Control end and the second transmission gate T 1Control end be connected the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode respectively with a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid be connected.

Described sensing circuit comprises the 3rd transmission gate T 2With the 4th transmission gate T 3, described the 3rd transmission gate T 2Output terminal and the 4th transmission gate T 3Output terminal respectively with the first current source I 0With the second current source I 1Be connected the 3rd transmission gate T 2Control end, the 4th transmission gate T 3Control end be connected the 3rd transmission gate T with sensing circuit enable signal Read_en 2Input end, the 5th NMOS transfer tube N 0Source electrode and the 7th NMOS transfer tube N 2Source electrode be connected the 4th transmission gate T 3Input end, the 6th NMOS transfer tube N 1Source electrode and the 8th NMOS transfer tube N 3Source electrode be connected the one or three value sensing circuit gating signal SEL 0, the 5th NMOS transfer tube N 0Grid and the 6th NMOS transfer tube N 1Grid be connected the two or three value sensing circuit gating signal SEL 1, the 7th NMOS transfer tube N 2Grid and the 8th NMOS transfer tube N 3Grid be connected the 5th NMOS transfer tube N 0Drain electrode and the 6th NMOS transfer tube N 1Drain electrode respectively with the first sense amplifier SA 1Input end and the second sense amplifier SA 2An input end be connected the first sense amplifier SA 1Another input end, the second sense amplifier SA 2Another input end and the first reference voltage V ReflBe connected the 7th NMOS transfer tube N 2Drain electrode and the 8th NMOS transfer tube N 3Drain electrode respectively with the 3rd sense amplifier SA 3Input end and the 4th sense amplifier SA 4An input end be connected the 3rd sense amplifier SA 3Another input end, the 4th sense amplifier SA 4Another input end and the second reference voltage V RefhBe connected the first sense amplifier SA 1Output terminal, the second sense amplifier SA 2Output terminal, the 3rd sense amplifier SA 3Output terminal and the 4th sense amplifier SA 4Output terminal be connected respectively other described the 3rd transmission gate T with four input ends of 4-3 scrambler 2Input end and the 4th transmission gate T 3Input end consisted of the input end group of sensing circuit, described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1Be connected the end respectively with the 3rd transmission gate T 2Input end and the 4th transmission gate T 3Input end be connected.

The realization method of writing of described three value type resistance-change memory unit with control circuit is write time period T at first default section continuous time sequentially being divided into first 00, second write time period T 01And the 3rd write time period T 02, then write time period T default first 00Stage arranges word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And to read enable signal Read_en be low level; And write time period T second 01Stage when needs data writing " 1 ", is increased to high level with word line WL, this moment the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal keeps low level, immediately the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting, and the first resistive element R 0With the second resistive element R 1Accessed, as the first source line SL 0With the second source line SL 1Connect low level and the first bit line BL 0With the second bit line BL 1Connect high level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the SET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the SET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into low resistance state, namely finished data writing " 1 "; When needs data writing " 0 ", with the first source line SL 0With the second source line SL 1Connect high level and the first bit line BL 0With the second bit line BL 1Connect low level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the RESET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the RESET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into high-impedance state, namely finished data writing " 0 "; And when needs write intermediateness " M ", with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal is pulled to high level, immediately the first transmission gate T 0With the second transmission gate T 1End, and intermediateness is write voltage V MBe controlled at and produce a value between described low resistance state and high-impedance state, thereby finished writing of intermediateness " M "; And write time period T the 3rd 02The time the one or three value sensing circuit gating signal SEL just 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, finish the write operation of three value type resistance-change memory unit.

The implementation method of reading of described three value type resistance-change memory unit with control circuit is three value type read operations, first default section continuous time sequentially is divided into the first read time section T 10, the second read time section T 11And third reading time period T 12, then at the first read time section T 10With word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and be set to low level; And at the second read time section T 11, with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal access low level, immediately the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5Cut-off, simultaneously the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting then will be read enable signal Read_en and become high level by low level, then the 3rd transmission gate T 2With the 4th transmission gate T 3Conducting starts the first current source I 0With the second current source I 1Respectively to the first resistive element R 0With the second resistive element R 1Pass to a steady state value electric current, produce pressure drop, if if this pressure drop less than default lower limit V L, then be logical value " 1 ", if this pressure drop is greater than default higher limit V H, then be logical value " 0 ", and pressure drop is V between default higher limit and lower limit M, then be logical value " M ", meanwhile control the one or three value sensing circuit gating signal SEL 0With the two or three value sensing circuit gating signal SEL 1Produce a high level pulse signal, with the first sense amplifier SA 1, the second sense amplifier SA 2, the 3rd sense amplifier SA 3With the 4th sense amplifier SA 4Conducting is subsequently with the first reference voltage V ReflAnd V RefhOutput to the 4-3 scrambler after making comparisons, the value of exporting after the 4-3 coder processes is exactly readout; At last at third reading time period T 12Interior with the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, finish three value type read operations.

By a kind of three value type resistance-change memory unit and implementing reading and writing methods thereof with control circuit are provided, have under the prerequisite of enough windows between 0 value and 1 value at RRAM, thereby be in and define a third state between the two by flowing through resistive element current value in control SET or the RESET process, again through corresponding reading and coded system, storage density is increased to 1.5bit/ resistive element, has satisfied the demand of actual storage density.

Description of drawings

Fig. 1 is the basic map of resistive element in the two-value type resistance-change memory unit and the synoptic diagram of choosing of two state of value.

Fig. 2 is the basic map of resistive element in the three value type resistance-change memory unit and the synoptic diagram of choosing of three state of value.

Fig. 3 is the write operation sequential chart of three value type resistance-change memory unit.

Fig. 4 is the read operation sequential chart of three value type resistance-change memory unit.

Embodiment

The present invention will be described in more detail below in conjunction with drawings and Examples.

Be illustrated in figure 1 as the basic map of resistive element in the two-value type resistance-change memory unit and the synoptic diagram of choosing of two state of value, defined logical value " 1 " and " 0 " when " H " and " L " is respectively the operation of two-value type among the figure, the resistive element belongs to high-impedance state when being in " H " attitude, applying voltage VH corresponding to steady current I is large voltage drop, otherwise, what " L " attitude was corresponding is low resistance state, applying voltage VL corresponding to steady current I is small voltage drop, so just definition " H " is low resistance state for high-impedance state reaches " L ", realizes thus being become low resistance SET process or being become high resistance RESET process by low resistance by high resistance.And the fundamental characteristics of resistive element and three selected states in the three value type resistance-change memory unit among the present invention, as shown in Figure 2, its " H " is same as shown in Figure 1 with choosing of " L " attitude, and " M " is defined the 3rd state in the storage of three values, has a middle resistance between high-impedance state and low resistance state, be called intermediateness " M ", also may be defined as " M " and be middle resistance state.

The present invention is with three value type resistance-change memory unit of control circuit, comprise three value type resistance-change memory unit, the input end group of described three value type resistance-change memory unit is connected with the output terminal group with the output terminal group of intermediateness write circuit and is connected the corresponding connection of input end group with sensing circuit.

Described three value type resistance-change memory unit comprise a 1T1R structure and the 2nd 1T1R structure, and a 1T1R structure is by the first resistive element R 0With drain electrode and this first resistive element R 0The NMOS transfer tube M that one end is connected 0Form, the 2nd 1T1R structure is by the second resistive element R 1With drain electrode and this second resistive element R 1The 2nd NMOS transfer tube M that one end is connected 1Form the first resistive element R 0The other end and the first bit line BL 0Be connected the second resistive element R 1The other end and the second bit line BL 1Be connected a NMOS transfer tube M 0Source electrode and the 2nd NMOS transfer tube M 1Source electrode receive respectively the first source line SL 0With the second source line SL 1On, and word line WL is through the first transmission gate T 0With the second transmission gate T 1Be connected to respectively a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid, described through the first transmission gate T 0Control end, the second transmission gate T 1Control end, a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid consisted of the input end group of three value type resistance-change memory unit, and described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1The end that is connected has consisted of the output terminal group of three value type resistance-change memory unit.

Described intermediateness write circuit comprises the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5, the 3rd NMOS transfer tube N 4Drain electrode and the 4th NMOS transfer tube N 5Drain electrode and the intermediateness voltage V of described three value type resistance-change memory unit MBe connected the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Respectively with the 3rd NMOS transfer tube N 4Grid and the 4th NMOS transfer tube N 5Grid be connected other the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Also respectively with the first phase inverter inv 0Input end and the second phase inverter inv 1Input end be connected the first phase inverter inv 0Output terminal, the second phase inverter inv 1Output terminal, the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode consisted of the output terminal group of intermediateness write circuit and the first phase inverter inv 0Output terminal and the second phase inverter inv 1Output terminal respectively with described the first transmission gate T 0Control end and the second transmission gate T 1Control end be connected the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode respectively with a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid be connected.

Described sensing circuit comprises the 3rd transmission gate T 2With the 4th transmission gate T 3, described the 3rd transmission gate T 2Output terminal and the 4th transmission gate T 3Output terminal respectively with the first current source I 0With the second current source I 1Be connected the 3rd transmission gate T 2Control end, the 4th transmission gate T 3Control end be connected the 3rd transmission gate T with sensing circuit enable signal Read_en 2Input end, the 5th NMOS transfer tube N 0Source electrode and the 7th NMOS transfer tube N 2Source electrode be connected the 4th transmission gate T 3Input end, the 6th NMOS transfer tube N 1Source electrode and the 8th NMOS transfer tube N 3Source electrode be connected the one or three value sensing circuit gating signal SEL 0, the 5th NMOS transfer tube N 0Grid and the 6th NMOS transfer tube N 1Grid be connected the two or three value sensing circuit gating signal SEL 1, the 7th NMOS transfer tube N 2Grid and the 8th NMOS transfer tube N 3Grid be connected the 5th NMOS transfer tube N 0Drain electrode and the 6th NMOS transfer tube N 1Drain electrode respectively with the first sense amplifier SA 1Input end and the second sense amplifier SA 2An input end be connected the first sense amplifier SA 1Another input end, the second sense amplifier SA 2Another input end and the first reference voltage V ReflBe connected the 7th NMOS transfer tube N 2Drain electrode and the 8th NMOS transfer tube N 3Drain electrode respectively with the 3rd sense amplifier SA 3Input end and the 4th sense amplifier SA 4An input end be connected the 3rd sense amplifier SA 3Another input end, the 4th sense amplifier SA 4Another input end and the second reference voltage V RefhBe connected the first sense amplifier SA 1Output terminal, the second sense amplifier SA 2Output terminal, the 3rd sense amplifier SA 3Output terminal and the 4th sense amplifier SA 4Output terminal be connected respectively other described the 3rd transmission gate T with four input ends of 4-3 scrambler 2Input end and the 4th transmission gate T 3Input end consisted of the input end group of sensing circuit, described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1Be connected the end respectively with the 3rd transmission gate T 2Input end and the 4th transmission gate T 3Input end be connected.

As shown in Figure 3, the realization method of writing of described three value type resistance-change memory unit with control circuit is write time period T at first default section continuous time sequentially being divided into first 00, second write time period T 01And the 3rd write time period T 02, then write time period T default first 00Stage arranges word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And to read enable signal Read_en be low level; And write time period T second 01Stage when needs data writing " 1 ", is increased to high level with word line WL, this moment the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal keeps low level, immediately the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting, and the first resistive element R 0With the second resistive element R 1Accessed, as the first source line SL 0With the second source line SL 1Connect low level and the first bit line BL 0With the second bit line BL 1Connect high level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the SET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the SET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into low resistance state, namely finished data writing " 1 "; When needs data writing " 0 ", with the first source line SL 0With the second source line SL 1Connect high level and the first bit line BL 0With the second bit line BL 1Connect low level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the RESET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the RESET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into high-impedance state, namely finished data writing " 0 "; And when needs write intermediateness " M ", with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal is pulled to high level, immediately the first transmission gate T 0With the second transmission gate T 1End, and intermediateness is write voltage V MBe controlled at and produce a value between described low resistance state and high-impedance state, thereby finished writing of intermediateness " M "; And write time period T the 3rd 02The time the one or three value sensing circuit gating signal SEL just 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, the write operation of three value type resistance-change memory unit of end.

As shown in Figure 4, the implementation method of reading of described three value type resistance-change memory unit with control circuit is three value type read operations, first default section continuous time sequentially is divided into the first read time section T 10, the second read time section T 11And third reading time period T 12, then at the first read time section T 10With word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and be set to low level; And at the second read time section T 11, with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal access low level, immediately the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5Cut-off, simultaneously the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting then will be read enable signal Read_en and become high level by low level, then the 3rd transmission gate T 2With the 4th transmission gate T 3Conducting starts the first current source I 0With the second current source I 1Respectively to the first resistive element R 0With the second resistive element R 1Pass to a steady state value electric current, produce pressure drop, if if this pressure drop less than default lower limit V L, then be logical value " 1 ", if this pressure drop is greater than default higher limit V H, then be logical value " 0 ", and pressure drop is V between default higher limit and lower limit M, then be logical value " M ", meanwhile control the one or three value sensing circuit gating signal SEL 0With the two or three value sensing circuit gating signal SEL 1Produce a high level pulse signal, with the first sense amplifier SA 1, the second sense amplifier SA 2, the 3rd sense amplifier SA 3With the 4th sense amplifier SA 4Conducting is subsequently with the first reference voltage V ReflAnd V RefhOutput to the 4-3 scrambler after making comparisons, the value of exporting after the 4-3 coder processes is exactly readout; At last at third reading time period T 12Interior with the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, finish three value type read operations.

When a 1T1R structure and the 2nd 1T1R structure were used three value type memory functions, they can join together to represent state among the 32=9 like this.8 kinds of states choosing in 9 kinds of states are encoded, and can realize the storage of 3bit logical value, and the specific coding mode is as shown in table 1:

Table 1 three value type resistance-change memory cell encoding tables

Thus by a kind of three value type resistance-change memory unit and implementing reading and writing methods thereof with control circuit are provided, have under the prerequisite of enough windows between 0 value and 1 value at RRAM, thereby be in and define a third state between the two by flowing through resistive element current value in control SET or the RESET process, again through corresponding reading and coded system, storage density is increased to 1.5bit/ resistive element, has satisfied the demand of actual storage density.

Claims (3)

1. three value type resistance-change memory unit with control circuit is characterized in that: the input end group of described three value type resistance-change memory unit is connected with the output terminal group with the output terminal group of intermediateness write circuit and is connected the corresponding connection of input end group with sensing circuit;
Described three value type resistance-change memory unit comprise a 1T1R structure and the 2nd 1T1R structure, and a 1T1R structure is by the first resistive element R 0With drain electrode and this first resistive element R 0The NMOS transfer tube M that one end is connected 0Form, the 2nd 1T1R structure is by the second resistive element R 1With drain electrode and this second resistive element R 1The 2nd NMOS transfer tube M that one end is connected 1Form the first resistive element R 0The other end and the first bit line BL 0Be connected the second resistive element R 1The other end and the second bit line BL 1Be connected a NMOS transfer tube M 0Source electrode and the 2nd NMOS transfer tube M 1Source electrode receive respectively the first source line SL 0With the second source line SL 1On, and word line WL is through the first transmission gate T 0With the second transmission gate T 1Be connected to respectively a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid, described through the first transmission gate T 0Control end, the second transmission gate T 1Control end, a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid consisted of the input end group of three value type resistance-change memory unit, and described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1The end that is connected has consisted of the output terminal group of three value type resistance-change memory unit;
Described intermediateness write circuit comprises the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5, the 3rd NMOS transfer tube N 4Drain electrode and the 4th NMOS transfer tube N 5Drain electrode and the intermediateness voltage V of described three value type resistance-change memory unit MBe connected the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Respectively with the 3rd NMOS transfer tube N 4Grid and the 4th NMOS transfer tube N 5Grid be connected other the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Also respectively with the first phase inverter inv 0Input end and the second phase inverter inv 1Input end be connected the first phase inverter inv 0Output terminal, the second phase inverter inv 1Output terminal, the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode consisted of the output terminal group of intermediateness write circuit and the first phase inverter inv 0Output terminal and the second phase inverter inv 1Output terminal respectively with described the first transmission gate T 0Control end and the second transmission gate T 1Control end be connected the 3rd NMOS transfer tube N 4Source electrode and the 4th NMOS transfer tube N 5Source electrode respectively with a NMOS transfer tube M 0Grid and the 2nd NMOS transfer tube M 1Grid be connected;
Described sensing circuit comprises the 3rd transmission gate T 2With the 4th transmission gate T 3, described the 3rd transmission gate T 2Output terminal and the 4th transmission gate T 3Output terminal respectively with the first current source I 0With the second current source I 1Be connected the 3rd transmission gate T 2Control end, the 4th transmission gate T 3Control end be connected the 3rd transmission gate T with sensing circuit enable signal Read_en 2Input end, the 5th NMOS transfer tube N 0Source electrode and the 7th NMOS transfer tube N 2Source electrode be connected the 4th transmission gate T 3Input end, the 6th NMOS transfer tube N 1Source electrode and the 8th NMOS transfer tube N 3Source electrode be connected the one or three value sensing circuit gating signal SEL 0, the 5th NMOS transfer tube N 0Grid and the 6th NMOS transfer tube N 1Grid be connected the two or three value sensing circuit gating signal SEL 1, the 7th NMOS transfer tube N 2Grid and the 8th NMOS transfer tube N 3Grid be connected the 5th NMOS transfer tube N 0Drain electrode and the 6th NMOS transfer tube N 1Drain electrode respectively with the first sense amplifier SA 1Input end and the second sense amplifier SA 2An input end be connected the first sense amplifier SA 1Another input end, the second sense amplifier SA 2Another input end and the first reference voltage V ReflBe connected the 7th NMOS transfer tube N 2Drain electrode and the 8th NMOS transfer tube N 3Drain electrode respectively with the 3rd sense amplifier SA 3Input end and the 4th sense amplifier SA 4An input end be connected the 3rd sense amplifier SA 3Another input end, the 4th sense amplifier SA 4Another input end and the second reference voltage V RefhBe connected the first sense amplifier SA 1Output terminal, the second sense amplifier SA 2Output terminal, the 3rd sense amplifier SA 3Output terminal and the 4th sense amplifier SA 4Output terminal be connected respectively other described the 3rd transmission gate T with four input ends of 4-3 scrambler 2Input end and the 4th transmission gate T 3Input end consisted of the input end group of sensing circuit, described the first resistive element R 0With the first bit line BL 0End and the second resistive element R are connected 1With the second bit line BL 1Be connected the end respectively with the 3rd transmission gate T 2Input end and the 4th transmission gate T 3Input end be connected.
2. the implementation method of three value type resistance-change memory unit with control circuit according to claim 1 is characterized in that: the realization method of writing of described three value type resistance-change memory unit with control circuit is write time period T at first default section continuous time sequentially being divided into first 00, second write time period T 01And the 3rd write time period T 02, then write time period T default first 00Stage arranges word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And to read enable signal Read_en be low level; And write time period T second 01Stage when needs data writing " 1 ", is increased to high level with word line WL, this moment the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal keeps low level, immediately the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting, and the first resistive element R 0With the second resistive element R 1Accessed, as the first source line SL 0With the second source line SL 1Connect low level and the first bit line BL 0With the second bit line BL 1Connect high level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the SET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the SET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into low resistance state, namely finished data writing " 1 "; When needs data writing " 0 ", with the first source line SL 0With the second source line SL 1Connect high level and the first bit line BL 0With the second bit line BL 1Connect low level, adjust the first source line SL 0With the first bit line BL 0The voltage drop that forms makes it greater than the first resistive element R 0Resistive threshold value in the RESET process, and the second source line SL 1With the second bit line BL 1The voltage drop that forms makes it greater than the second resistive element R 1Resistive threshold value in the RESET process, thus the first resistive element R 0With the second resistive element R 1Be transformed into high-impedance state, namely finished data writing " 0 "; And when needs write intermediateness " M ", with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal is pulled to high level, immediately the first transmission gate T 0With the second transmission gate T 1End, and intermediateness is write voltage V MBe controlled at and produce a value between described low resistance state and high-impedance state, thereby finished writing of intermediateness " M "; And write time period T the 3rd 02The time the one or three value sensing circuit gating signal SEL just 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, the write operation of three value type resistance-change memory unit of end.
3. the implementation method of three value type resistance-change memory unit with control circuit according to claim 1, it is characterized in that: the implementation method of reading of described three value type resistance-change memory unit with control circuit is three value type read operations, first default section continuous time sequentially is divided into the first read time section T 10, the second read time section T 11And third reading time period T 12, then at the first read time section T 10With word line WL, the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and be set to low level; And at the second read time section T 11, with the first intermediateness write-enable signal WRM 0With the second intermediateness write-enable signal WRM 1Signal access low level, immediately the 3rd NMOS transfer tube N 4With the 4th NMOS transfer tube N 5Cut-off, simultaneously the first transmission gate T 0With the second transmission gate T 1Conducting causes a NMOS transfer tube M who is connected to word line WL 0With the 2nd NMOS transfer tube M 1Also conducting then will be read enable signal Read_en and become high level by low level, then the 3rd transmission gate T 2With the 4th transmission gate T 3Conducting starts the first current source I 0With the second current source I 1Respectively to the first resistive element R 0With the second resistive element R 1Pass to a steady state value electric current, produce pressure drop, if if this pressure drop less than default lower limit V L, then be logical value " 1 ", if this pressure drop is greater than default higher limit V H, then be logical value " 0 ", and pressure drop is V between default higher limit and lower limit M, then be logical value " M ", meanwhile control the one or three value sensing circuit gating signal SEL 0With the two or three value sensing circuit gating signal SEL 1Produce a high level pulse signal, with the first sense amplifier SA 1, the second sense amplifier SA 2, the 3rd sense amplifier SA 3With the 4th sense amplifier SA 4Conducting is subsequently with the first reference voltage V ReflAnd V RefhOutput to the 4-3 scrambler after making comparisons, the value of exporting after the 4-3 coder processes is exactly readout; At last at third reading time period T 12Interior with the one or three value sensing circuit gating signal SEL 0, the two or three value sensing circuit gating signal SEL 1, the first intermediateness write-enable signal WRM 0, the second intermediateness write-enable signal WRM 1And read enable signal Read_en and all reduce to low level, finish three value type read operations.
CN 201010598114 2010-12-15 2010-12-15 Three-value resistance variable storage unit with control circuit and read-write implementation method thereof CN102034535B (en)

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