CN102881631A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN102881631A CN102881631A CN201110195504XA CN201110195504A CN102881631A CN 102881631 A CN102881631 A CN 102881631A CN 201110195504X A CN201110195504X A CN 201110195504XA CN 201110195504 A CN201110195504 A CN 201110195504A CN 102881631 A CN102881631 A CN 102881631A
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- barrier layer
- diffusion barrier
- layer
- semiconductor substrate
- gate oxide
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Abstract
The invention provides a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: providing a semiconductor substrate, forming a grid structure on the semiconductor substrate and forming active/drain regions at the two sides of the grid structure; forming dielectric layers on the semiconductor substrate and forming copper metal interconnecting lines in the dielectric layers; and copper diffusion impervious layers are formed on the dielectric layers and the copper interconnecting lines, wherein a precursor material used for forming the copper interconnecting lines comprising hexamethyldisilazane, cyanamide and ammonia. According to the manufacturing method of the semiconductor device, hydrogen can be effectively prevented from entering a gate oxide through copper diffusion to inducing leakage by the gate oxide, so that the reliability of the gate oxide can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, adopt new copper metal diffusion barrier layer to improve the method for gate oxide leaky in particular to a kind of.
Background technology
Along with improving constantly of IC manufacturing integration degree, the gate oxide of MOS device thins down.Although operating voltage is minimized, the improving constantly to put on the electric field strength of the gate oxide higher of day by day microminiaturization of device and performance.Electric field strength is higher, and the gate oxide leaky is more serious, occur through the time dielectric breakdown (TDDB) time shorter, therefore, more and more higher to the requirement of reliability of the gate oxide.
The factor that affects reliability of the gate oxide is a lot, such as the performance of the constituent material of gate oxide own, the method that forms gate oxide, subsequent technique on the impact (such as stress influence) of gate oxide etc.There are some researches show, after implementing the metal interconnected technique of copper, the interface trap density of the gate oxide of measuring by charge pump (charge-pumping) method increases, be that defective in the gate oxide increases, the number of defects purpose increases so that the leaky of gate oxide increases, so occur through the time dielectric breakdown (TDDB) possibility greatly improve.This is owing to needing to form the barrier layer that stops the diffusion of copper metal in the process of the metal interconnected technique of enforcement copper, be used for to stop the diffusion of lower floor's copper metal to upper strata dielectric layer and upper copper metal to lower floor's dielectric layer, usually adopt silicon nitride as the material of described copper metal diffusion barrier layer, form silicon nitride and usually make silane (SiH by plasma enhanced chemical vapor deposition (PECVD)
4) and ammonia (NH
3) react to prepare.Have a large amount of si-h bond (Si-H) in the silicon nitride of this method preparation, hydrogen wherein can be diffused in the gate oxide by the copper metal under the effect of electric field, induces gate oxide to produce defective, and then affects the reliability of gate oxide.
Therefore, need to propose a kind of method to form new copper metal diffusion barrier layer, induce gate oxide to produce electric leakage to avoid hydrogen, affect the reliability of gate oxide.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate, and form active/drain region in the both sides of described grid structure; Form dielectric layer in described Semiconductor substrate, and in described dielectric layer, form the copper metal interconnecting wires; Form copper diffusion barrier layer at described dielectric layer and copper metal interconnecting wires, the precursor material that forms described copper diffusion barrier layer comprises hexamethyldisiloxane.
Preferably, adopt chemical vapor deposition method to form described copper diffusion barrier layer.
Preferably, the flow of hexamethyldisiloxane is 100-1000sccm.
Preferably, the precursor material that forms described copper diffusion barrier layer also comprises cyanamide.
Preferably, the flow of cyanamide is 100-1000sccm.
Preferably, the precursor material that forms described copper diffusion barrier layer also comprises ammonia.
Preferably, the flow of ammonia is 100-1000sccm.
Preferably, adopt helium as the carrier gas of described chemical vapour deposition (CVD).
Preferably, the flow of helium is 1000-2000sccm.
Preferably, described chemical vapor deposition processes is at pressure 3-7Torr, carries out under the condition of power 150-1000W.
Preferably, the thickness of described copper diffusion barrier layer is the 100-2000 dust.
Preferably, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer that stacks gradually.
Preferably, described gate dielectric is gate oxide.
Preferably, described dielectric layer is the material layer with low-k.
According to the present invention, can effectively avoid hydrogen to diffuse into gate oxide by the copper metal, induce gate oxide to produce electric leakage, improve the reliability of gate oxide.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In the accompanying drawing:
Figure 1A-Fig. 1 C is the new copper metal diffusion barrier layer of the employing that proposes of the present invention with the schematic cross sectional view of each step of the method for improving the gate oxide leaky;
Fig. 2 is the new copper metal diffusion barrier layer of the employing that proposes of the present invention with the flow chart of the method for improving the gate oxide leaky.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explaination the present invention adopts new copper metal diffusion barrier layer to improve the leaky of gate oxide in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, the new copper metal diffusion barrier layer of employing that the present invention proposes is described with the detailed step of the method for improving the gate oxide leaky with reference to Figure 1A-Fig. 1 C and Fig. 2.
With reference to Figure 1A-Fig. 1 C, wherein show the new copper metal diffusion barrier layer of employing that the present invention proposes with the schematic cross sectional view of each step of the method for improving the gate oxide leaky.
At first, shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, is doped with the monocrystalline silicon of impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to consist of.Be formed with isolation channel in Semiconductor substrate 100, buried regions, and various trap (well) structure in order to simplify, are omitted in the diagram.
Be formed with grid structure 102 in described Semiconductor substrate 100, as an example, described grid structure 102 comprises gate dielectric, gate material layers and the grid hard masking layer that stacks gradually from bottom to top.Gate dielectric can be oxide skin(coating), for example, and silicon dioxide (SiO
2) layer; Gate material layers can be polysilicon layer; The grid hard masking layer can be oxide skin(coating).
In addition, as example, on described Semiconductor substrate 100, also be formed with and be positioned at described grid structure 102 both sides and near the clearance wall structure 103 of grid structure.Wherein, clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
In the Semiconductor substrate of described grid structure 102 both sides, form respectively source region 104 and drain region 105.
Before forming described grid structure 102, can form monoxide layer 101 in described Semiconductor substrate 100, so that Semiconductor substrate 100 is avoided unnecessary loss in subsequent process steps.
Then, as shown in Figure 1B, form a dielectric layer 106 in described Semiconductor substrate 100, it typically is the material layer with low-k, adopt silicon oxide layer in the present embodiment.Be formed with in the described dielectric layer 106 for the groove of filling metal interconnecting wires.Deposit a metal level, copper metal layer for example on described dielectric layer 106, and fills up groove in the described dielectric layer 106.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, the surface that is ground to described dielectric layer 106 stops, and forms copper metal interconnecting wires 107 in described dielectric layer 106.
Then, shown in Fig. 1 C, form a barrier layer 108 at described dielectric layer 106 and copper metal interconnecting wires 107.Described barrier layer 108 is used for stoping the diffusion of lower floor's copper metal to upper strata dielectric layer and upper copper metal to lower floor's dielectric layer.Adopt chemical vapor deposition method to form described barrier layer 108, wherein, with the carrier gas of helium (He) as chemical vapour deposition (CVD), with hexamethyldisiloxane (C
6H
19NSi
2), cyanamide (CH
2N
2) and ammonia (NH
3) as the precursor material that forms described barrier layer 108, C
6H
19NSi
2, CH
2N
2And NH
3React and form carbonitride of silicium (Si
xC
yN
z) as the material on described barrier layer 108, reduce hydrogen to the impact of reliability of the gate oxide.
The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 3-7Torr, power 150-1000W, C
6H
19NSi
2Flow be 100-1000sccm, CH
2N
2Flow be 100-1000sccm, NH
3Flow be 100-1000sccm, the flow of He is 1000-2000sccm.The thickness on the described barrier layer 108 that deposition forms is the 100-2000 dust.
So far, finish according to an exemplary embodiment of the present invention whole processing steps of method enforcement, according to the present invention, can effectively avoid hydrogen to diffuse into gate oxide by the copper metal, induced gate oxide to produce electric leakage, improved the reliability of gate oxide.
With reference to Fig. 2, wherein show the new copper metal diffusion barrier layer of employing that the present invention proposes with the flow chart of the method for improving the gate oxide leaky, be used for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, be formed with grid structure in described Semiconductor substrate, and form active/drain region in the both sides of described grid structure;
In step 202, form dielectric layer in described Semiconductor substrate, and in described dielectric layer, form the copper metal interconnecting wires;
In step 203, form copper diffusion barrier layer at described dielectric layer and copper metal interconnecting wires, the precursor material that forms described copper diffusion barrier layer comprises hexamethyldisiloxane, cyanamide and ammonia.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate, and form active/drain region in the both sides of described grid structure;
Form dielectric layer in described Semiconductor substrate, and in described dielectric layer, form the copper metal interconnecting wires;
Form copper diffusion barrier layer at described dielectric layer and copper metal interconnecting wires, the precursor material that forms described copper diffusion barrier layer comprises hexamethyldisiloxane.
2. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form described copper diffusion barrier layer.
3. method according to claim 1 is characterized in that, the flow of hexamethyldisiloxane is 100-1000sccm.
4. method according to claim 1 is characterized in that, the precursor material that forms described copper diffusion barrier layer also comprises cyanamide.
5. method according to claim 4 is characterized in that, the flow of cyanamide is 100-1000sccm.
6. method according to claim 1 is characterized in that, the precursor material that forms described copper diffusion barrier layer also comprises ammonia.
7. method according to claim 6 is characterized in that, the flow of ammonia is 100-1000sccm.
8. method according to claim 2 is characterized in that, adopts helium as the carrier gas of described chemical vapour deposition (CVD).
9. method according to claim 8 is characterized in that, the flow of helium is 1000-2000sccm.
10. method according to claim 2 is characterized in that, described chemical vapor deposition processes is at pressure 3-7Torr, carries out under the condition of power 150-1000W.
11. method according to claim 1 and 2 is characterized in that, the thickness of described copper diffusion barrier layer is the 100-2000 dust.
12. method according to claim 1 is characterized in that, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer that stacks gradually.
13. method according to claim 12 is characterized in that, described gate dielectric is gate oxide.
14. method according to claim 1 is characterized in that, described dielectric layer is the material layer with low-k.
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|---|---|---|---|
| CN201110195504.XA CN102881631B (en) | 2011-07-13 | 2011-07-13 | Manufacturing method of semiconductor device |
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|---|---|---|---|
| CN201110195504.XA CN102881631B (en) | 2011-07-13 | 2011-07-13 | Manufacturing method of semiconductor device |
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| CN102881631B CN102881631B (en) | 2014-12-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448724A (en) * | 2014-08-22 | 2016-03-30 | 无锡华润上华半导体有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020096726A1 (en) * | 2000-12-26 | 2002-07-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| TW200746356A (en) * | 2005-08-15 | 2007-12-16 | Renesas Tech Corp | Semiconductor integrated circuit device and method for manufacture thereof |
| CN101252087A (en) * | 2007-02-16 | 2008-08-27 | 东京毅力科创株式会社 | SiCN film formation method and apparatus |
-
2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020096726A1 (en) * | 2000-12-26 | 2002-07-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| TW200746356A (en) * | 2005-08-15 | 2007-12-16 | Renesas Tech Corp | Semiconductor integrated circuit device and method for manufacture thereof |
| CN101252087A (en) * | 2007-02-16 | 2008-08-27 | 东京毅力科创株式会社 | SiCN film formation method and apparatus |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448724A (en) * | 2014-08-22 | 2016-03-30 | 无锡华润上华半导体有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
| CN105448724B (en) * | 2014-08-22 | 2019-03-22 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
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| Publication number | Publication date |
|---|---|
| CN102881631B (en) | 2014-12-17 |
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