CN103165519B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
- Publication number
- CN103165519B CN103165519B CN201110407484.8A CN201110407484A CN103165519B CN 103165519 B CN103165519 B CN 103165519B CN 201110407484 A CN201110407484 A CN 201110407484A CN 103165519 B CN103165519 B CN 103165519B
- Authority
- CN
- China
- Prior art keywords
- interlayer dielectric
- layer
- dielectric layer
- silicon layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides the manufacture method of a kind of semiconductor device, including: Semiconductor substrate is provided, is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；Form a silicon layer on the semiconductor substrate；Graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；Described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；Described oxidation-treated silicon layer is implemented an ion implanting；Form an interlayer dielectric layer on the semiconductor substrate, seal the open top of described groove completely.According to the present invention it is possible to form the air gap with relatively large-feature-size between described copper metal interconnection structure, thus effectively reducing the size of interconnection capacitance；Meanwhile, the injection technology by wherein adopting can also reduce the k value of described interlayer dielectric layer further.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method forming air gap.
Background technology
Along with reducing of feature sizes of semiconductor devices, the performance of great scale integrated circuit (VLSI) chip is increasingly by the restriction of interconnection capacitance.Impact in order to reduce described interconnection capacitance postpones and power consumption to reduce RC, and in low-k dielectric layer/copper metal interconnection process, integrated one technique forming air gap is a kind of very effective solution.
Traditional processing step forming air gap includes: first, as shown in Figure 1A, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 is formed interlayer dielectric layer 101 and low-k dielectric layer 102 from bottom to top, described low-k dielectric layer 102 is formed the first bronze medal metal interconnection structure 103, wherein, the top of described first bronze medal metal interconnection structure 103 is formed with cover layer 104, and described first bronze medal metal interconnection structure 103 is made up of the barrier layer of copper metal layer and the described copper metal layer of encirclement；Then, as shown in Figure 1B, described Semiconductor substrate 100 forms a metal level 105, to cover described copper metal interconnection structure 103, then, adopt a graphical described metal level 105 of photoresist 106；Then, as shown in Figure 1 C, adopt dry method etch technology etching described through patterned metal level 105, to form a groove 107 between described copper metal interconnection structure 103；Then, as shown in figure ip, forming an interlayer dielectric layer 108 on the semiconductor substrate, described interlayer dielectric layer 108 has relatively low coverage in described groove 107, thus forming an air gap 109 between described copper metal interconnection structure；Then, as referring to figure 1e, described interlayer dielectric layer 108 forms the second bronze medal metal interconnection structure 110.
When adopting above-mentioned technical process to form described air gap, owing to stacking layers of material forms the structure of a complexity, thus result in and be difficult between described copper metal interconnection structure to form the air gap with relatively large-feature-size, it is impossible to effectively reduce the size of described interconnection capacitance.
It is, therefore, desirable to provide a kind of method, to solve the problems referred to above.
Summary of the invention
For the deficiencies in the prior art, the present invention provides the manufacture method of a kind of semiconductor device, including: Semiconductor substrate is provided, is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；Form a silicon layer on the semiconductor substrate；Graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；Described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；Described oxidation-treated silicon layer is implemented an ion implanting；Form an interlayer dielectric layer on the semiconductor substrate, to seal the open top of described groove completely.
Further, chemical vapor deposition method is adopted to form described silicon layer.
Further, described silicon layer thickness be 50-400 angstrom.
Further, dry method etch technology is adopted to implement described etching.
Further, described etching process terminates when reaching described etching stopping layer.
Further, after described oxidation processes, the open-topped width of described groove is less than 45nm.
Further, the injection source of described ion implanting is carbon source or nitrogenous source.
Further, chemical vapor deposition method is adopted to form described interlayer dielectric layer.
Further, the material of described interlayer dielectric layer is the material with low-k.
The present invention also provides for the manufacture method of a kind of semiconductor device, including: Semiconductor substrate is provided, it is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；Form a silicon layer on the semiconductor substrate；Graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；Described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；Sequentially form an etching stopping layer and an interlayer dielectric layer on the semiconductor substrate, to seal the open top of described groove completely.
Further, chemical vapor deposition method is adopted to form described silicon layer.
Further, described silicon layer thickness be 50-400 angstrom.
Further, dry method etch technology is adopted to implement described etching.
Further, described etching process terminates when reaching described etching stopping layer.
Further, after described oxidation processes, the open-topped width of described groove is less than 45nm.
Further, chemical vapor deposition method is adopted to sequentially form described etching stopping layer and described interlayer dielectric layer.
Further, the material of described etching stopping layer is carbonitride of silicium or silicon oxide carbide.
Further, the material of described interlayer dielectric layer is the material with low-k.
According to the present invention it is possible to form the air gap with relatively large-feature-size between described copper metal interconnection structure, thus effectively reducing the size of interconnection capacitance；Meanwhile, the injection technology by wherein adopting can also reduce the k value of described interlayer dielectric layer further.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining principles of the invention.
In accompanying drawing:
Figure 1A-Fig. 1 E is the schematic cross sectional view of each step of traditional technique forming air gap；
Fig. 2 A-Fig. 2 E is the schematic cross sectional view of each step of the first embodiment of the method forming air gap that the present invention proposes；
Fig. 3 A-Fig. 3 F is the schematic cross sectional view of each step of the second embodiment of the method forming air gap that the present invention proposes；
Fig. 4 is the flow chart of the method forming air gap that the present invention proposes.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to the explaination present invention.Obviously, the execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions, the present invention can also have other embodiments.
Should be understood that, when using term " comprising " and/or " including " in this manual, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not preclude the presence or addition of other features one or more, entirety, step, operation, element, assembly and/or their combination.
With reference to Fig. 2 A-Fig. 2 E, illustrated therein is the schematic cross sectional view of each step of the first embodiment of the method forming air gap that the present invention proposes.
First, as shown in Figure 2 A, it is provided that Semiconductor substrate 200, the constituent material of described Semiconductor substrate 200 can adopt unadulterated monocrystal silicon, doped with the monocrystal silicon of impurity, silicon-on-insulator (SOI) etc..Exemplarily, in the present embodiment, described Semiconductor substrate 200 selects single crystal silicon material to constitute.Described Semiconductor substrate 200 is formed with isolation channel, buried regions, and various trap (well) structure, to put it more simply, diagram is omitted.
In described Semiconductor substrate 200, it is formed with various element, to put it more simply, diagram is omitted, etching stopping layer 201 and interlayer dielectric layer 202 that a stepped construction, described stepped construction include stacking gradually from bottom to top is only shown here.The material of described etching stopping layer 201 is carbonitride of silicium or silicon oxide carbide, and the material of described interlayer dielectric layer 202 is the material with low-k.
Described interlayer dielectric layer 202 is formed with the groove for filler metal interconnection line.Deposit a metal level, for instance copper metal layer, on described interlayer dielectric layer 202, and fill up the groove in described interlayer dielectric layer 202.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, be ground to the surface termination of described interlayer dielectric layer 202, described interlayer dielectric layer 202 is formed copper metal interconnecting wires 203.
Then, as shown in Figure 2 B, adopting chemical vapor deposition method to form a silicon layer 204 in described Semiconductor substrate 200, the thickness of described silicon layer 204 is 50-400 angstrom.
Then, as shown in Figure 2 C, graphical described silicon layer 204, and etch described silicon layer 204 and described interlayer dielectric layer 202 successively, to form a groove 205 between described copper metal interconnecting wires 203.Adopting dry method etch technology to implement described etching, described etching process terminates when reaching described etching stopping layer 201, and the etching gas used includes fluoro-gas (CF4、CHF3、CH2F2Deng), diluent gas (He, N2Deng) and oxygen.
Then, as shown in Figure 2 D, described silicon layer 204 is carried out an oxidation processes.After described oxidation processes, described silicon layer 204 is changed into silicon oxide layer 206；The top open part of described groove 205 is sealed by described silicon oxide layer 206, and the open-topped width stayed is less than 45nm, and its concrete size can be determined according to the expectation of described oxidation processes.
Then, as shown in Figure 2 E, chemical vapor deposition method is adopted to sequentially form described etching stopping layer 201 and described interlayer dielectric layer 202 in described Semiconductor substrate 200, the open top of described groove 205 is sealed by described etching stopping layer 201 completely, to form an air gap 207 between described copper metal interconnecting wires 203.It follows that complete the making of upper copper metal interconnecting wires and air gap by repeating said process.
With reference to Fig. 3 A-Fig. 3 F, illustrated therein is the schematic cross sectional view of each step of the second embodiment of the method forming air gap that the present invention proposes.
As shown in Figure 3A, it is provided that Semiconductor substrate 300, the constituent material of described Semiconductor substrate 300 can adopt unadulterated monocrystal silicon, doped with the monocrystal silicon of impurity, silicon-on-insulator (SOI) etc..Exemplarily, in the present embodiment, described Semiconductor substrate 300 selects single crystal silicon material to constitute.Described Semiconductor substrate 300 is formed with isolation channel, buried regions, and various trap (well) structure, to put it more simply, diagram is omitted.
In described Semiconductor substrate 300, it is formed with various element, to put it more simply, diagram is omitted, etching stopping layer 301 and interlayer dielectric layer 302 that a stepped construction, described stepped construction include stacking gradually from bottom to top is only shown here.The material of described etching stopping layer 301 is carbonitride of silicium or silicon oxide carbide, and the material of described interlayer dielectric layer 302 is the material with low-k.
Described interlayer dielectric layer 302 is formed with the groove for filler metal interconnection line.Deposit a metal level, for instance copper metal layer, on described interlayer dielectric layer 302, and fill up the groove in described interlayer dielectric layer 302.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, be ground to the surface termination of described interlayer dielectric layer 302, described interlayer dielectric layer 302 is formed copper metal interconnecting wires 303.
Then, as shown in Figure 3 B, adopting chemical vapor deposition method to form a silicon layer 304 in described Semiconductor substrate 300, the thickness of described silicon layer 304 is 50-400 angstrom.
Then, as shown in Figure 3 C, graphical described silicon layer 304, and etch described silicon layer 304 and described interlayer dielectric layer 302 successively, to form a groove 305 between described copper metal interconnecting wires 203.Adopting dry method etch technology to implement described etching, described etching process terminates when reaching described etching stopping layer 301, and the etching gas used includes fluoro-gas (CF4、CHF3、CH2F2Deng), diluent gas (He, N2Deng) and oxygen.
Then, as shown in Figure 3 D, described silicon layer 304 is carried out an oxidation processes.After described oxidation processes, described silicon layer 304 is changed into silicon oxide layer 306；The top open part of described groove 305 is sealed by described silicon oxide layer 306, and the open-topped width stayed is less than 45nm, and its concrete size can be determined according to the expectation of described oxidation processes.
Then, as shown in FIGURE 3 E, described silicon oxide layer 306 being implemented an ion implanting 307, the injection source of described ion implanting 307 is carbon source or nitrogenous source.After described ion implanting terminates, described silicon oxide layer 306 is changed into the silicon oxide layer doped with carbon or nitrogen element, its can as formed upper copper metal interconnecting wires time etching stopping layer.Meanwhile, when the injection source of described ion implanting 307 is carbon source, after described ion implanting terminates, described interlayer dielectric layer 302 is doped into carbon, thus can reduce the k value of described interlayer dielectric layer 302.
Then, as illustrated in Figure 3 F, adopt chemical vapor deposition method to form described interlayer dielectric layer 302 in described Semiconductor substrate 300, seal the open top of described groove 305 completely to form an air gap 308 between described copper metal interconnecting wires 303.It follows that complete the making of upper copper metal interconnecting wires and air gap by repeating said process.
So far, completing whole processing steps that method is implemented according to an exemplary embodiment of the present invention, it follows that the making of whole semiconductor device can be completed by subsequent technique, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention it is possible to form the air gap with relatively large-feature-size between described copper metal interconnection structure, thus effectively reducing the size of interconnection capacitance；Meanwhile, the injection technology by wherein adopting can also reduce the k value of described interlayer dielectric layer further.
With reference to Fig. 4, illustrated therein is the flow chart of the method forming air gap that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 401, it is provided that Semiconductor substrate, it is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；
In step 402, a silicon layer is formed on the semiconductor substrate；
In step 403, graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；
In step 404, described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；
In step 405, described oxidation-treated silicon layer is implemented an ion implanting；
In a step 406, form an interlayer dielectric layer on the semiconductor substrate, to seal the open top of described groove completely.
The present invention is illustrated already by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within present invention scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (17)
1. a manufacture method for semiconductor device, including:
Semiconductor substrate is provided, is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；
Form a silicon layer on the semiconductor substrate；
Graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；
Described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；
Described oxidation-treated silicon layer is implemented an ion implanting, and the injection source of described ion implanting is carbon source or nitrogenous source, and when the injection source of described ion implanting is carbon source, the dielectric constant of described interlayer dielectric layer reduces；
Form an interlayer dielectric layer on the semiconductor substrate, to seal the open top of described groove completely.
2. method according to claim 1, it is characterised in that adopt chemical vapor deposition method to form described silicon layer.
3. method according to claim 1 and 2, it is characterised in that described silicon layer thickness be 50-400 angstrom.
4. method according to claim 1, it is characterised in that adopt dry method etch technology to implement described etching.
5. method according to claim 4, it is characterised in that described etching process terminates when reaching described etching stopping layer.
6. method according to claim 1, it is characterised in that after described oxidation processes, the open-topped width of described groove is less than 45nm.
7. method according to claim 1, it is characterised in that adopt chemical vapor deposition method to form described interlayer dielectric layer.
8. the method according to claim 1 or 7, it is characterised in that the material of described interlayer dielectric layer is the material with low-k.
9. a manufacture method for semiconductor device, including:
Semiconductor substrate is provided, is formed with the etching stopping layer and interlayer dielectric layer that stack gradually from bottom to top on the semiconductor substrate, and in described interlayer dielectric layer, is formed with copper metal interconnecting wires；
Form a silicon layer on the semiconductor substrate；
Graphical described silicon layer, and etch described silicon layer and described interlayer dielectric layer successively, to form a groove between described copper metal interconnecting wires；
Described silicon layer is carried out an oxidation processes, to reduce the open top of described groove；
Sequentially form an etching stopping layer and an interlayer dielectric layer on the semiconductor substrate, to seal the open top of described groove completely.
10. method according to claim 9, it is characterised in that adopt chemical vapor deposition method to form described silicon layer.
11. the method according to claim 9 or 10, it is characterised in that the thickness of described silicon layer is 50-400 angstrom.
12. method according to claim 9, it is characterised in that adopt dry method etch technology to implement described etching.
13. method according to claim 12, it is characterised in that described etching process terminates when reaching described etching stopping layer.
14. method according to claim 9, it is characterised in that after described oxidation processes, the open-topped width of described groove is less than 45nm.
15. method according to claim 9, it is characterised in that adopt chemical vapor deposition method to sequentially form described etching stopping layer and described interlayer dielectric layer.
16. the method according to claim 9 or 15, it is characterised in that the material of described etching stopping layer is carbonitride of silicium or silicon oxide carbide.
17. the method according to claim 9 or 15, it is characterised in that the material of described interlayer dielectric layer is the material with low-k.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110407484.8A CN103165519B (en) | 2011-12-08 | 2011-12-08 | A kind of manufacture method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110407484.8A CN103165519B (en) | 2011-12-08 | 2011-12-08 | A kind of manufacture method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103165519A CN103165519A (en) | 2013-06-19 |
| CN103165519B true CN103165519B (en) | 2016-07-27 |
Family
ID=48588496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110407484.8A Active CN103165519B (en) | 2011-12-08 | 2011-12-08 | A kind of manufacture method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103165519B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10727114B2 (en) | 2017-01-13 | 2020-07-28 | International Business Machines Corporation | Interconnect structure including airgaps and substractively etched metal lines |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1856872A (en) * | 2003-09-30 | 2006-11-01 | 国际商业机器公司 | Adjustable self-aligned air gap dielectric for low capacitance wiring |
| CN101197423A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Method for making a self-converged memory material element for memory cell |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10348641A1 (en) * | 2003-10-15 | 2005-05-25 | Infineon Technologies Ag | Method for reducing parasitic couplings in circuits |
| US7473614B2 (en) * | 2004-11-12 | 2009-01-06 | Intel Corporation | Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer |
-
2011
- 2011-12-08 CN CN201110407484.8A patent/CN103165519B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1856872A (en) * | 2003-09-30 | 2006-11-01 | 国际商业机器公司 | Adjustable self-aligned air gap dielectric for low capacitance wiring |
| CN101197423A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Method for making a self-converged memory material element for memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103165519A (en) | 2013-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104658971B (en) | The method for manufacturing FINFET device | |
| US11239310B2 (en) | Seamless gap fill | |
| TW201138021A (en) | Semiconductor device and method for fabricating the same | |
| CN100459096C (en) | Process of making an integrated circuit comprising shallow trench isolation and corresponding integrated circuit | |
| CN113658868A (en) | Semiconductor element and manufacturing method thereof | |
| CN107785273A (en) | Semiconductor devices and its manufacture method | |
| CN107636810A (en) | The making based on etch stop region of bonding semiconductor structure | |
| TWI525823B (en) | Integrated circuit device and method for fabricating the same | |
| CN107785426A (en) | A kind of semiconductor devices and its manufacture method | |
| CN103489822B (en) | A kind of manufacture method of semiconductor device | |
| CN108695382B (en) | Semiconductor device and method for manufacturing the same | |
| CN103943551B (en) | A kind of manufacture method of semiconductor device | |
| CN103811538B (en) | With device income and the improved metal gate structure of productivity ratio | |
| CN103855021B (en) | A kind of manufacture method of FinFET | |
| CN103165519B (en) | A kind of manufacture method of semiconductor device | |
| CN105762105A (en) | Semiconductor device, manufacturing method of semiconductor device, and electronic device | |
| CN103151264B (en) | A kind of manufacture method of semiconductor devices | |
| CN107464741A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN106898575A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN103681462B (en) | A kind of manufacture method of semiconductor devices | |
| CN103094180B (en) | Manufacturing method of semiconductor device | |
| CN103515228B (en) | A kind of manufacture method of semiconductor device | |
| CN111916398B (en) | Method for manufacturing semiconductor device | |
| CN105990237B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN105097695B (en) | A kind of semiconductor devices and its manufacturing method, electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |