CN103681462B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN103681462B CN103681462B CN201210336591.0A CN201210336591A CN103681462B CN 103681462 B CN103681462 B CN 103681462B CN 201210336591 A CN201210336591 A CN 201210336591A CN 103681462 B CN103681462 B CN 103681462B
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- dielectric layer
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 144
- 238000005530 etching Methods 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000011229 interlayer Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 238000011049 filling Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000000470 constituent Substances 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 239000010949 copper Substances 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided；An etching stopping layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate；Form the groove and through hole for filling interconnection metal；Using plasma etch process removes the etching stopping layer below the through hole, wherein the removal process includes：Etching treatment procedure after first carrying out one, to remove etch residue material and the impurity to be formed in the groove and the through hole；Again using based on CF4、CO2The plasma etching is performed with CO etching gas.According to the present invention, when etching the etching stopping layer below the through hole, to the damage very little of the interlayer dielectric layer, and the material that the rear etching process is difficult to remove will not be formed in the bottom of the through hole, it is ensured that the side wall and the surface smoothness of bottom of the through hole.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to it is a kind of formed interconnected for filling metal groove and
The method that the etch stop layer below the through hole is removed after through hole.
Background technology
When the process node of semiconductor fabrication process reaches below 28nm, when forming the interconnecting metal layer of semiconductor devices
The interlayer dielectric layer used is generally made up of the material with ultralow dielectric, so that the RC for reducing semiconductor devices prolongs
Late.
Semiconductor devices generally has multilayer interconnection metal, forms groove and through hole for filling the interconnection metal
Technique comprises the following steps：First, as shown in Figure 1A there is provided Semiconductor substrate 100, formed in the Semiconductor substrate 100
There is active device layer, to put it more simply, the Semiconductor substrate 100 is only shown in diagram, then, in the Semiconductor substrate 100
On sequentially form an etching stopping layer 101 and an interlayer dielectric layer 102；Then, as shown in Figure 1B, in the interlayer dielectric layer
A metal hard mask layer 103 is formed on 102, then, is formed in the metal hard mask layer 103 for etching the through hole
Figure 104；Then, as shown in Figure 1 C, the interlayer dielectric layer 102 is formed again in the Semiconductor substrate 100, to cover
The metal hard mask layer 103 with the via hole image 104, next, in the interlayer dielectric layer 102 formed again
It is upper to form a photoresist layer 105 with the groove figure；Then, as shown in figure iD, lost successively using dry method etch technology
The upper strata interlayer dielectric layer 102 not covered by the photoresist layer 105 shown in needle drawing and not by the metal hard mask
Lower floor's interlayer dielectric layer 102 that layer 103 is covered, the etching process terminates at the etching stopping layer 101, so as to form use
In the groove 106 and through hole 107 of filling interconnection metal, then, the photoresist layer 105 is removed.
Connected to realize with the final of the active device layer, it is necessary to by the etching stopping layer of the lower section of the through hole 107
101 remove, when implementing the removal process using dry method etch technology, due to conveying plasma etch gases into etched cavity
Carrier gas be usually nitrogen（N2）, the copper-connection metal in the active device layer being exposed reacts in institute with nitrogen
State the bottom forming material of through hole 107（CuxNy）, this material is difficult to remove；Simultaneously as constituting the interlayer dielectric layer 102
Material has larger porosity, and main component is CF4Plasma etch gases to the side wall of the interlayer dielectric layer 102
Damage is also more serious, and therefore, above-mentioned phenomenon will influence the side wall of the through hole 107 and the surface smoothness of bottom, unfavorable
In the formation of subsequent copper metal barrier, the aggravation of the diffusion of copper metal is ultimately resulted in.
It is, therefore, desirable to provide a kind of method, to prevent the above-described problem from occurring.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate；An etching stopping layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate；Formed for filling interconnection gold
The groove and through hole of category；Using plasma etch process removes the etching stopping layer below the through hole, wherein described remove
Process includes：Etching treatment procedure after first carrying out one, to remove the etch residues to be formed in the groove and the through hole
Matter and impurity；Again using based on CF4、CO2The plasma etching is performed with CO etching gas.
Further, the etching stopping layer and the interlayer dielectric layer are formed using chemical vapor deposition method.
Further, the material of the etching stopping layer is SiCN or SiN.
Further, the constituent material of the interlayer dielectric layer is the material with ultralow dielectric.
Further, the dielectric constant of the interlayer dielectric layer is 2.45 or 2.2.
Further, the groove and through hole for being used to fill interconnection metal is formed using integral etch process.
Further, the integral etch process comprises the following steps：A metallic hard is formed on the interlayer dielectric layer to cover
Film layer, and form in the metal hard mask layer figure for etching the through hole；On the semiconductor substrate again
The interlayer dielectric layer is formed, to cover the metal hard mask layer with the via hole image, and is formed again described
Interlayer dielectric layer on formed one have the groove figure photoresist layer；Etched successively using dry method etch technology not by institute
State the interlayer dielectric layer that photoresist layer is covered and the interlayer dielectric layer not covered by the metal hard mask layer, the etching
Process terminates at the etching stopping layer.
Further, the metal hard mask layer is formed using physical gas-phase deposition or atom layer deposition process.
Further, the constituent material of the metal hard mask layer is TiN, BN, AlN or its arbitrary combination.
Further, the CF4Flow be 50-500sccm, the CO2Flow be 10-500sccm, the stream of the CO
Measure as 10-500sccm, the pressure of the plasma etching is 10-100mTorr, and power is 100-500W, processing time is
10-60s。
Further, in the rear before etching treatment procedure, in addition to using based on CF4And N2Etching gas perform institute
The step of stating plasma etching.
Further, the CF4Flow be 50-500sccm, the N2Flow be 10-500sccm, the plasma
The pressure of etching is 10-100mTorr, and power is 100-500W, and processing time is 10-60s.
According to the present invention, when etching the etching stopping layer below the through hole, to the damage of the interlayer dielectric layer very
It is small, and the material that the rear etching process is difficult to remove will not be formed in the bottom of the through hole, it is ensured that the side wall of the through hole
With the surface smoothness of bottom.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 D are schematically cuing open for each step that prior art forms the groove that metal is interconnected for filling and through hole
Face figure；
Fig. 2A-Fig. 2 E for it is proposed by the present invention formed for fill interconnection metal groove and through hole after remove the through hole
The schematic cross sectional view of each step of the method for the etch stop layer of lower section；
Fig. 3 for it is proposed by the present invention formed for fill interconnection metal groove and through hole after remove below the through hole
The flow chart of the method for etch stop layer.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Formation be used to filling the method that etch stop layer below the through hole is removed after the groove and through hole of interconnection metal.Obviously,
The execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.Presently preferred embodiments of the present invention
It is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
Below, reference picture 2A- Fig. 2 E and Fig. 3 come describe it is proposed by the present invention formed for fill interconnection metal groove and
The detailed step of the method for etch stop layer below the through hole is removed after through hole.
Reference picture 2A- Fig. 2 E, illustrated therein is the groove and through hole proposed by the present invention formed for filling interconnection metal
The schematic cross sectional view of each step of the method for etch stop layer below the through hole is removed afterwards.
First, as shown in Figure 2 A there is provided Semiconductor substrate 200, the constituent material of the Semiconductor substrate 200 can be used
Undoped with monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.As an example, in the present embodiment, institute
Semiconductor substrate 200 is stated to constitute from single crystal silicon material.Be formed with isolation structure in the Semiconductor substrate 200, it is described every
Be that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure from structure, the isolation structure will it is described partly
200 points of conductor substrate is nmos area and PMOS areas.Various traps (well) structure is also formed with the Semiconductor substrate 200.
Active device layer is formed with the Semiconductor substrate 200.The active device layer includes grid structure, as
One example, the grid structure may include that the gate dielectric stacked gradually from bottom to top, gate material layers and grid are covered firmly
Cover layer.The both sides of underface in the Semiconductor substrate 200 positioned at the grid structure are formed with source/drain region, in source/drain
It is channel region between area；Self-aligned silicide is formed with the grid structure and source/drain region.In the active device layer
One or more layers interconnecting metal layer is also formed with, to put it more simply, only showing the Semiconductor substrate 200 in diagram.
Next, sequentially forming an etching stopping layer in the Semiconductor substrate 200 using chemical vapor deposition method
201 and an interlayer dielectric layer 202.The material preferred SiCN or SiN of the etching stopping layer 201.The etching stopping layer 201 can
Damage to active device layer during preventing that subsequent etch is used to fill the groove and through hole of copper-connection metal.The interlayer
The constituent material of dielectric layer 202 is the material with ultralow dielectric, such as described dielectric constant is 2.45 or 2.2 material
Material.
Then, as shown in Figure 2 B, a metal hard mask layer 203, the metallic hard are formed on the interlayer dielectric layer 202
The constituent material of mask layer 203 can be selected as TiN, BN, AlN or its arbitrary combination.Form the metal hard mask layer
The 203 various suitable technologies that can be familiar with using those skilled in the art, for example physical gas-phase deposition or
Atom layer deposition process.
Next, form the figure 204 for etching the through hole in the metal hard mask layer 203, it include with
Lower step：One is formed on the metal hard mask layer 203 has the photoresist layer of the via hole image 204；Etching is not by institute
State the metal hard mask layer 203 that photoresist layer is covered；Remove the photoresist layer.In order to prevent from removing the photoresist layer institute
Damage of the cineration technics of use to the interlayer dielectric layer 202 of the lower section of metal hard mask layer 203, is generally forming the gold
A passivation layer is formed on the interlayer dielectric layer 202 before category hard mask layer 203, the constituent material of the passivation layer can be selected
TEOS is selected as, composition is mainly silica, is to use Si (OC2H5)4Generation is reacted for primary raw material.
Then, as shown in Figure 2 C, the interlayer dielectric layer 202 is formed again in the Semiconductor substrate 200, to cover
The metal hard mask layer 203 with via hole image 204, then, is formed on the interlayer dielectric layer 202 formed again
One has the photoresist layer 205 of the groove figure.In order to prevent during the subsequently copper metal interconnection layer of grinding formation to the layer
Between dielectric layer 202 cause damage, before the photoresist layer 205 is formed, on the interlayer dielectric layer 202 forming one adulterates
The silicon material layer of carbon, such as SiC layer.
Then, as shown in Figure 2 D, etched successively using dry method etch technology not by the photoresist layer 205 covered it is upper
Layer interlayer dielectric layer 202 and the lower floor's interlayer dielectric layer 202 not covered by the metal hard mask layer 203, it is described etched
Journey terminates at the etching stopping layer 201, so as to form the groove 206 and through hole 207 for being used to fill interconnection metal.It is above-mentioned
The technical process for forming the groove 206 and through hole 207 for being used to fill interconnection metal is generally referred to by those skilled in the art as one
Etching process procedure（all-in-one etch process）.Hereafter, the photoresist layer 205 is removed.
Then, as shown in Figure 2 E, using plasma etch process removes the etching stopping layer of the lower section of through hole 207
201, to realize the connection with the superiors' interconnecting metal layer in the active device layer.
The removal of the etching stopping layer 201 of the lower section of through hole 207 can be implemented by following two modes：
Embodiment one
First using based on CF4And N2Etching gas perform the plasma etching；Then, etched after performing one
（post-etch）Processing procedure, to remove the etch residue material to be formed in the groove 206 and the through hole 207 and miscellaneous
Matter；Finally, using based on CF4、CO2The plasma etching is performed again with CO etching gas, wherein, the CF4Stream
Measure as 50-500sccm, the N2Flow be 10-500sccm, the CO2Flow be 10-500sccm, the flow of the CO
For 10-500sccm, the pressure of the plasma etching twice is 10-100mTorr, and power is 100-500W, processing
Time is 10-60s.
Embodiment two
Etching treatment procedure after first carrying out one, it is residual to remove the etching to be formed in the groove 206 and the through hole 207
Stay material and impurity；Then, using based on CF4、CO2The plasma etching is performed with CO etching gas, wherein, it is described
CF4Flow be 50-500sccm, the CO2Flow be 10-500sccm, the flow of the CO is 10-500sccm, described
The pressure of plasma etching is 10-100mTorr, and power is 100-500W, and processing time is 10-60s.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed, next, in institute
State in groove 206 and the through hole 207 and sequentially form copper metal diffusion impervious layer and copper metal layer.According to the present invention, in etching
During etching stopping layer below the through hole, to the damage very little of the interlayer dielectric layer, and will not in the bottom of the through hole
Form the material that the rear etching process is difficult to remove（Such as CuxNy）, so as to ensure side wall and the surface of bottom of the through hole
Flatness.
Reference picture 3, illustrated therein is it is proposed by the present invention formed for fill interconnection metal groove and through hole after remove
The flow chart of the method for etch stop layer below the through hole, the flow for schematically illustrating whole manufacturing process.
There is provided Semiconductor substrate in step 301；
In step 302, an etching stopping layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate；
In step 303, the groove and through hole for filling interconnection metal are formed；
In step 304, using plasma etch process removes the etching stopping layer below the through hole.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, interconnecting metal layer is formed with the semiconductor substrate；
An etching stopping layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate；
Form the groove and through hole for filling interconnection metal；
Using plasma etch process removes the etching stopping layer below the through hole, wherein the removal process includes：First
Etching treatment procedure after performing one, to remove etch residue material and the impurity to be formed in the groove and the through hole；Again
Using based on CF4、CO2The plasma etching is performed with CO etching gas, to avoid in the interconnecting metal layer exposed
Metal be difficult to the substance C u that removes with gas reaction generation used in the plasma etchingxNy。
2. according to the method described in claim 1, it is characterised in that the etch stop is formed using chemical vapor deposition method
Layer and the interlayer dielectric layer.
3. method according to claim 1 or 2, it is characterised in that the material of the etching stopping layer is SiCN or SiN.
4. method according to claim 1 or 2, it is characterised in that the constituent material of the interlayer dielectric layer is with super
The material of low-k.
5. method according to claim 4, it is characterised in that the dielectric constant of the interlayer dielectric layer be 2.45 or
2.2。
6. according to the method described in claim 1, it is characterised in that form described for filling interconnection using integral etch process
The groove and through hole of metal.
7. method according to claim 6, it is characterised in that the integral etch process comprises the following steps：Described
A metal hard mask layer is formed on interlayer dielectric layer, and forms in the metal hard mask layer figure for etching the through hole
Shape；Interlayer dielectric layer is formed again on the semiconductor substrate, to cover the gold with the figure for etching the through hole
Belonging to hard mask layer, and form one on the interlayer dielectric layer formed again has the photoresist layer of groove figure；Lost using dry method
Carving technology etches the interlayer dielectric layer that is not covered by the photoresist layer and not covered by the metal hard mask layer successively
Interlayer dielectric layer, the etching process terminates at the etching stopping layer.
8. method according to claim 7, it is characterised in that use physical gas-phase deposition or ald work
Skill forms the metal hard mask layer.
9. method according to claim 8, it is characterised in that the constituent material of the metal hard mask layer be TiN, BN,
AlN or its arbitrary combination.
10. according to the method described in claim 1, it is characterised in that the CF4Flow be 50-500sccm, the CO2's
Flow is 10-500sccm, and the flow of the CO is 10-500sccm, and the pressure of the plasma etching is 10-
100mTorr, power is 100-500W, and processing time is 10-60s.
11. according to the method described in claim 1, it is characterised in that in the rear before etching treatment procedure, in addition to use
Based on CF4And N2Etching gas perform the plasma etching the step of.
12. method according to claim 11, it is characterised in that the CF4Flow be 50-500sccm, the N2's
Flow is 10-500sccm, and the pressure of the plasma etching is 10-100mTorr, and power is 100-500W, processing time
For 10-60s.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210336591.0A CN103681462B (en) | 2012-09-12 | 2012-09-12 | A kind of manufacture method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210336591.0A CN103681462B (en) | 2012-09-12 | 2012-09-12 | A kind of manufacture method of semiconductor devices |
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| CN103681462A CN103681462A (en) | 2014-03-26 |
| CN103681462B true CN103681462B (en) | 2017-08-01 |
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| JP7025189B2 (en) * | 2017-12-05 | 2022-02-24 | 株式会社ミツトヨ | Scale and its manufacturing method |
| CN108831859A (en) * | 2018-06-15 | 2018-11-16 | 武汉新芯集成电路制造有限公司 | The manufacturing method of through-hole |
| CN109712990A (en) * | 2019-01-02 | 2019-05-03 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
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| CN1271871A (en) * | 1999-04-26 | 2000-11-01 | 国际商业机器公司 | Corrosion technique of anisotropic nitride by inlay corrosion method |
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| US7045464B1 (en) * | 2004-11-15 | 2006-05-16 | International Business Machines Corporation | Via reactive ion etching process |
| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102324401A (en) * | 2011-09-28 | 2012-01-18 | 上海华力微电子有限公司 | Method for manufacturing copper interconnection structure |
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| CN1271871A (en) * | 1999-04-26 | 2000-11-01 | 国际商业机器公司 | Corrosion technique of anisotropic nitride by inlay corrosion method |
| CN1438681A (en) * | 2002-02-10 | 2003-08-27 | 台湾积体电路制造股份有限公司 | Method for removing stop-layer |
| US7045464B1 (en) * | 2004-11-15 | 2006-05-16 | International Business Machines Corporation | Via reactive ion etching process |
| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102324401A (en) * | 2011-09-28 | 2012-01-18 | 上海华力微电子有限公司 | Method for manufacturing copper interconnection structure |
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