CN102881567A - Dual-diagramming method - Google Patents
Dual-diagramming method Download PDFInfo
- Publication number
- CN102881567A CN102881567A CN2012104048547A CN201210404854A CN102881567A CN 102881567 A CN102881567 A CN 102881567A CN 2012104048547 A CN2012104048547 A CN 2012104048547A CN 201210404854 A CN201210404854 A CN 201210404854A CN 102881567 A CN102881567 A CN 102881567A
- Authority
- CN
- China
- Prior art keywords
- offset plate
- photoetching offset
- layer
- photoresist
- spin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The invention discloses a dual-diagramming method. The dual-diagramming method includes forming a medium layer and a hard masking layer on a substrate sequentially; forming and diagramming a first photoresist layer to form a first photoresist diagram structure; forming and diagramming a second photoresist layer to form a second photoresist diagram structure; forming a spin coating glass layer between the first photoresist diagram structure and the second photoresist diagram structure and exposing the tops of the first photoresist diagram structure and the second photoresist diagram structure; removing the first photoresist diagram structure and the second photoresist diagram structure; and taking the spin coating glass layer as a masking etching hard masking layer. Affection on subsequent etching process from etching by different types of photoresists can be eliminated effectively, so that etching shape can be well controlled in the subsequent etching process, and a larger process window can be obtained.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly a kind of Double-patterning method.
Background technology
Along with the development of semiconductor integrated circuit technology, require more circuit devcie is integrated on the very little chip area, it is more and more less that the semiconductor circuit device size is just becoming, and namely requires photoetching process can produce the dimension of picture of less live width.Yet because the wavelength that determines the light source in the photoetching process of device size is near its technological limit that can reduce, device size can not unrestrictedly dwindle near the limiting resolution of exposure bench.
Utilize the Dual graphing technical method can solve photoetching process resolution limit problem, form less dimension of picture.The method is to utilize the limit of photoetching process resolution so that the integrated level of circuit improves twice, the design configuration that is about to exceed the mask aligner limiting resolution is split into two layer patterns of the resolution that mask aligner can reach, and utilize two reticle, order is carried out Twi-lithography technique so that pattern density doubles on same substrate.
Figure 1A to Fig. 1 F and Fig. 2 A to Fig. 2 E are each step schematic diagram of the Double-patterning method of prior art.
Please first with reference to Figure 1A to Fig. 1 F, at first growth needs carries out patterned film layer structure 102 on silicon substrate 101; At film layer structure 102 grown on top layer of metal hard mask layers 103, then carry out coating, exposure, the development of photoetching anti-reflecting layer 104 for the first time and photoresist, again the litho pattern structure first time after developing 105 is carried out baking-curing, shown in Figure 1A; Then carry out gluing, exposure, the development of for the second time photoetching, just formed like this photoetching offset plate figure structure 105 and 106 behind the Twi-lithography on silicon substrate 101, as shown in Figure 1B, the photoetching offset plate figure density that this moment, Twi-lithography produced is the twice of a photoetching.Then shown in Fig. 1 C and 1D, utilize dry plasma etch, open anti-reflecting layer 104 and the metal hard mask layer 103 of photoresist below, photoetching offset plate figure is transferred on the metal hard mask layer 103 of below, then shown in Fig. 1 E, remove photoresist, clean, keep metal hard mask 103a.Utilize at last metal hard mask 103a as mask the film layer structure 102 below it to be carried out dry etching, required figure is delivered on the film layer structure 102, shown in Fig. 1 F.
Yet, in above-mentioned Double-patterning method, if the photoresist type difference that Twi-lithography uses may cause the difference of etching characteristic.
Please refer to Fig. 2 A because the photoresist model that adopts of Twi-lithography is different, after the development the first time photoetching offset plate figure structure 205 and the second time photoetching offset plate figure structure 206 height different, even its pattern is not identical yet.The characteristic of the etching of two kinds of photoresists also may be different, therefore in anti-reflecting layer 204 etching technics, easily cause anti-reflecting layer figure pattern difference, shown in Fig. 2 B, wherein for the first time the anti-reflecting layer graphic structure 204a that produces of photoetching offset plate figure structure 205 is variant on pattern with the anti-reflecting layer graphic structure 204b that photoetching offset plate figure structure 206 for the second time produces.Anti-reflecting layer 204 is opened the etching technics of laggard row metal hard mask layer 203.Because the difference of photoetching offset plate figure and anti-reflecting layer figure, may produce different metal hard mask pattern and critical size when causing the metal hard mask etching technics, shown in Fig. 2 C, wherein the metal hard mask 203b of the metal hard mask 203a of for the first time litho pattern generation and for the second time litho pattern generation is variant on pattern.The processing of removing photoresist after the metal hard mask etching, wash result has stayed different metal hard mask 203a and the 203b of pattern shown in Fig. 2 D.Shown in Fig. 2 E, utilize afterwards metal hard mask 203a and 203b to carry out follow-up etching technics to produce needed figure 202a and 202b for mask, because the difference of metal hard mask figure 203a and 203b pattern, cause adjacent in subsequent medium rete 202 etching technics two figure 202a and 202b also producing difference on the pattern and on the critical size.
Above because of the different caused photoresist thickness of two kinds of photoresist models and pattern difference in order to eliminate, the difference that finally causes etching characteristic, need to carry out fine optimization to photoetching process, this has also increased difficulty and the complexity of etching technics simultaneously more just so that lithographic process window becomes less.
Summary of the invention
Main purpose of the present invention is to provide a kind of Double-patterning method, has overcome in the prior art Double-patterning method to the harmful effect of subsequent etching technique, so that the process window of subsequent etching technique is larger.
For reaching above-mentioned purpose, the invention provides a kind of Double-patterning method, comprise the steps: on substrate, to form successively dielectric layer, hard mask layer; Form and graphical the first photoresist layer, to form the first photoetching offset plate figure structure; Form and graphical the second photoresist layer, to form the second photoetching offset plate figure structure, described the first photoresist layer is different from the type of described the second photoresist layer; Between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, form spin-on-glass layer, and the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure is exposed; Remove described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure; And, the described hard mask layer take described spin-on-glass layer as mask etching.
Optionally, between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, form spin-on-glass layer, and the step that expose at the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure comprises: form described spin-on-glass layer between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, the height of described spin-on-glass layer is more than or equal to the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure; And the described spin-on-glass layer of etching exposes the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure.
Optionally, the described spin-on-glass layer of etching comprises the method that exposes at the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure described spin-on-glass layer is anti-carved, and control anti-carves the degree of depth according to etch period.
Optionally, the described step that forms successively dielectric layer, hard mask layer on substrate also is included in described hard mask layer and forms anti-reflecting layer.
Optionally, the described anti-reflecting layer take described spin-on-glass layer as mask etching.
Optionally, the material of described hard mask layer is titanium or titanium nitride.
Optionally, the method for removing described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure is that dry method is removed photoresist or wet method is removed photoresist.
The invention has the advantages that by the dissimilar defined figure of photoetching offset plate figure structure is transferred on the spin-on-glass layer, thus, subsequent etching technique only need adopt a kind of material namely to can be used as the hard mask of etching to form required figure.Double-patterning method of the present invention can effectively be eliminated and adopt dissimilar photoresist photoetching on the impact of subsequent etching technique, so that can control better the pattern of etching in subsequent etching technique, critical size and final etching depth obtain larger process window.
Description of drawings
Figure 1A ~ Fig. 1 F is the cross-sectional view of a kind of method of Dual graphing in the prior art.
Fig. 2 A ~ Fig. 2 E is the cross-sectional view of a kind of method of Dual graphing in the prior art.
Fig. 3 A ~ Fig. 3 F is the cross-sectional view of the Double-patterning method of the specific embodiment of the invention.
Fig. 4 is the flow chart of the Double-patterning method of the specific embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Fig. 4 is the flow chart of the Double-patterning method of the specific embodiment of the invention, and with reference to figure 4, Double-patterning method comprises:
Step S41 forms dielectric layer, hard mask layer successively on substrate;
Step S42 forms and graphical the first photoresist layer, to form the first photoetching offset plate figure structure;
Step S43 forms and graphical the second photoresist layer, to form the second photoetching offset plate figure structure; Wherein the first photoresist layer is different from the type of described the second photoresist layer;
Step S44 form spin-on-glass layer between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, and the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure is exposed;
Step S45 removes described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure;
Step S46, the described hard mask layer take described spin-on-glass layer as mask etching.
Fig. 3 A to Fig. 3 F is the cross-sectional view of the Double-patterning method of the specific embodiment of the invention, for the embodiment that those skilled in the art be can better understand the present invention, describe the method for the Dual graphing of the specific embodiment of the present invention in detail below in conjunction with specific embodiment and Fig. 3 A to Fig. 3 F.
Please refer to Fig. 3 A, at first, provide substrate 201, the material of substrate 201 can be silicon, germanium or germanium silicon.In the present embodiment, substrate 201 is silicon substrate, and substrate 201 has been finished front road technique.Then form successively dielectric layer 202 and hard mask layer 203 on substrate 201, the material of dielectric layer 202 can be silicon dioxide (SiO2) or advanced low-k materials, and the material of hard mask layer 203 can be the metals such as titanium or titanium nitride.
Please refer to Fig. 3 B, better, also can on hard mask layer 203, form first anti-reflecting layer 204, in a preferred embodiment of the invention, anti-reflecting layer 204 is used for preventing that the light that passes the first photoresist layer is reflected back the first photoresist layer at substrate 201, thereby interference is incident to the light of the first photoresist layer and causes exposing inhomogeneous.The material of anti-reflecting layer 204 can be advanced low-k materials, the method that forms anti-reflecting layer 204 can make vapour deposition, for example, chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapour deposition (PVD) (PVD) and ald (ALD) etc.Then, carry out gluing, exposure, the development of the first photoresist layer, and to the baking-curing of the rear figure that develops, to form the first photoetching offset plate figure structure 205a.Then, utilize the photoresist of Second Type to form and graphical the second photoresist layer, to form the second photoetching offset plate figure structure 206a, the formation method as hereinbefore.Because Twi-lithography glue model is different, the first photoetching offset plate figure structure 205a is different with the height pattern of the photoetching offset plate figure structure 206a second time.Please continue with reference to figure 3B and Fig. 3 C, next, adopt the low temperature spin coating proceeding to form spin-on-glass layer (SOG) 207a, its material can make silicon dioxide, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass or advanced low-k materials, and spin-on-glass layer 207a has the upper surface of planarization.Concrete grammar for example is, first between the first photoetching offset plate figure structure 205a and the second photoetching offset plate figure structure 205b, fill spin-coating glass, so that the height of spin-on-glass layer 207 is greater than the top of the first photoetching offset plate figure structure 205a and the second photoetching offset plate figure structure 205b.Then, shown in Fig. 3 C, utilize and anti-carve the spin-on-glass layer 207a that the technique height of formation is lower than the first photoetching offset plate figure structure 205a and the second photoetching offset plate figure structure 205b top, wherein anti-carving the degree of depth can be controlled by etch period.Can normally carry out for the etching that makes follow-up antagonistic reflex layer 204 and hard mask layer 203, spin-on-glass layer 207a also need keep certain height.Thus, expose at the top of the first photoetching offset plate figure structure 205a and the second photoetching offset plate figure structure 205b, and the spin-on-glass layer 207a between the photoetching offset plate figure structure has an even surface.
Next, please refer to Fig. 3 D, remove photoetching offset plate figure structure 205a and the second photoetching offset plate figure structure 205b, the removal method for example is wet method degumming process or dry method degumming process, because these degumming process can not be damaged to spin-coating glass, therefore spin-on-glass layer 207a can be by complete reservation, it should be noted that, the photoetching offset plate figure structure side wall can the photoetching process through optimizing make its perpendicularity near 90 degree, after the photoetching offset plate figure structure was removed so, the sidewall pattern of the final spin-on-glass layer 207a that forms also can be near 90 degree.Thereafter, shown in Fig. 3 E, take spin-on-glass layer 207a as hard mask, successively etching anti-reflecting layer 204 and hard mask layer 203.The advantage of doing like this is, because the sidewall pattern of the final spin-on-glass layer 207a that forms is near 90 degree, just can eliminate thus because of two kinds of dissimilar photoresists as the formed figure difference of mask, therefore, by spin-on-glass layer 207a, the first photoetching offset plate figure structure 205a and the defined figure of the second photoetching offset plate figure structure 205b can be transferred to hard mask layer 203 exactly, thereby eliminated because of the impact of dissimilar photoresist on subsequent etching technique, so that has larger process window in subsequent etching technique.At last, take hard mask layer 203 as mask dielectric layer 202 is carried out etching, the figure that needs is the most at last transferred on the dielectric layer.It should be noted that, when adopting method of the present invention to realize needed pattern density and size, step in photoetching should be with live width and the interval counter-rotating of targeted graphical, when for example targeted graphical is 40nm live width and 60nm interval, then should be 60nm live width 40nm interval through the formed photoetching offset plate figure structure of Twi-lithography, thus, after the photoetching offset plate figure structure is removed, spin-on-glass layer will be 40nm live width and 60nm interval, could obtain targeted graphical thereby carry out subsequent etching take spin-on-glass layer as mask.The spin-on-glass layer 207a of subsequent etching process medium layer 202 top, anti-reflecting layer 204 and hard mask layer 203 constantly are consumed, final behind the etching technics of finishing dielectric layer 202, spin-on-glass layer 207a and the anti-reflecting layer 204 of its top have been consumed fully, and part consumes hard mask layer 203, the structure of formation shown in Fig. 3 F.Certainly, the spin-on-glass layer 207a of its top also may still have residue after dielectric layer 202 etchings are finished.
In sum, the present invention is after finishing the Twi-lithography exposure technology of prior art, directly do not utilize the formed photoetching offset plate figure structure of Twi-lithography as etch mask, remove again the photoetching offset plate figure structure but between the photoetching offset plate figure structure, form spin-on-glass layer, thereby the defined figure of photoetching offset plate figure structure is transferred on the spin-on-glass layer, thus, subsequent etching technique only need adopt a kind of material namely to can be used as the hard mask of etching to form required figure.Double-patterning method of the present invention can effectively be eliminated and adopt dissimilar photoresist photoetching on the impact of subsequent etching technique, so that can control better the pattern of etching in subsequent etching technique, critical size and final etching depth obtain larger process window.
Although the present invention discloses as above with preferred embodiment; right described many embodiment only give an example for convenience of explanation; be not to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion so that claims are described.
Claims (7)
1. a Double-patterning method is characterized in that, may further comprise the steps:
On substrate, form successively dielectric layer, hard mask layer;
Form and graphical the first photoresist layer, to form the first photoetching offset plate figure structure;
Form and graphical the second photoresist layer, to form the second photoetching offset plate figure structure, described the first photoresist layer is different from the type of described the second photoresist layer;
Between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, form spin-on-glass layer, and the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure is exposed;
Remove described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure; And
The described hard mask layer take described spin-on-glass layer as mask etching.
2. Double-patterning method according to claim 1, it is characterized in that, describedly between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, form spin-on-glass layer, and the step that expose at the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure comprises:
Form described spin-on-glass layer between described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure, the height of described spin-on-glass layer is more than or equal to the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure; And
The described spin-on-glass layer of etching exposes the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure.
3. Double-patterning method according to claim 2, it is characterized in that, the described spin-on-glass layer of etching comprises the method that exposes at the top of described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure described spin-on-glass layer is anti-carved, and control anti-carves the degree of depth according to etch period.
4. Double-patterning method according to claim 1 is characterized in that, the described step that forms successively dielectric layer, hard mask layer on substrate also comprises:
Form anti-reflecting layer at described hard mask layer.
5. Double-patterning method according to claim 4 is characterized in that, also comprises:
The described anti-reflecting layer take described spin-on-glass layer as mask etching.
6. Double-patterning method according to claim 1 is characterized in that, the material of described hard mask layer is titanium or titanium nitride.
7. Double-patterning method according to claim 1 is characterized in that, the method for removing described the first photoetching offset plate figure structure and described the second photoetching offset plate figure structure is that dry method is removed photoresist or wet method is removed photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210404854.7A CN102881567B (en) | 2012-10-22 | 2012-10-22 | A kind of Double-patterning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210404854.7A CN102881567B (en) | 2012-10-22 | 2012-10-22 | A kind of Double-patterning method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102881567A true CN102881567A (en) | 2013-01-16 |
| CN102881567B CN102881567B (en) | 2017-09-29 |
Family
ID=47482852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210404854.7A Active CN102881567B (en) | 2012-10-22 | 2012-10-22 | A kind of Double-patterning method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102881567B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752170A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Dual-patterning formation method |
| CN111403278A (en) * | 2019-11-29 | 2020-07-10 | 上海华力微电子有限公司 | Method for forming mandrel pattern |
| CN111477541A (en) * | 2020-04-23 | 2020-07-31 | 上海华力集成电路制造有限公司 | Self-aligned dual imaging technique |
| CN115903401A (en) * | 2022-12-22 | 2023-04-04 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double photoetching |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471232A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a semiconductor device pattern |
| CN101577212A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming method of semiconductor device |
| US20100055910A1 (en) * | 2008-08-29 | 2010-03-04 | Hynix Semiconductor Inc. | Exposure mask and method for forming semiconductor device using the same |
| CN102437049A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for simplifying double pattern exposure process of side wall definition |
| CN102466969A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Dual-patterning method |
-
2012
- 2012-10-22 CN CN201210404854.7A patent/CN102881567B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471232A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a semiconductor device pattern |
| CN101577212A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming method of semiconductor device |
| US20100055910A1 (en) * | 2008-08-29 | 2010-03-04 | Hynix Semiconductor Inc. | Exposure mask and method for forming semiconductor device using the same |
| CN102466969A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Dual-patterning method |
| CN102437049A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for simplifying double pattern exposure process of side wall definition |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752170A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Dual-patterning formation method |
| CN104752170B (en) * | 2013-12-30 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of Dual graphing |
| CN111403278A (en) * | 2019-11-29 | 2020-07-10 | 上海华力微电子有限公司 | Method for forming mandrel pattern |
| CN111477541A (en) * | 2020-04-23 | 2020-07-31 | 上海华力集成电路制造有限公司 | Self-aligned dual imaging technique |
| CN115903401A (en) * | 2022-12-22 | 2023-04-04 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double photoetching |
| CN115903401B (en) * | 2022-12-22 | 2024-03-12 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double lithography |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102881567B (en) | 2017-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10014175B2 (en) | Lithography using high selectivity spacers for pitch reduction | |
| US10049878B2 (en) | Self-aligned patterning process | |
| TWI493626B (en) | Methods of minimizing etch undercut and providing clean metal liftoff | |
| TWI614805B (en) | Lithographic technique incorporating varied pattern materials | |
| CN103839781A (en) | Method for forming fine patterns on semiconductor | |
| JP2013511153A (en) | Semiconductor device manufacturing using multiple exposure and blocking mask techniques to reduce design rule violations | |
| CN102446703A (en) | Dual patterning method | |
| CN107799402A (en) | The forming method of secondary figure | |
| US10685846B2 (en) | Semiconductor integrated circuit fabrication with pattern-reversing process | |
| CN102881567A (en) | Dual-diagramming method | |
| CN102446704B (en) | Dual patterning method | |
| CN104078366A (en) | Manufacturing method for fin structure of dual graphical fin type transistor | |
| US8835322B2 (en) | Method for reducing a minimum line width in a spacer-defined double patterning process | |
| JP2009239030A (en) | Method of manufacturing semiconductor device | |
| CN101452214B (en) | Exposure method, photolithography method and method for making through-hole | |
| JP2005159264A (en) | Method of forming pattern and method of manufacturing semiconductor device | |
| TWI443758B (en) | Method of forming gate conductor structures | |
| CN104157556B (en) | Metal hard mask opening lithographic method | |
| US7939451B2 (en) | Method for fabricating a pattern | |
| KR20090103520A (en) | Exposure mask and method for forming of semiconductor device using the same | |
| CN103050383A (en) | Method for eliminating side lobe pattern | |
| KR100843948B1 (en) | Method for forming fine pattern of semiconductor device | |
| KR101161797B1 (en) | Method for forming micropattern in semiconductor device | |
| US20150243511A1 (en) | Method of forming pattern and photo mask used therein | |
| CN110783263B (en) | Method for forming semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |