CN102874739A - Self-locking wafer bonding structure and manufacturing method thereof - Google Patents
Self-locking wafer bonding structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102874739A CN102874739A CN2012103827271A CN201210382727A CN102874739A CN 102874739 A CN102874739 A CN 102874739A CN 2012103827271 A CN2012103827271 A CN 2012103827271A CN 201210382727 A CN201210382727 A CN 201210382727A CN 102874739 A CN102874739 A CN 102874739A
- Authority
- CN
- China
- Prior art keywords
- bonding
- disk
- self
- locking
- groove structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a self-locking wafer bonding structure and a manufacturing method thereof. According to the self-locking wafer bonding structure, a self-locking micro structure is formed by embedding boss structures of a bonding upper wafer into groove structures of a bonding lower wafer, and the upper and lower bonding wafers are bonded through bonding of bonding materials between the lower groove structures and the upper boss structure or direct bonding of the lower groove structures and the upper boss structures. The manufacturing method is characterized in that the groove structures and the boss structures are manufactured before deposition and bonding of the bonding materials. The self-locking micro structure locks the boned silicon wafer by aligning with the position of the boned silicon wafer, so that the displacement of the wafer, which is caused by pressure and temperature load in the bonding process of the wafer, can be eliminated, so that the bonding alignment accuracy is improved.
Description
Technical field
The present invention relates to micro-electromechanical system field and technical field of micro and nano fabrication, particularly a kind of for micro-structural is made and the silicon of encapsulation and non-silica-based MEMS device, IC device, photoelectric device disk are integrated autoregistration wafer bonding structure and preparation method thereof.
Background technology
Wafer bonding refers to form a close-connected bonded layer by high temperature and high pressure environment between two kinds of different disks, thereby realizes the integrated of two kinds of different disks, as shown in Figure 1.Because wafer bonding can be realized the integrated of silica-based disk and non-silica-based disk, the wafer bonding technology has now developed into a core process technology of technical field of micro and nano fabrication.
Wafer bonding both can be used for the encapsulation of micro electro mechanical device, also can be used for the making of micro-nano device.Micro electro mechanical device is through the development of decades, and its chip technology is quite ripe, but a lot of chip does not but obtain practical application as product, and its one of the main reasons encapsulates problem exactly.Micro electro mechanical device generally adopts the microactuator suspension structure to carry out sensing or actuating, so its structure especially easily sustains damage in the encapsulation process such as scribing, paster.And employing wafer bonding technology is then protected micro electro mechanical device disk and cover plate wafer bonding in its bonding cavity with suspension structure by wafer level technique, thereby has simplified the encapsulation of micro electro mechanical device, has reduced the packaging cost of micro electro mechanical device.And by when wafer bonding, controlling the atmosphere of bonding cavity, such as vacuum bonding, then can further reduce the loss when micro-structural is worked in the bonding cavity, thus improve the performance after the micro electro mechanical device encapsulation, further improved the cost performance of micro electro mechanical device.In addition, by making circuit structure or other photoelectric device at the cover plate disk, then adopt the wafer bonding technology to realize that when simplifying the micro electro mechanical device encapsulation disk of micro electro mechanical device and reading circuit, optical-electric module is integrated, thereby further improved the integrated level of device, reduced the size of micro-system.
Because during wafer bonding, micro-structural is arranged generally on the bonding pad, wafer bonding need to be aimed at bonding with the micro-structural on the bonding pad.And for improving performance of devices behind the bonding, reduce the volume of device behind the bonding, wafer bonding is having higher requirement aspect the bonding aligning.At present, adopt litho machine to aim at and two kinds of alignment methods of the former bit alignment of bonder as the unification of disk alignment keys.Compare with alignment method of lithography machine, the former bit alignment of bonder has higher bonding alignment precision.Alignment method of lithography machine is to utilize litho machine that the bonding disk is aimed at, and the bonding disk is not to contacting the bonding disk on time, and the bonding disk is aimed at rear transferring to by the bonding fixture and carried out bonding in the bonder.Method by the pressurization that heats up in bonder contacts bonding with the bonding disk of aiming at.Because bonding pad is to transfer in the bonder by the bonding fixture after aiming at, needing to apply external force in the bonding process takes out silicon chip from the bonding fixture, thereby easily cause bonding disk position to be offset, side-play amount can reach tens to the hundreds of micron, so the bonding alignment precision descends greatly.In addition, because bonded interface bonding material softening and flowing, the upper lower silicon slice of bonding easily slides in bonding technology, has further increased the drift of bonding aligning, has reduced the bonding alignment precision in the bonding process.The former bit alignment of bonder is first bonding pad to be put into bonder, bonding pad is aimed in bonder after bonder heats up again, and the bonding silicon chip is in contact with one another, and then by exerting pressure silicon chip bonding under hot environment.Because wafer bonding generally is to carry out bonding by bonding material softening up and down bonding silicon chip under HTHP, in the bonding process up and down the bonding silicon chip bonded layer have certain flowability, therefore the pressure load in the bonding process is easy to make the bonding silicon chip to slide, thereby cause bonding to aim at drift, reduced the bonding alignment precision.In addition, the variations in temperature in the bonding process also can cause the variation of middle bonded layer residual stress, thereby further causes the movement of lower silicon slice on the bonding, reduces the bonding alignment precision.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of self-locking wafer bonding structure, the pressure load that is used for solving in the prior art bonding process slides the bonding silicon chip, thereby causes bonding to aim at drift, reduces the problem of bonding alignment precision.
Reach for achieving the above object other relevant purposes, the invention provides a kind of self-locking wafer bonding structure, described self-locking wafer bonding structure comprises disk under the bonding that is provided with groove structure and is provided with disk on the bonding of boss structure; Disk disk on described bonding is embedded in the bonding that cooperates of boss structure by described groove structure under the described bonding, forms self-locking structure.
Preferably, the height of described boss structure is more than or equal to the degree of depth of groove structure.
Preferably, be provided with the bonding material layer in the described groove structure, the height sum of the thickness of described bonding material layer and described boss structure is more than or equal to the degree of depth of described groove structure.
Preferably, described groove structure or described are provided with the bonding material layer outward, and the thickness of described bonding material layer is less than the height of described boss structure; Described boss structure contacts cooperation with described groove structure.
Preferably, disk is provided with circuit structure under the described bonding; Disk is provided with sensor microstructure on the described bonding.
The present invention also provides a kind of self-locking wafer bonding construction manufacturing method, and this preparation method may further comprise the steps:
1) disk is made groove structure under bonding;
2) disk is made boss structure on bonding;
3) disk on disk under the bonding and the bonding is aimed at bonding.
Preferably, behind the groove structure in forming step 1) within it section's deposition form first key condensation material layer; Forming step 2) in boss structure after at an upper portion thereof deposition form the second bonding material layer; The thickness of described first key condensation material layer, the second bonding material layer and with the height sum of the described boss degree of depth more than or equal to described groove structure.
Preferably, disk is provided with the first film layer under the bonding on the described step 1), and described groove structure is formed in this first film layer; Described step 2) disk is provided with the second thin layer on the bonding on, and described groove structure is formed in this second thin layer.
Preferably, described step 1) disk under bonding also comprises the step for preparing circuit structure before making groove structure; Described step 2) before making boss structure, disk on the bonding also comprises the step for preparing sensor microstructure.
The present invention forms a stable self-locking structure, and the bonding silicon chip can't produce displacement when bearing ambient pressure and variations in temperature up and down, thereby has improved the bonding precision.In the bonding process, although bonding material also can soften, but owing to being subjected to the restriction of self-locking micro-structural, bonding material after softening can't flow, thereby disk slides under extraneous pressure and temperature loading condition in the time of can avoiding bonding, reduce bonding and aimed at drift, improved the bonding alignment precision.
Description of drawings
Fig. 1 is shown as traditional disk bonding structure.
Fig. 2 is shown as a kind of example structure schematic diagram of self-locking wafer bonding structure of the present invention.
Fig. 3-1 is shown as self-locking wafer bonding structure fabrication flow process proposed by the invention to Fig. 3-7;
Wherein, Fig. 3-1 is shown as disk deposition one deck mask layer under bonding;
Fig. 3-2 is shown as the figure of producing the self-locking groove structure at mask layer;
Fig. 3-3 is shown as by etching the figure of self-locking groove structure is transferred under the bonding on the disk;
Fig. 3-4 is shown as and removes the mask material on the disk under the bonding;
Fig. 3-5 is shown as at self-locking groove structure inside deposition bonding material;
Fig. 3-6 is shown as disk making self-locking boss structure on bonding, and deposits bonding material at the self-locking boss structure;
Fig. 3-7 is shown as on the bonding under the disk and bonding disk and aims at bonding;
Fig. 4 is shown as self-locking wafer bonding structure and is used for circuit wafer and sensor disk aligning bonding.
Fig. 5 is shown as the self-locking wafer bonding bonding structure without middle bonded layer.
Fig. 6 is shown as by make the self-locking wafer bonding structure that low groove and convex platform structure obtain at bonding disk film.
Fig. 7-1 is shown as disk making self-locking groove structure under bonding, and at the peripheral deposition of self-locking groove structure bonding material;
Fig. 7-2 is shown as disk making self-locking boss structure on bonding, and at the peripheral deposition of self-locking boss structure bonding material;
Fig. 7-3 is shown as on the bonding under the disk and bonding disk and aims at bonding.
The element numbers explanation
The specific embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by the other different specific embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also the embodiment schematic diagram of a kind of self-locking wafer bonding structure shown in Figure 2.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
See also a kind of example structure schematic diagram of self-locking wafer bonding structure shown in Figure 2.The present invention proposes whole autoregistration wafer bonding and comprises disk 11 under the bonding, self-locking groove 14, bonding material layer 15, five parts such as disk 16, self-locking boss 17 on the bonding. Bonding disk 11 and 16 carries out wafer bonding by bonding material layer 15 up and down.Self-locking groove structure 14 is produced under the bonding on the disk 11, self-locking boss structure 17 is produced on the bonding on the disk 16, self-locking boss structural bond is embedded on the self-locking groove structure when closing, and bonding material layer 15 then is distributed between self-locking groove structure and the self-locking boss structure.The length and width size of the wide size of self-locking convex director and self-locking groove is suitable, after the self-locking boss structure is embedded in the self-locking groove structure, will form a stable self-locking structure.The bonding silicon chip can't produce displacement when bearing ambient pressure and variations in temperature up and down, thereby improve the bonding precision.In the bonding process, although bonding material also can soften, but owing to being subjected to the restriction of self-locking micro-structural, bonding material after softening can't flow, thereby disk slides under extraneous pressure and temperature loading condition in the time of can avoiding bonding, reduce bonding and aimed at drift, improved the bonding alignment precision.
In self-locking wafer bonding structure, the bonding method that can select to have bonding material layer 15 also can be selected the bonding method without bonding material layer 15.When selecting the bonding method with bonded layer, can inlay the formation self-locking structure for the boss structure 17 of disk 16 on the groove structure 14 that guarantees disk 11 under the bonding and the bonding, require the degree of depth of groove to be greater than the thickness of bonding material layer 15.And when the bonding method of selecting without bonded layer, finish to contact for the boss structure of disk on the groove structure that guarantees disk under the bonding and the bonding, require boss structure otherwise less than the degree of depth of groove structure.
Embodiment one
See also Fig. 3-1 to shown in Fig. 3-7, be the process chart of structure shown in Figure 2.Select the bonding method with bonded layer 15 to aim at bonding, the degree of depth of disk groove structure is greater than the thickness of bonded layer under the bonding, thereby guarantees that bonding rearward recess structure and boss structure can form physical contact.Concrete steps are as follows:
(1) provide disk 11 under the bonding, disk 11 deposition one deck mask layers 12 under this bonding, its flow process schematic cross-section is seen Fig. 3-1.The material of disk belongs to the common practise of this area under the described bonding, does not repeat them here.
(2) produce the figure of self-locking groove structure by photoetching or other lithographic methods on mask layer 12, its flow process schematic cross-section is seen Fig. 3-2.
(3) by etching the figure of self-locking groove structure is transferred under the bonding on the disk 11, disk forms self-locking groove structure 14 under bonding.Its flow process schematic cross-section is seen Fig. 3-3.
(4) remove the residue mask layer on the disk 11 under the bonding, its flow process schematic cross-section is seen Fig. 3-4.
(5) at the inside deposition first key condensation material layer 15 of self-locking groove structure 14, its flow process schematic cross-section is seen Fig. 3-5.
(6) provide disk 16 on the bonding, on disk 16 on the described bonding, make the self-locking boss structure 17 corresponding with above-mentioned groove location by techniques such as etchings, and at this self-locking boss structure 17 depositions the second bonding material layer 15, its flow process schematic cross-section is seen Fig. 3-6.The material of disk belongs to the common practise of this area under the described bonding, does not repeat them here.
(7) disk under disk on the bonding and the bonding is aimed at bonding, the step of this aligning bonding can be carried out in vacuum or particular atmosphere environment, thereby realizes the control of atmosphere in the para-linkage chamber.Its flow process schematic cross-section is seen Fig. 3-7.
Embodiment two
See also another embodiment shown in Figure 4.Its concrete step of preparation process is identical with embodiment one, the main distinction is to have cmos circuit structure 18 under the bonding on the disk, and has the sensor microstructure 19 of the suspension corresponding with this cmos circuit structure 18 on the bonding on the disk, the preparation technology of the sensor microstructure 19 of described cmos circuit structure 18 and described suspension belongs to the common practise of this area, again repeats no more.Undertaken cmos circuit and sensor microstructure integrated by the self-locking bonding structure.
The thickness sum of the second bonding material layer that deposits on the first key condensation material layer of deposition, the described boss structure in the described groove structure in the present embodiment, and the height sum of described boss structure are greater than the degree of depth of described groove.The sensor microstructure 19 of being convenient to suspend on the disk on the bonding is accommodated in the gap that forms behind the wafer bonding up and down with bonding.
Embodiment three
The implementation step of embodiment three part is identical with embodiment one, and the main distinction is that bonding selects the bonding (such as Si-Si direct bonding, silex glass Direct Bonding etc.) without the bonding material layer, thereby has avoided the manufacture craft of bonding material layer.Owing to having avoided the making of bonding material layer, therefore the height of disk convex platform structure should be equal to or greater than the degree of depth of disk upper groove structure under the bonding on the bonding, thereby the convex platform structure can contact fully with the low groove structure in the assurance bonding process, forms effective bonding.
The concrete technology step is as follows:
(1) provide disk 11 under the bonding, in the present embodiment, the material of disk is silicon or glass etc. under this bonding.Disk 11 deposition one deck mask layers under this bonding.
(2) on this mask layer, produce the figure of self-locking groove structure by methods such as photoetching.
(3) by etching the figure of self-locking groove structure is transferred under the bonding on the disk 11, disk 11 forms self-locking groove structures 14 under this bonding.
(4) remove under the described bonding remaining mask layer on the disk 11.
(5) provide disk 16 on the bonding, the material of disk is the substrates such as silicon or glass on this bonding.Its with described bonding under the material of disk 11 can be identical, also can be different.Disk adopts the technique such as etching to produce self-locking boss structure 17 on bonding.
(6) disk under disk on the bonding and the bonding is aimed at bonding, its final structural representation that forms is seen Fig. 5.
Embodiment four
Its implementation step part is identical with embodiment one, the main distinction is that the boss structure of disk on the groove structure of disk under the bonding and the bonding is not directly to make at the bottom of bonding radical, but make being deposited on the suprabasil film of bonding, its structural representation is as shown in Figure 6.The concrete technology step is as follows:
(1) provides disk 11 under the bonding, disk 11 deposition the first film layers 20 under this bonding.The material of this first film layer is polysilicon, monocrystalline silicon or epitaxial material.
(2) on this first film layer 20, produce the self-locking groove structure by photoetching or other processes.
(3) provide disk 16 on the bonding, disk 16 depositions the second thin layer 21 on this bonding.The material of this second thin layer 21 is polysilicon, monocrystalline silicon or epitaxial material.
(4) adopt photoetching or other processes to produce the self-locking boss structure corresponding with above-mentioned self-locking groove structure at this second thin layer 21.
(5) disk under disk on the bonding and the bonding is aimed at bonding, its final structural representation that forms is seen Fig. 6.
Embodiment five
Its implementation step part is identical with embodiment one, and the main distinction is that the bonding material layer is not to be produced in the groove structure, but is produced on the groove structure periphery.Also can only be sitting in the boss structure periphery.The thickness of described bonding material layer is less than the height of described boss structure; Described boss structure contacts cooperation with described groove structure.Wafer bonding is realized by the bonding material layer, the self-locking realization of groove structure about alignment precision then passes through.Its structural representation is shown in Fig. 7-3.The concrete technology step is as follows:
(1) provides disk 11 under the bonding, disk 11 deposition one deck mask layers 12 under this bonding.The material of disk belongs to the common practise of this area under the described bonding, does not repeat them here.
(2) on mask layer 12, produce the figure of self-locking groove structure by photoetching or other lithographic methods.
(3) by etching the figure of self-locking groove structure is transferred under the bonding on the disk 11, disk forms self-locking groove structure 14 under bonding.
(4) remove the residue mask layer on the disk 11 under the bonding.
(5) at the outside deposition first key condensation material layer 15 of self-locking groove structure 14, its flow process schematic cross-section is seen Fig. 7-1.
(6) provide disk 16 on the bonding, on disk 16 on the described bonding, make the self-locking boss structure 17 corresponding with above-mentioned groove location by techniques such as etchings, and at these self-locking boss structure 17 peripheral deposition the second bonding material layers 15, its flow process schematic cross-section is seen Fig. 7-2.The material of disk belongs to the common practise of this area under the described bonding, does not repeat them here.
(7) disk under disk on the bonding and the bonding is aimed at bonding, guarantee that the convex platform structure can contact fully with the low groove structure in the bonding process, form effective bonding.The step of this aligning bonding can be carried out in vacuum or particular atmosphere environment, thereby realizes the control of atmosphere in the para-linkage chamber.Its flow process schematic cross-section is seen Fig. 7-3.
The present invention forms a stable self-locking structure, and the bonding silicon chip can't produce displacement when bearing ambient pressure and variations in temperature up and down, thereby has improved the bonding precision.In the bonding process, although bonding material also can soften, but owing to being subjected to the restriction of self-locking micro-structural, bonding material after softening can't flow, thereby disk slides under extraneous pressure and temperature loading condition in the time of can avoiding bonding, reduce bonding and aimed at drift, improved the bonding alignment precision.
In sum, the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (9)
1. a self-locking wafer bonding structure is characterized in that, described self-locking wafer bonding structure comprises disk under the bonding that is provided with groove structure and is provided with disk on the bonding of boss structure; Disk disk on described bonding is embedded in the bonding that cooperates of boss structure by described groove structure under the described bonding, forms self-locking structure.
2. self-locking wafer bonding structure according to claim 1 is characterized in that, the height of described boss structure is more than or equal to the degree of depth of groove structure.
3. self-locking wafer bonding structure according to claim 1 is characterized in that, is provided with the bonding material layer in the described groove structure, and the height sum of the thickness of described bonding material layer and described boss structure is more than or equal to the degree of depth of described groove structure.
4. self-locking wafer bonding structure according to claim 1 is characterized in that, described groove structure or described are provided with the bonding material layer outward, and the thickness of described bonding material layer is less than the height of described boss structure; Described boss structure contacts cooperation with described groove structure.
5. according to claim 1 to the described self-locking wafer bonding of 4 any one structure, it is characterized in that, disk is provided with circuit structure under the described bonding; Disk is provided with sensor microstructure on the described bonding.
6. a self-locking wafer bonding construction manufacturing method is characterized in that, this preparation method may further comprise the steps:
1) disk is made groove structure under bonding;
2) disk is made boss structure on bonding;
3) disk on disk under the bonding and the bonding is aimed at bonding.
7. self-locking wafer bonding construction manufacturing method according to claim 6 is characterized in that, behind the groove structure in forming step 1) within it section's deposition form first key condensation material layer; Forming step 2) in boss structure after at an upper portion thereof deposition form the second bonding material layer; The thickness of described first key condensation material layer, the second bonding material layer and with the height sum of the described boss structure degree of depth more than or equal to described groove structure.
8. according to claim 6 or 7 described self-locking wafer bonding construction manufacturing methods, it is characterized in that, disk is provided with the first film layer under the bonding on the described step 1), and described groove structure is formed in this first film layer; Described step 2) disk is provided with the second thin layer on the bonding on, and described groove structure is formed in this second thin layer.
9. self-locking wafer bonding construction manufacturing method according to claim 6 is characterized in that, described step 1) disk under bonding also comprises the step for preparing circuit structure before making groove structure; Described step 2) before making boss structure, disk on the bonding also comprises the step for preparing sensor microstructure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103827271A CN102874739A (en) | 2012-10-10 | 2012-10-10 | Self-locking wafer bonding structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103827271A CN102874739A (en) | 2012-10-10 | 2012-10-10 | Self-locking wafer bonding structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102874739A true CN102874739A (en) | 2013-01-16 |
Family
ID=47476305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103827271A Pending CN102874739A (en) | 2012-10-10 | 2012-10-10 | Self-locking wafer bonding structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102874739A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103818876A (en) * | 2014-03-12 | 2014-05-28 | 杭州霆科生物科技有限公司 | Rapid bonding method for micro-fluidic chip |
| CN105097777A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN105572421A (en) * | 2014-10-17 | 2016-05-11 | 北京自动化控制设备研究所 | Multilayer bonding method based on vibration beam accelerometer of full quartz structure |
| CN105584987A (en) * | 2014-11-12 | 2016-05-18 | 精工爱普生株式会社 | Physical quantity sensor, method for manufacturing physical quantity sensor, electronic device, and moving body |
| CN107404062A (en) * | 2017-05-12 | 2017-11-28 | 浙江澍源智能技术有限公司 | A kind of die bonding method |
| CN111599693A (en) * | 2019-02-20 | 2020-08-28 | 中科院微电子研究所昆山分所 | Bonding method |
| CN113972900A (en) * | 2021-12-22 | 2022-01-25 | 深圳新声半导体有限公司 | Bonding method and bonding structure of surface acoustic wave filter |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1228615A (en) * | 1998-03-11 | 1999-09-15 | 国际商业机器公司 | High performance chip packaging and method |
| JP2005107452A (en) * | 2003-10-02 | 2005-04-21 | Sony Corp | Method for manufacturing liquid crystal display element, liquid crystal display element, projection display apparatus and method for laminating substrate |
| US20060246630A1 (en) * | 2005-04-27 | 2006-11-02 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
| US7375425B2 (en) * | 2003-02-06 | 2008-05-20 | Intel Corporation | Fabricating stacked chips using fluidic templated-assembly |
| CN101552263A (en) * | 2009-05-18 | 2009-10-07 | 中国电子科技集团公司第十三研究所 | Wafer-level packaging of chip and packaging method thereof |
| CN101867080A (en) * | 2010-05-21 | 2010-10-20 | 中国科学院上海微系统与信息技术研究所 | Bulk silicon micro mechanic resonator and manufacturing method thereof |
| TW201210098A (en) * | 2010-08-20 | 2012-03-01 | Txc Corp | Resonating device wafer level package structure with enhanced air-tightness |
| CN102627253A (en) * | 2012-04-24 | 2012-08-08 | 江苏物联网研究发展中心 | Self-aligning packaging structure for micro-electromechanical system (MEMS) device and manufacture method thereof |
-
2012
- 2012-10-10 CN CN2012103827271A patent/CN102874739A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1228615A (en) * | 1998-03-11 | 1999-09-15 | 国际商业机器公司 | High performance chip packaging and method |
| US7375425B2 (en) * | 2003-02-06 | 2008-05-20 | Intel Corporation | Fabricating stacked chips using fluidic templated-assembly |
| JP2005107452A (en) * | 2003-10-02 | 2005-04-21 | Sony Corp | Method for manufacturing liquid crystal display element, liquid crystal display element, projection display apparatus and method for laminating substrate |
| US20060246630A1 (en) * | 2005-04-27 | 2006-11-02 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
| CN101552263A (en) * | 2009-05-18 | 2009-10-07 | 中国电子科技集团公司第十三研究所 | Wafer-level packaging of chip and packaging method thereof |
| CN101867080A (en) * | 2010-05-21 | 2010-10-20 | 中国科学院上海微系统与信息技术研究所 | Bulk silicon micro mechanic resonator and manufacturing method thereof |
| TW201210098A (en) * | 2010-08-20 | 2012-03-01 | Txc Corp | Resonating device wafer level package structure with enhanced air-tightness |
| CN102627253A (en) * | 2012-04-24 | 2012-08-08 | 江苏物联网研究发展中心 | Self-aligning packaging structure for micro-electromechanical system (MEMS) device and manufacture method thereof |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103818876A (en) * | 2014-03-12 | 2014-05-28 | 杭州霆科生物科技有限公司 | Rapid bonding method for micro-fluidic chip |
| CN105097777A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN105097777B (en) * | 2014-04-21 | 2019-01-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN105572421A (en) * | 2014-10-17 | 2016-05-11 | 北京自动化控制设备研究所 | Multilayer bonding method based on vibration beam accelerometer of full quartz structure |
| CN105584987A (en) * | 2014-11-12 | 2016-05-18 | 精工爱普生株式会社 | Physical quantity sensor, method for manufacturing physical quantity sensor, electronic device, and moving body |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN105185719B (en) * | 2015-06-24 | 2018-04-17 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of bayonet type |
| CN107404062A (en) * | 2017-05-12 | 2017-11-28 | 浙江澍源智能技术有限公司 | A kind of die bonding method |
| CN111599693A (en) * | 2019-02-20 | 2020-08-28 | 中科院微电子研究所昆山分所 | Bonding method |
| CN111599693B (en) * | 2019-02-20 | 2022-07-12 | 昆山微电子技术研究院 | Bonding method |
| CN113972900A (en) * | 2021-12-22 | 2022-01-25 | 深圳新声半导体有限公司 | Bonding method and bonding structure of surface acoustic wave filter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102874739A (en) | Self-locking wafer bonding structure and manufacturing method thereof | |
| CN103890906B (en) | For the method for the flexible silicon base of manufacturing machine | |
| CN105097809B (en) | Mechanical stress uncoupling in semiconductor devices | |
| CN101450786B (en) | Pressure sensor for micro electro-mechanical system and production method thereof | |
| CN101837944A (en) | Method for forming a gyroscope and accelerometer | |
| CN103922267A (en) | Inertial sensor production and wafer level package process based on MEMS (micro-electromechanical system) | |
| CN103824787B (en) | Wafer bonding method based on bonding agent | |
| CN104576482A (en) | Wafer alignment method | |
| CN102804337A (en) | A method of bonding by molecular bonding | |
| CN103674355A (en) | Suspended force-sensitive sensor chip capable of eliminating encapsulation stress and manufacture method thereof | |
| CN105043439A (en) | Sensor integration device and production method thereof | |
| CN101475298B (en) | Method for moulding disc grade glass device by using micro-mould | |
| CN109292729B (en) | Preparation method of all-silicon environment isolation MEMS device | |
| CN104249992B (en) | Alignment methods between wafer and wafer | |
| CN103449358A (en) | Manufacturing method of closed cavity of micro-electromechanical system (MEMS) | |
| CN105366632A (en) | Monolithic integration of stress isolation feautures in a microelectromechanical system (mems) structure | |
| WO2016078452A1 (en) | Positioning method in microprocessing process of bulk silicon | |
| CN106800273A (en) | Method for forming mark on back of substrate | |
| Kurz et al. | High precision low temperature direct wafer bonding technology for wafer-level 3D ICs manufacturing | |
| CN102328900A (en) | Cavity manufacturing method | |
| CN102811942B (en) | For the manufacture of method and the microelectromechanicdevices devices of microelectromechanicdevices devices | |
| CN103407958A (en) | Production method of cavity-SOI (Silicon On Insulator) | |
| CN104649218B (en) | A kind of wafer-level vacuum encapsulating method | |
| CN105486445B (en) | Pressure sensor and its manufacture method | |
| CN104773706B (en) | Silica-based magnetic material substrate fabrication method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130116 |