CN102868292B - A kind of driving interlock circuit of anti-bridge arm direct pass - Google Patents
A kind of driving interlock circuit of anti-bridge arm direct pass Download PDFInfo
- Publication number
- CN102868292B CN102868292B CN201210386366.8A CN201210386366A CN102868292B CN 102868292 B CN102868292 B CN 102868292B CN 201210386366 A CN201210386366 A CN 201210386366A CN 102868292 B CN102868292 B CN 102868292B
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- bridge
- circuit
- control signal
- output circuit
- signal pwm
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/20—Interlocking, locking, or latching mechanisms
Abstract
The present invention relates to brachium pontis drive circuit technical field, refer to a kind of driving interlock circuit of anti-bridge arm direct pass especially.Comprise A bridge output circuit, B bridge output circuit interlocking signal control circuit, described interlocking signal control circuit blocks A bridge output circuit when B bridge control signal PWM_B is effective, described interlocking signal control circuit blocks B bridge output circuit when A bridge control signal PWM_A is effective, therefore between two dead bands, when the control signal of one of them switching tube is effective, interlocking signal control circuit exports the output circuit that locking signal blocks another switching tube, this output circuit is exported invalid, the switching tube that this output circuit controls cannot conducting, therefore between these two dead bands, a switching tube conducting is had all the time at the most, stop the problem that the conducting simultaneously of two switching tubes causes bridge arm direct pass and then damages switching tube.
Description
Technical field
The present invention relates to brachium pontis drive circuit technical field, particularly a kind of driving interlock circuit of anti-bridge arm direct pass.
Background technology
In the power electronic technology of nowadays extensive use, many circuit topologies be widely used as half-bridge, full-bridge, the framework such as to recommend, once there is the phenomenon that upper and lower bridge arm switching tube is straight-through, this bridgc arm short will be caused, form very large short circuit current, cause switching tube to demolish.And in recent years, due to the development of embedded technology, in increasing application, the PWM drive control signal of brachium pontis switching tube is all sent by DSP/MCU etc.And DSP/MCU may, because of factors such as the instability of working power, cause program run-time error to send out the control signal of mistake by mistake; Or the long distance cabling between DSP to switch tube driving circuit is subject to other signal disturbing of machine intimate; Thus cause upper and lower bridge arm switching tube to lead directly to.
Drive singal in order to avoid mistake causes upper and lower bridge arm Switch Cut-through, just seems extremely important in the lockout circuit of the position access control signal near switch tube driving circuit.
The interference driven has two kinds usually: one is upper brachium pontis or lower brachium pontis switching tube when being in opening state, and the drive control signal of another brachium pontis is disturbed and make this brachium pontis switching tube also conducting, causes upper and lower bridge arm to lead directly to; Another kind is that upper and lower bridge arm interferes with each other or makes upper and lower bridge arm switching tube simultaneously from off state to conducting State Transferring by same interference source interference.Some current interlock protection circuits usually only can available protecting for wherein a part of situation, perfect not enough.
As patent documentation CN102035192A discloses a kind of uninterrupted power supply control signal interlock protection circuit, comprise pwm signal detecting circuit, interlocking signal decision circuitry and the lockout circuit of PWM drive singal, fault-signal disappearance self-repairing circuit; This invention to IGBT upper and lower bridge arm control signal whether interlocking is monitored, because certain factor causes control signal mistake, when occurring that upper and lower bridge arm exists the logic of common conducting, block drive singal immediately, prevent IGBT occur lead directly to up and down.But this invention cannot ensure when circuit produces locking signal, drive singal is not transferred into output, when in the face of the first disturbed condition, namely when a brachium pontis is opened, the driving of another brachium pontis is interfered, now drive the signal of interlocking obviously can not block the driving of upper and lower bridge arm in time, cause upper and lower bridge to lead directly to.
Summary of the invention
The object of the invention is to avoid above-mentioned weak point of the prior art and the driving lockout circuit that a kind of anti-bridge arm direct pass of the phenomenon that can effectively prevent the upper and lower bridge of same brachium pontis from leading directly to is provided.
Object of the present invention is achieved through the following technical solutions:
Provide a kind of driving interlock circuit of anti-bridge arm direct pass, comprise A bridge output circuit and B bridge output circuit, the output of described A bridge output circuit outwards exports A bridge drive singal OUT_A, the output of described B bridge output circuit outwards exports B bridge drive singal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit, the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit, also comprise and interlocking signal control circuit, described interlocking signal control circuit blocks A bridge output circuit until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when B bridge control signal PWM_B is effective, described interlocking signal control circuit blocks B bridge output circuit until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when A bridge control signal PWM_A is effective.
Wherein, be connected with A bridge delay circuit between the control signal input Delay_A of described A bridge output circuit and A bridge control signal PWM_A, between the control signal input Delay_B of described B bridge output circuit and B bridge control signal PWM_B, be connected with B bridge delay circuit.
Wherein, described interlocking signal control circuit comprises the lockout circuit of A bridge, the lockout circuit of B bridge and reset circuit, the output of described A bridge lockout circuit exports locking signal to A bridge output circuit, the output of described B bridge lockout circuit exports locking signal to B bridge output circuit, an input coupling B bridge control signal PWM_B of described A bridge lockout circuit, the reset signal that another input coupling reset circuit exports, an input coupling A bridge control signal PWM_A of described B bridge lockout circuit, the reset signal that another input coupling reset circuit exports, the defeated A bridge control signal PWM_A and B bridge control signal PWM_B that is simultaneously coupled of described reset circuit, described reset circuit output Reset only exports effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid.
Wherein, A bridge delay circuit is connected with between the control signal input Delay_A of described A bridge output circuit and A bridge control signal PWM_A, B bridge delay circuit is connected with between the control signal input Delay_B of described B bridge output circuit and B bridge control signal PWM_B, described reset circuit is time-delay reset circuit, and its delay time is longer than the delay time of A bridge delay circuit and the delay time of B bridge delay circuit.
Wherein, the lockout circuit of described A bridge does not accept reset when B bridge control signal PWM_B is effective, and the lockout circuit of described B bridge does not accept reset when A bridge control signal PWM_A is effective.
Beneficial effect of the present invention: the driving interlock circuit that the invention provides a kind of anti-bridge arm direct pass, between two dead bands (namely A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid), when the control signal of one of them switching tube is effective, interlocking signal control circuit exports the output circuit that locking signal blocks another switching tube, this output circuit is exported invalid, the switching tube that this output circuit controls cannot conducting, therefore between these two dead bands, a switching tube conducting is had all the time at the most, stop the problem that the conducting simultaneously of two switching tubes causes bridge arm direct pass and then damages switching tube.
Accompanying drawing explanation
The invention will be further described to utilize accompanying drawing, but the embodiment in accompanying drawing does not form any limitation of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to the following drawings.
Fig. 1 is the structural representation of the embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention.
Fig. 2 is the structural representation of the interlocking signal control circuit of the embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention.
Embodiment
The invention will be further described with the following Examples.
One of embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention, as shown in Figure 1, comprise: A bridge output circuit 1 and B bridge output circuit 2, the output of described A bridge output circuit 1 outwards exports A bridge drive singal OUT_A, the output of described B bridge output circuit 2 outwards exports B bridge drive singal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit 1, the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit 2, also comprise and interlocking signal control circuit 3, described interlocking signal control circuit 3 comprises A bridge output and B bridge output, the output signal of described A bridge output is connected with the interlocking signal input Protect_A of A bridge output circuit 1, the output signal of described B bridge output is connected with the interlocking signal input Protect_B of B bridge output circuit 2.
Described interlocking signal control circuit 3 exports an effective locking signal until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when B bridge control signal PWM_B is effective to interlocking signal input Protect_A, this locking signal blocks A bridge output circuit 1, now no matter whether A bridge control signal PWM_A is effective, the A bridge drive singal OUT_A that A bridge output circuit 1 exports is invalid, i.e. the switching tube not conducting of A bridge.A bridge output circuit 1 input/output list is as follows:
Described interlocking signal control circuit 3 exports an effective locking signal until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when A bridge control signal PWM_A is effective to interlocking signal input Protect_B, this locking signal blocks B bridge output circuit 2, now no matter whether B bridge control signal PWM_B is effective, the A bridge drive singal OUT_B that A bridge output circuit 1 exports is invalid, i.e. the switching tube not conducting of B bridge.B bridge output circuit 2 input/output list is as follows:
Therefore, between two dead bands (namely A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid), when the control signal of one of them switching tube is effective, interlocking signal control circuit 3 exports the output circuit that locking signal blocks another switching tube, this output circuit is exported invalid, the switching tube that this output circuit controls cannot conducting, therefore between these two dead bands, have a switching tube conducting all the time at the most, stopped the problem that the conducting simultaneously of two switching tubes causes bridge arm direct pass and then damages switching tube.
Wherein, be connected with A bridge delay circuit 4 between the control signal input Delay_A of described A bridge output circuit 1 and A bridge control signal PWM_A, between the control signal input Delay_B of described B bridge output circuit 2 and B bridge control signal PWM_B, be connected with B bridge delay circuit 5.Therefore the control signal input Delay_A of A bridge control signal PWM_A to A bridge output circuit 1 delays the locking signal that exports in interlocking signal control circuit 3 to the interlocking signal input Protect_A of A bridge output circuit 1, the control signal input Delay_B of B bridge control signal PWM_B to B bridge output circuit 2 delays the locking signal that exports in the interlocking signal control circuit 3 interlocking signal input Protect_B to B bridge output circuit 2, which ensure that the preferentially enable of locking signal, prevent control signal when may cause failing to block output circuit in time because the production and transfer time of locking signal is longer to arrive and make switching tube conducting and then produce straight-through accident.Improve the reliability of this circuit.
As described in Figure 2, described interlocking signal control circuit 3 comprises A bridge lockout circuit 32, B bridge lockout circuit 33 and time-delay reset circuit 31, the output of described A bridge lockout circuit 32 exports locking signal to A bridge output circuit 1, the output of described B bridge lockout circuit 33 exports locking signal to B bridge output circuit 2, an input coupling B bridge control signal PWM_B of described A bridge lockout circuit 32, the reset signal that another input coupling time-delay reset circuit 31 exports, an input coupling A bridge control signal PWM_A of described B bridge lockout circuit 33, the reset signal that another input coupling time-delay reset circuit 31 exports, the defeated A bridge control signal PWM_A and B bridge control signal PWM_B that is simultaneously coupled of described time-delay reset circuit 31, described time-delay reset circuit 31 output Reset only exports effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid.
A bridge delay circuit 4 is connected with between the control signal input Delay_A of described A bridge output circuit 1 and A bridge control signal PWM_A, be connected with B bridge delay circuit 5 between the control signal input Delay_B of described B bridge output circuit 2 and B bridge control signal PWM_B, the delay time of described time-delay reset circuit 31 is longer than the delay time of A bridge delay circuit 4 and the delay time of B bridge delay circuit 5.
Described A bridge lockout circuit 32 does not accept reset when B bridge control signal PWM_B is effective, and described B bridge lockout circuit 33 does not accept reset when A bridge control signal PWM_A is effective.
For time-delay reset circuit 31, as A bridge control signal PWM_A and B bridge control signal PWM_B all invalid (i.e. dead band), output Reset exports an effective signal, i.e. a reset signal.
For A bridge lockout circuit 32, when B bridge control signal PWM_B is effective, it exports an effective locking signal to A bridge output circuit 1 until there is reset signal to input, and the input/output list of A bridge lockout circuit 32 is as follows:
For B bridge lockout circuit 33, when A bridge control signal PWM_A is effective, it exports an effective locking signal to B bridge output circuit 2 until there is reset signal to input, and the input/output list of B bridge lockout circuit 33 is as follows:
To sum up, the interlocking signal control circuit 3 be made up of time-delay reset circuit 31, A bridge lockout circuit 32 and B bridge lockout circuit 33 can block A bridge output circuit 1 and B bridge output circuit 2 effectively, and when A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid, (dead band) produces both reset signal releasings blockade simultaneously.
Simultaneously, time-delay reset circuit 31 delay time is greater than the delay time of A bridge delay circuit 4 and the delay time of B bridge delay circuit 5, avoid because the too fast generation of reset signal makes locking signal invalid in advance, cause A bridge output circuit 1 may produce effective driving thus the danger making that switching tube conducting and then generation are led directly to.Further, A bridge lockout circuit 32 and B bridge lockout circuit 33 do not accept reset signal when control signal is effective, avoid reset signal too fast or make mistakes that to be that the blockade simultaneously removing A bridge lockout circuit 32 and B bridge lockout circuit 33 causes straight-through dangerous further.
Finally should be noted that; above embodiment is only in order to illustrate technical scheme of the present invention; but not limiting the scope of the invention; although done to explain to the present invention with reference to preferred embodiment; those of ordinary skill in the art is to be understood that; can modify to technical scheme of the present invention or equivalent replacement, and not depart from essence and the scope of technical solution of the present invention.
Claims (2)
1. the driving interlock circuit of an anti-bridge arm direct pass, comprise A bridge output circuit (1) and B bridge output circuit (2), the output of described A bridge output circuit (1) outwards exports A bridge drive singal OUT_A, the output of described B bridge output circuit (2) outwards exports B bridge drive singal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit (1), the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit (2), it is characterized in that: also comprise interlocking signal control circuit (3), described interlocking signal control circuit (3) blocks A bridge output circuit (1) until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when B bridge control signal PWM_B is effective, described interlocking signal control circuit (3) blocks B bridge output circuit (2) until A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid when A bridge control signal PWM_A is effective, described interlocking signal control circuit (3) comprises reset circuit, described reset circuit is coupled A bridge control signal PWM_A and B bridge control signal PWM_B simultaneously, described reset circuit output Reset only exports effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B is all invalid.
2. the driving interlock circuit of a kind of anti-bridge arm direct pass according to claim 1, it is characterized in that: between the control signal input Delay_A of described A bridge output circuit (1) and A bridge control signal PWM_A, be connected with A bridge delay circuit (4), between the control signal input Delay_B of described B bridge output circuit (2) and B bridge control signal PWM_B, be connected with B bridge delay circuit (5).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210386366.8A CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
| PCT/CN2013/083774 WO2014056393A1 (en) | 2012-10-12 | 2013-09-18 | Drive interlocking circuit preventing direct connection of bridge arms |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210386366.8A CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102868292A CN102868292A (en) | 2013-01-09 |
| CN102868292B true CN102868292B (en) | 2016-02-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210386366.8A Active CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
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| Country | Link |
|---|---|
| CN (1) | CN102868292B (en) |
| WO (1) | WO2014056393A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868292B (en) * | 2012-10-12 | 2016-02-03 | 广东易事特电源股份有限公司 | A kind of driving interlock circuit of anti-bridge arm direct pass |
| CN104113197B (en) * | 2013-04-19 | 2016-09-07 | 广东美的制冷设备有限公司 | A kind of SPM |
| CN105703334B (en) * | 2015-11-27 | 2018-05-22 | 深圳市英威腾光伏科技有限公司 | The protective device and three-level inverter of a kind of three-level inverter |
| CN105620706B (en) * | 2016-02-19 | 2018-10-23 | 武汉理工大学 | Watercraft electric propulsion system with harmonics restraint and regenerative braking function and control method |
| CN105720808A (en) * | 2016-03-16 | 2016-06-29 | 珠海格力电器股份有限公司 | Inverter startup short-circuit protection method and device |
| CN105871185A (en) * | 2016-04-25 | 2016-08-17 | 佛山市新光宏锐电源设备有限公司 | Mode control driven self-locking protection circuit |
| CN113131765A (en) * | 2019-12-31 | 2021-07-16 | 核工业西南物理研究院 | H-bridge rapid linear adjustment driving circuit in probe power supply |
| CN112910228B (en) * | 2021-01-27 | 2022-07-22 | 浙江禾川科技股份有限公司 | Converter and bridge circuit thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200983562Y (en) * | 2006-12-14 | 2007-11-28 | 谢步明 | Converter dead area generation circuit |
| CN202818084U (en) * | 2012-10-12 | 2013-03-20 | 广东易事特电源股份有限公司 | A drive interlocking circuit against direction connection of bridge arms |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2920072B2 (en) * | 1994-06-28 | 1999-07-19 | 株式会社中島電機製作所 | Automatic section switch |
| CN102148494B (en) * | 2010-02-10 | 2014-01-29 | 艾默生网络能源系统北美公司 | Bridge arm conduction protection circuit and rectification circuit |
| CN202111464U (en) * | 2011-06-29 | 2012-01-11 | 深圳市伟创电气有限公司 | Inverter leg interlocking protection circuit |
| CN202282730U (en) * | 2011-11-11 | 2012-06-20 | 山东新风光电子科技发展有限公司 | Upper and lower bridge interlocking circuit in two-level inverter |
| CN102868292B (en) * | 2012-10-12 | 2016-02-03 | 广东易事特电源股份有限公司 | A kind of driving interlock circuit of anti-bridge arm direct pass |
-
2012
- 2012-10-12 CN CN201210386366.8A patent/CN102868292B/en active Active
-
2013
- 2013-09-18 WO PCT/CN2013/083774 patent/WO2014056393A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200983562Y (en) * | 2006-12-14 | 2007-11-28 | 谢步明 | Converter dead area generation circuit |
| CN202818084U (en) * | 2012-10-12 | 2013-03-20 | 广东易事特电源股份有限公司 | A drive interlocking circuit against direction connection of bridge arms |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102868292A (en) | 2013-01-09 |
| WO2014056393A1 (en) | 2014-04-17 |
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