CN102868292A - Driving interlock circuit for preventing bridge arms from direct connection - Google Patents
Driving interlock circuit for preventing bridge arms from direct connection Download PDFInfo
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- CN102868292A CN102868292A CN2012103863668A CN201210386366A CN102868292A CN 102868292 A CN102868292 A CN 102868292A CN 2012103863668 A CN2012103863668 A CN 2012103863668A CN 201210386366 A CN201210386366 A CN 201210386366A CN 102868292 A CN102868292 A CN 102868292A
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- bridge
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/20—Interlocking, locking, or latching mechanisms
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to the technical field of bridge arm driving circuits, in particular to a driving interlock circuit for preventing bridge arms from direct connection. The driving interlock circuit comprises an A bridge output circuit, a B bridge output circuit and an interlocking signal control circuit, the interlocking signal control circuit locks the A bridge output circuit when B bridge control signal PWM-B is effective, and the interlocking signal control circuit locks the B bridge output circuit when A bridge control signal PWM-A is effective, so that control signals of one switch tube between two dead zones are effective, the interlocking signal control circuit outputs locking signals to lock an output circuit of the other switch tube to enable output of the output circuit to be invalid, the switch tube controlled by the output circuit is not communicated, at most one switch tube between the two dead zones is always communicated, and a problem that communication of the two switch tubes is avoided simultaneously to cause direct-connection bridge arms to further damage the switch tubes is solved.
Description
Technical field
The present invention relates to brachium pontis drive circuit technical field, particularly a kind of driving interlock circuit of anti-bridge arm direct pass.
Background technology
In the power electronic technology of nowadays extensive use, many circuit topologies that are widely used such as half-bridge, full-bridge, the framework such as recommend, in case the straight-through phenomenon of upper and lower bridge arm switching tube occurs, will cause this bridgc arm short, form very large short circuit current, cause the switching tube demolition.And in recent years, because the development of embedded technology, in increasing the application, the PWM drive control signal of brachium pontis switching tube all is to be sent by DSP/MCU etc.And DSP/MCU may because of the factor such as unstable of working power, cause program run-time error mistake to send out a wrong control signal; Length between perhaps from DSP to the switch tube driving circuit is subject to other signals of machine intimate apart from cabling and disturbs; Thereby cause that the upper and lower bridge arm switching tube is straight-through.
Driving signal for fear of mistake causes the upper and lower bridge arm Switch Cut-through, just seems extremely important in the lockout circuit near the position access control signal of switch tube driving circuit.
The interference that drives has two kinds usually: a kind of is upper brachium pontis or lower brachium pontis switching tube when being in opening state, and the drive control signal of another brachium pontis is disturbed and so that this also conducting of brachium pontis switching tube causes upper and lower bridge arm straight-through; Another kind be upper and lower bridge arm interfere with each other or be subjected to same interference source to disturb and so that the upper and lower bridge arm switching tube change to conducting state from off state simultaneously.Some present interlock protection circuits only can effectively be protected for a part of situation wherein usually, and are perfect not enough.
Disclose a kind of uninterrupted power supply control signal interlock protection circuit such as patent documentation CN 102035192A, comprised that pwm signal detecting circuit, interlocking signal decision circuitry and PWM drive signal lockout circuit, fault-signal disappearance self-repairing circuit; This invention to IGBT upper and lower bridge arm control signal whether interlocking is monitored, because certain factor causes the control signal mistake, when upper and lower bridge arm occurring and having the logic of common conducting, block immediately and drive signal, it is straight-through up and down to prevent that IGBT from occurring.But this invention can't guarantee when circuit produces locking signal, drive signal and be not transferred into output, in the face of the first disturbed condition the time, when namely a brachium pontis has been opened, the driving of another brachium pontis is interfered, the driving that the signal of driving interlocking this moment obviously can not in time block upper and lower bridge arm, causing up and down, bridge leads directly to.
Summary of the invention
The object of the invention is to avoid above-mentioned weak point of the prior art and provide a kind of and can effectively prevent the up and down driving lockout circuit of the anti-bridge arm direct pass of the straight-through phenomenon of bridge of same brachium pontis.
Purpose of the present invention is achieved through the following technical solutions:
A kind of driving interlock circuit of anti-bridge arm direct pass is provided, comprise A bridge output circuit and B bridge output circuit, the output of described A bridge output circuit is outwards exported the A bridge and is driven signal OUT_A, the output of described B bridge output circuit is outwards exported the B bridge and is driven signal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit, the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit, also comprise and the interlocking signal control circuit, described interlocking signal control circuit blocks A bridge output circuit until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid when B bridge control signal PWM_B is effective, described interlocking signal control circuit blocks B bridge output circuit until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid when A bridge control signal PWM_A is effective.
Wherein, be connected with A bridge delay circuit between the control signal input Delay_A of described A bridge output circuit and the A bridge control signal PWM_A, be connected with B bridge delay circuit between the control signal input Delay_B of described B bridge output circuit and the B bridge control signal PWM_B.
Wherein, described interlocking signal control circuit comprises the lockout circuit of A bridge, the lockout circuit of B bridge and reset circuit, the output of described A bridge lockout circuit is to A bridge output circuit output locking signal, the output of described B bridge lockout circuit is to B bridge output circuit output locking signal, an input coupling B bridge control signal PWM_B of described A bridge lockout circuit, the reset signal of another input coupling reset circuit output, an input coupling A bridge control signal PWM_A of described B bridge lockout circuit, the reset signal of another input coupling reset circuit output, defeated A bridge control signal PWM_A and the B bridge control signal PWM_B of being coupled simultaneously of described reset circuit, described reset circuit output Reset only export effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid.
Wherein, be connected with A bridge delay circuit between the control signal input Delay_A of described A bridge output circuit and the A bridge control signal PWM_A, be connected with B bridge delay circuit between the control signal input Delay_B of described B bridge output circuit and the B bridge control signal PWM_B, described reset circuit is time-delay reset circuit, and its delay time is longer than the delay time of A bridge delay circuit and the delay time of B bridge delay circuit.
Wherein, the lockout circuit of described A bridge is not accepted to reset when B bridge control signal PWM_B is effective, and the lockout circuit of described B bridge is not accepted to reset when A bridge control signal PWM_A is effective.
Beneficial effect of the present invention: the driving interlock circuit that the invention provides a kind of anti-bridge arm direct pass, between two dead bands (being that A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid), when the control signal of one of them switching tube when being effective, interlocking signal control circuit output locking signal blocks the output circuit of another switching tube, make this output circuit output invalid, the switching tube of this output circuit control can't conducting, therefore between these two dead bands, a switching tube conducting is arranged at the most all the time, stopped the problem that two simultaneously conductings of switching tube cause bridge arm direct pass and then damage switching tube.
Description of drawings
The invention will be further described to utilize accompanying drawing, but the embodiment in the accompanying drawing does not consist of any limitation of the invention, for those of ordinary skill in the art, under the prerequisite of not paying creative work, can also obtain according to the following drawings other accompanying drawing.
Fig. 1 is the structural representation of embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention.
Fig. 2 is the structural representation of interlocking signal control circuit of embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention.
Embodiment
The invention will be further described with the following Examples.
One of embodiment of the driving interlock circuit of a kind of anti-bridge arm direct pass of the present invention, as shown in Figure 1, comprise: A bridge output circuit 1 and B bridge output circuit 2, the output of described A bridge output circuit 1 is outwards exported the A bridge and is driven signal OUT_A, the output of described B bridge output circuit 2 is outwards exported the B bridge and is driven signal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit 1, the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit 2, also comprise and interlocking signal control circuit 3, described interlocking signal control circuit 3 comprises A bridge output and B bridge output, the output signal of described A bridge output is connected with the interlocking signal input Protect_A of A bridge output circuit 1, and the output signal of described B bridge output is connected with the interlocking signal input Protect_B of B bridge output circuit 2.
Described interlocking signal control circuit 3 is exported an effective locking signal until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid to interlocking signal input Protect_A when B bridge control signal PWM_B is effective, this locking signal blocks A bridge output circuit 1, this moment, no matter whether A bridge control signal PWM_A was effective, it is all invalid that the A bridge of A bridge output circuit 1 output drives signal OUT_A, i.e. the not conducting of switching tube of A bridge.A bridge output circuit 1 input/output list is as follows:
Described interlocking signal control circuit 3 is exported an effective locking signal until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid to interlocking signal input Protect_B when A bridge control signal PWM_A is effective, this locking signal blocks B bridge output circuit 2, this moment, no matter whether B bridge control signal PWM_B was effective, it is invalid that the A bridge of A bridge output circuit 1 output drives signal OUT_B, i.e. the not conducting of switching tube of B bridge.B bridge output circuit 2 input/output lists are as follows:
Therefore, between two dead bands (being that A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid), when the control signal of one of them switching tube when being effective, interlocking signal control circuit 3 output locking signals block the output circuit of another switching tube, make this output circuit output invalid, the switching tube of this output circuit control can't conducting, therefore between these two dead bands, a switching tube conducting is arranged at the most all the time, stopped the problem that two simultaneously conductings of switching tube cause bridge arm direct pass and then damage switching tube.
Wherein, be connected with A bridge delay circuit 4 between the control signal input Delay_A of described A bridge output circuit 1 and the A bridge control signal PWM_A, be connected with B bridge delay circuit 5 between the control signal input Delay_B of described B bridge output circuit 2 and the B bridge control signal PWM_B.Therefore the control signal input Delay_A of A bridge control signal PWM_A to A bridge output circuit 1 delays the interlocking signal input Protect_A in the locking signal of interlocking signal control circuit 3 outputs to A bridge output circuit 1, the control signal input Delay_B of B bridge control signal PWM_B to B bridge output circuit 2 delays the interlocking signal input Protect_B in the locking signal of interlocking signal control circuit 3 output to B bridge output circuit 2, this has guaranteed preferentially enabling of locking signal, prevented may since the generation of locking signal and transmission time long when causing failing in time to block output circuit control signal arrived and made the switching tube conducting and then produced straight-through accident.Improved the reliability of this circuit.
As described in Figure 2, described interlocking signal control circuit 3 comprises A bridge lockout circuit 32, the lockout circuit 33 of B bridge and time-delay reset circuit 31, the output of described A bridge lockout circuit 32 is to A bridge output circuit 1 output locking signal, the output of described B bridge lockout circuit 33 is to B bridge output circuit 2 output locking signals, an input coupling B bridge control signal PWM_B of described A bridge lockout circuit 32, the reset signal of another input coupling time-delay reset circuit 31 outputs, an input coupling A bridge control signal PWM_A of described B bridge lockout circuit 33, the reset signal of another input coupling time-delay reset circuit 31 outputs, described time-delay reset circuit 31 defeated be coupled simultaneously A bridge control signal PWM_A and B bridge control signal PWM_B, described time-delay reset circuit 31 output Reset only export effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid.
Be connected with A bridge delay circuit 4 between the control signal input Delay_A of described A bridge output circuit 1 and the A bridge control signal PWM_A, be connected with B bridge delay circuit 5 between the control signal input Delay_B of described B bridge output circuit 2 and the B bridge control signal PWM_B, the delay time of described time-delay reset circuit 31 is longer than the delay time of A bridge delay circuit 4 and the delay time of B bridge delay circuit 5.
Described A bridge lockout circuit 32 is not accepted to reset when B bridge control signal PWM_B is effective, and described B bridge lockout circuit 33 is not accepted to reset when A bridge control signal PWM_A is effective.
For time-delay reset circuit 31, when an equal output Reset output effective signal, i.e. reset signals when invalid (being the dead band) of A bridge control signal PWM_A and B bridge control signal PWM_B.
For A bridge lockout circuit 32, it exports an effective locking signal to A bridge output circuit 1 until the reset signal input is arranged when B bridge control signal PWM_B is effective, and the input/output list of A bridge lockout circuit 32 is as follows:
For B bridge lockout circuit 33, it exports an effective locking signal to B bridge output circuit 2 until the reset signal input is arranged when A bridge control signal PWM_A is effective, and the input/output list of B bridge lockout circuit 33 is as follows:
To sum up, the interlocking signal control circuit 3 that is made of time-delay reset circuit 31, A bridge lockout circuit 32 and B bridge lockout circuit 33 can block A bridge output circuit 1 and B bridge output circuit 2 effectively, and simultaneously (dead band) produces reset signal and remove the two blockade when A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid.
Simultaneously, time-delay reset circuit 31 delay times are greater than the delay time of A bridge delay circuit 4 and the delay time of B bridge delay circuit 5, avoid because the too fast generation of reset signal makes locking signal invalid in advance, make the switching tube conducting and then produce straight-through danger thereby cause A bridge output circuit 1 may produce effective driving.Further, reset signal is not accepted in A bridge lockout circuit 32 and B bridge lockout circuit 33 when control signal is effective, further avoids reset signal too fast or to make mistakes be that the blockade of removing simultaneously A bridge lockout circuit 32 and B bridge lockout circuit 33 causes straight-through dangerous.
Should be noted that at last; above embodiment is only in order to illustrate technical scheme of the present invention; but not limiting the scope of the invention; although with reference to preferred embodiment the present invention has been done to explain; those of ordinary skill in the art is to be understood that; can make amendment or be equal to replacement technical scheme of the present invention, and not break away from essence and the scope of technical solution of the present invention.
Claims (5)
1. the driving interlock circuit of an anti-bridge arm direct pass, comprise A bridge output circuit (1) and B bridge output circuit (2), the output of described A bridge output circuit (1) is outwards exported the A bridge and is driven signal OUT_A, the output of described B bridge output circuit (2) is outwards exported the B bridge and is driven signal OUT_B, the control signal input Delay_A coupling A bridge control signal PWM_A of described A bridge output circuit (1), the control signal input Delay_B coupling B bridge control signal PWM_B of described B bridge output circuit (2), it is characterized in that: also comprise interlocking signal control circuit (3), described interlocking signal control circuit (3) blocks A bridge output circuit (1) until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid when B bridge control signal PWM_B is effective, described interlocking signal control circuit (3) blocks B bridge output circuit (2) until A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid when A bridge control signal PWM_A is effective.
2. the driving interlock circuit of a kind of anti-bridge arm direct pass according to claim 1, it is characterized in that: be connected with A bridge delay circuit (4) between the control signal input Delay_A of described A bridge output circuit (1) and the A bridge control signal PWM_A, be connected with B bridge delay circuit (5) between the control signal input Delay_B of described B bridge output circuit (2) and the B bridge control signal PWM_B.
3. the driving interlock circuit of a kind of anti-bridge arm direct pass according to claim 1, it is characterized in that: described interlocking signal control circuit (3) comprises A bridge lockout circuit (32), B bridge lockout circuit (33) and reset circuit, the output of described A bridge lockout circuit (32) is to A bridge output circuit (1) output locking signal, the output of described B bridge lockout circuit (33) is to B bridge output circuit (2) output locking signal, an input coupling B bridge control signal PWM_B of described A bridge lockout circuit (32), the reset signal of another input coupling reset circuit output, an input coupling A bridge control signal PWM_A of described B bridge lockout circuit (33), the reset signal of another input coupling reset circuit output, defeated A bridge control signal PWM_A and the B bridge control signal PWM_B of being coupled simultaneously of described reset circuit, described reset circuit output Reset only export effective reset signal in order to lift a blockade when A bridge control signal PWM_A and B bridge control signal PWM_B are all invalid.
4. the driving interlock circuit of a kind of anti-bridge arm direct pass according to claim 3, it is characterized in that: be connected with A bridge delay circuit (4) between the control signal input Delay_A of described A bridge output circuit (1) and the A bridge control signal PWM_A, be connected with B bridge delay circuit (5) between the control signal input Delay_B of described B bridge output circuit (2) and the B bridge control signal PWM_B, described reset circuit is time-delay reset circuit (31), and its delay time is longer than the delay time of A bridge delay circuit (4) and the delay time of B bridge delay circuit (5).
5. the driving interlock circuit of a kind of anti-bridge arm direct pass according to claim 3, it is characterized in that: described A bridge lockout circuit (32) is not accepted to reset when B bridge control signal PWM_B is effective, and described B bridge lockout circuit (33) is not accepted to reset when A bridge control signal PWM_A is effective.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210386366.8A CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
| PCT/CN2013/083774 WO2014056393A1 (en) | 2012-10-12 | 2013-09-18 | Drive interlocking circuit preventing direct connection of bridge arms |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210386366.8A CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102868292A true CN102868292A (en) | 2013-01-09 |
| CN102868292B CN102868292B (en) | 2016-02-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210386366.8A Active CN102868292B (en) | 2012-10-12 | 2012-10-12 | A kind of driving interlock circuit of anti-bridge arm direct pass |
Country Status (2)
| Country | Link |
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| CN (1) | CN102868292B (en) |
| WO (1) | WO2014056393A1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014056393A1 (en) * | 2012-10-12 | 2014-04-17 | 广东易事特电源股份有限公司 | Drive interlocking circuit preventing direct connection of bridge arms |
| CN104113197A (en) * | 2013-04-19 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module |
| CN105620706A (en) * | 2016-02-19 | 2016-06-01 | 武汉理工大学 | Ship electric propulsion system with harmonic suppressing and regenerative braking functions and control method |
| CN105703334A (en) * | 2015-11-27 | 2016-06-22 | 深圳市英威腾电气股份有限公司 | Three-level inverter protection device and three-level inverter |
| CN105720808A (en) * | 2016-03-16 | 2016-06-29 | 珠海格力电器股份有限公司 | Inverter starting short-circuit protection method and device |
| CN112910228A (en) * | 2021-01-27 | 2021-06-04 | 浙江禾川科技股份有限公司 | Converter and bridge circuit thereof |
| CN113131765A (en) * | 2019-12-31 | 2021-07-16 | 核工业西南物理研究院 | H-bridge rapid linear adjustment driving circuit in probe power supply |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105871185A (en) * | 2016-04-25 | 2016-08-17 | 佛山市新光宏锐电源设备有限公司 | Mode control driven self-locking protection circuit |
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| CN202818084U (en) * | 2012-10-12 | 2013-03-20 | 广东易事特电源股份有限公司 | A drive interlocking circuit against direction connection of bridge arms |
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| JP2920072B2 (en) * | 1994-06-28 | 1999-07-19 | 株式会社中島電機製作所 | Automatic section switch |
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| CN202111464U (en) * | 2011-06-29 | 2012-01-11 | 深圳市伟创电气有限公司 | Inverter leg interlocking protection circuit |
| CN202282730U (en) * | 2011-11-11 | 2012-06-20 | 山东新风光电子科技发展有限公司 | Upper and lower bridge interlocking circuit in two-level inverter |
| CN102868292B (en) * | 2012-10-12 | 2016-02-03 | 广东易事特电源股份有限公司 | A kind of driving interlock circuit of anti-bridge arm direct pass |
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2012
- 2012-10-12 CN CN201210386366.8A patent/CN102868292B/en active Active
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2013
- 2013-09-18 WO PCT/CN2013/083774 patent/WO2014056393A1/en active Application Filing
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| CN200983562Y (en) * | 2006-12-14 | 2007-11-28 | 谢步明 | Converter dead area generation circuit |
| CN202818084U (en) * | 2012-10-12 | 2013-03-20 | 广东易事特电源股份有限公司 | A drive interlocking circuit against direction connection of bridge arms |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014056393A1 (en) * | 2012-10-12 | 2014-04-17 | 广东易事特电源股份有限公司 | Drive interlocking circuit preventing direct connection of bridge arms |
| CN104113197A (en) * | 2013-04-19 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module |
| CN104113197B (en) * | 2013-04-19 | 2016-09-07 | 广东美的制冷设备有限公司 | A kind of SPM |
| CN105703334A (en) * | 2015-11-27 | 2016-06-22 | 深圳市英威腾电气股份有限公司 | Three-level inverter protection device and three-level inverter |
| CN105703334B (en) * | 2015-11-27 | 2018-05-22 | 深圳市英威腾光伏科技有限公司 | The protective device and three-level inverter of a kind of three-level inverter |
| CN105620706A (en) * | 2016-02-19 | 2016-06-01 | 武汉理工大学 | Ship electric propulsion system with harmonic suppressing and regenerative braking functions and control method |
| CN105620706B (en) * | 2016-02-19 | 2018-10-23 | 武汉理工大学 | Watercraft electric propulsion system with harmonics restraint and regenerative braking function and control method |
| CN105720808A (en) * | 2016-03-16 | 2016-06-29 | 珠海格力电器股份有限公司 | Inverter starting short-circuit protection method and device |
| WO2017157108A1 (en) * | 2016-03-16 | 2017-09-21 | 珠海格力电器股份有限公司 | Short-circuit protection method and device during inverter startup |
| CN113131765A (en) * | 2019-12-31 | 2021-07-16 | 核工业西南物理研究院 | H-bridge rapid linear adjustment driving circuit in probe power supply |
| CN112910228A (en) * | 2021-01-27 | 2021-06-04 | 浙江禾川科技股份有限公司 | Converter and bridge circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2014056393A1 (en) | 2014-04-17 |
| CN102868292B (en) | 2016-02-03 |
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