CN102867758B - Bumping manufacturing process and structure thereof - Google Patents
Bumping manufacturing process and structure thereof Download PDFInfo
- Publication number
- CN102867758B CN102867758B CN201110194648.3A CN201110194648A CN102867758B CN 102867758 B CN102867758 B CN 102867758B CN 201110194648 A CN201110194648 A CN 201110194648A CN 102867758 B CN102867758 B CN 102867758B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- periphery wall
- layer
- copper
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention is about a kind of bumping manufacturing process and structure thereof.Wherein manufacturing process comprises: provide substrate; Form copper-containing metal layer in this substrate, copper-containing metal layer has the firstth district and the secondth district; Form photoresist layer in copper-containing metal layer; Patterning photoresist layer; Form copper bump and each copper bump has the first end face; Form conductive layer in the first end face, this conductive layer has the second end face; Remove photoresist layer; Remove the secondth district, and make the firstth district form a Underbump metallization floor, each Underbump metallization layer has the first periphery wall, and each copper bump has the second periphery wall, and conductive layer has the 3rd periphery wall; Form anti-ionized layers, it is cover this second end face that anti-ionized layers has the first overlay segment of covered substrate, the second overlay segment covering the first periphery wall, the second periphery wall and the 3rd periphery wall, the 3rd overlay segment and the section of removing; Form dielectric layer in anti-ionized layers; This dielectric layer of patterning; And remove this section of removing to appear this second end face.
Description
Technical field
The present invention relates to a kind of bumping manufacturing process, particularly relate to a kind of bumping manufacturing process preventing copper ion free.
Background technology
As Figure 1A to 1H, existing known bumping manufacturing process at least comprises the following step: first, refer to Figure 1A, one substrate 10 is provided, this substrate 10 be there is a surface 11, protective layer 13 that multiple weld pads 12 and being arranged at this surface 11 are formed at this surface 11, this protective layer 13 appears above-mentioned weld pad 12, then, refer to Figure 1B, form a copper-containing metal layer 20 in above-mentioned weld pad 12 and this protective layer 13, afterwards, refer to Fig. 1 C, form a photoresist layer 30 in this copper-containing metal layer 20, then, refer to Fig. 1 D, this photoresist layer 30 of patterning is to form multiple opening 31, afterwards, refer to Fig. 1 E, form multiple copper bump 40 in above-mentioned opening 31, respectively this copper bump 40 has one first periphery wall 41, then, refer to Fig. 1 F, form a conductive layer 50 in above-mentioned copper bump 40, afterwards, refer to Fig. 1 G, remove this photoresist layer 30, finally, refer to Fig. 1 H, this copper-containing metal layer 20 utilizing engraving method to remove not covered by above-mentioned copper bump 40 is to form a Underbump metallization layer 21, respectively this Underbump metallization layer 21 has one second periphery wall 21a, so when carrying out removing the step of this copper-containing metal layer 20 do not covered by above-mentioned copper bump 40, because the material of above-mentioned copper bump 40 includes copper, therefore above-mentioned copper bump 40 can be caused above-mentioned first periphery wall 41 of above-mentioned copper bump 40 to produce the situation of depression simultaneously together with this copper-containing metal layer 20 by etching, and the degree that the above-mentioned second periphery wall 21a of above-mentioned Underbump metallization layer 21 caves in more is greater than above-mentioned first periphery wall 41 of above-mentioned copper bump 40, in addition, due to above-mentioned first periphery wall 41 and above-mentioned second periphery wall 21a cave in and exposed, therefore the phenomenon easily causing copper ion to dissociate and cause the situation of short circuit to occur.
Because the defect that above-mentioned existing bumping manufacturing process exists, the present inventor is based on being engaged in the practical experience and professional knowledge that this type of product design manufacture enriches for many years, and coordinate the utilization of scientific principle, actively in addition research and innovation, to founding a kind of new bumping manufacturing process and structure thereof, general existing bumping manufacturing process can be improved, make it have more practicality.Through constantly research, design, and through repeatedly studying sample and after improving, finally creating the present invention had practical value.
Summary of the invention
Main purpose of the present invention is, overcome the shortcoming that existing bumping manufacturing process exists, and provide a kind of bumping manufacturing process and structure thereof, technical problem to be solved is, avoids copper ion to dissociate causing the situation of short circuit.
For achieving the above object and solving the problems of the technologies described above, a kind of bumping manufacturing process provided by the invention, it at least comprises provides substrate, and this substrate has surface and multiple weld pad being arranged at this surface, and respectively this weld pad has to appear face and ring wall, form copper-containing metal layer and cover above-mentioned weld pad in this substrate, this copper-containing metal layer has multiple firstth district and multiple secondth district, form photoresist layer in this copper-containing metal layer, this photoresist layer of patterning to form multiple opening, corresponding above-mentioned firstth district of above-mentioned opening, form multiple copper bump in above-mentioned opening, respectively this copper bump cover this copper-containing metal layer respectively this firstth district and respectively this copper bump there is the first end face, form conductive layer in above-mentioned first end face of above-mentioned copper bump, this conductive layer has the second end face and this conductive layer includes nickel dam and knitting layer, and this nickel dam is between this copper bump and this knitting layer, remove this photoresist layer, remove above-mentioned secondth district of this copper-containing metal layer, and make respectively this firstth district of this copper-containing metal layer form Underbump metallization floor, wherein respectively this Underbump metallization layer has the first periphery wall, respectively this copper bump has the second periphery wall, this conductive layer has the 3rd periphery wall, being have the first spacing between 3rd periphery wall and this second periphery wall, is have the second spacing between the 3rd periphery wall and this first periphery wall, form anti-ionized layers in this second end face of this conductive layer, above-mentioned first periphery wall of above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump, 3rd periphery wall of this conductive layer and this substrate, this anti-ionized layers has the first overlay segment, second overlay segment, 3rd overlay segment and the section of removing, this first overlay segment covers this substrate, this second overlay segment is above-mentioned first periphery wall covering above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump and the 3rd periphery wall of this conductive layer, 3rd overlay segment and this section of removing are this second end faces covering this conductive layer, this anti-ionized layers be selected from oxide or nitride one of them, form dielectric layer in this anti-ionized layers, this dielectric layer of patterning multiplely appears opening to be formed, and the above-mentioned opening that appears is this section of removing appearing this anti-ionized layers, and this section of removing removing this anti-ionized layers is to appear this second end face of this conductive layer.
Preferably, above-mentioned bumping manufacturing process, wherein separately includes the step of the 3rd overlay segment removing this anti-ionized layers.
Preferably, above-mentioned bumping manufacturing process, wherein this substrate separately has protective layer, and this protective layer is formed at this surface and covers above-mentioned weld pad.
Preferably, above-mentioned bumping manufacturing process, wherein this first overlay segment is this protective layer covering this substrate.
Preferably, above-mentioned bumping manufacturing process, wherein this first overlay segment covers this ring wall of this weld pad and this surface of this substrate.
Preferably, above-mentioned bumping manufacturing process, wherein this second spacing is not less than this first spacing.
Preferably, above-mentioned bumping manufacturing process, wherein this nitride be can be silicon nitride, silicon oxynitride or its mixture one of them, this oxide be can be silicon dioxide, silicon oxynitride or its mixture one of them.
Preferably, above-mentioned bumping manufacturing process, wherein the material of this dielectric layer is selected from polyimides (Pl, Polyimides) or benzocyclobutene (BCB, Benzocyclobutane).
The present invention also provides a kind of projection cube structure, at least comprises: substrate, and it has surface and multiple weld pad being arranged at this surface, and respectively this weld pad has and appears face and ring wall; Multiple Underbump metallization layer, it is formed on above-mentioned weld pad, and respectively this Underbump metallization layer has the first periphery wall; Multiple copper bump, it is formed on above-mentioned Underbump metallization layer, and respectively this copper bump has the first end face and the second periphery wall; Conductive layer, it is above-mentioned first end face being formed at above-mentioned copper bump, this conductive layer has the second end face and the 3rd periphery wall, and this conductive layer includes nickel dam and knitting layer, this nickel dam is between this copper bump and this knitting layer, being wherein have the first spacing between the 3rd periphery wall and this second periphery wall, is have the second spacing between the 3rd periphery wall and this first periphery wall; Anti-ionized layers, it is formed at above-mentioned first periphery wall of above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump, the 3rd periphery wall of this conductive layer and this substrate, this anti-ionized layers has the first overlay segment and the second overlay segment, this first overlay segment covers this substrate, this second overlay segment covers the 3rd periphery wall of above-mentioned first periphery wall of above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump and this conductive layer, this anti-ionized layers be selected from oxide or nitride one of them; And dielectric layer, it is formed at this anti-ionized layers, and this dielectric layer has multiple opening that appears to appear this second end face of this conductive layer.
Preferably, above-mentioned projection cube structure, wherein this anti-ionized layers separately has the 3rd overlay segment, and the 3rd overlay segment is this second end face covering this conductive layer.
Preferably, above-mentioned projection cube structure, wherein the 3rd periphery wall has the 3rd outer perimeter, this second periphery wall has the second outer perimeter, this first periphery wall has the first outer perimeter, and the 3rd outer perimeter is greater than this second outer perimeter, and this second outer perimeter is not less than this first outer perimeter.
Preferably, above-mentioned projection cube structure, wherein this substrate separately has protective layer, and this protective layer is formed at this surface and covers above-mentioned weld pad.
Preferably, above-mentioned projection cube structure, wherein this first overlay segment covers this ring wall of this weld pad and this surface of this substrate.
Preferably, above-mentioned projection cube structure, wherein the first overlay segment is this protective layer covering this substrate.
Beneficial effect of the present invention is: because this anti-ionized layers is this second end face covering this conductive layer, above-mentioned first periphery wall of above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump, 3rd periphery wall of this conductive layer and this substrate, it is the situation above-mentioned second periphery wall of above-mentioned first periphery wall of above-mentioned Underbump metallization layer and above-mentioned copper bump can avoided exposed and cause copper ion to dissociate to cause short circuit, in addition, because this dielectric layer covers again this ionized layers, therefore the thickness of this ionized layers does not need too thick and this dielectric layer to be structural strength after can increasing encapsulation and reduces the consumption of filling glue, more effectively can block aqueous vapor.
In sum, the present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to 1H: the schematic cross-section of existing known bumping manufacturing process.
Fig. 2 A to 2L: according to a preferred embodiment of the present invention, a kind of schematic cross-section of bumping manufacturing process.
Fig. 3: according to another preferred embodiment of the present invention, the schematic cross-section of another kind of projection cube structure.
Fig. 4: according to another preferred embodiment of the present invention, the schematic cross-section of another projection cube structure.
[main element symbol description]
10 substrate 11 surfaces
12 weld pad 13 protective layers
20 copper-containing metal layer 21 Underbump metallization layers
21a second periphery wall
30 photoresist layer 31 openings
40 copper bump 41 first periphery walls
50 conductive layers
100 projection cube structures
110 substrate 111 surfaces
112 weld pad 112a appear face
112b ring wall 113 protective layer
120 copper-containing metal layer 121 first districts
122 second district 123 Underbump metallization floor
123a first periphery wall
130 photoresist layer 131 openings
140 copper bump 141 first end faces
142 second periphery walls
150 conductive layer 151 second end faces
152 nickel dam 153 knitting layers
154 the 3rd periphery walls
160 anti-ionized layers 161 first overlay segments
162 second overlay segment 163 the 3rd overlay segments
164 sections of removing
170 dielectric layers 171 appear opening
D1 first space D 2 second spacing
L1 first outer perimeter L2 second outer perimeter
L3 the 3rd outer perimeter
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, the bumping manufacturing process propose foundation the present invention and the embodiment of structure, structure, step, feature and effect thereof, be described in detail as follows.
Refer to Fig. 2 A to Fig. 2 L, it is a preferred embodiment of the present invention, a kind of bumping manufacturing process, it at least comprises the following step: first, refer to Fig. 2 A, there is provided a substrate 110, this substrate 110 has surface 111 and the multiple weld pad 112 being arranged at this surface 111, and respectively this weld pad 112 has one to appear a face 112a and ring wall 112b; Then, refer to Fig. 2 B, forming a copper-containing metal layer 120 in this substrate 110 covers above-mentioned weld pad 112, in the present embodiment, this copper-containing metal layer 120 is this surface 111 and the above-mentioned weld pad 112 that cover this substrate 110, and this copper-containing metal layer 120 has multiple first district 121 and multiple second district 122; Then, refer to Fig. 2 C, form a photoresist layer 130 in this copper-containing metal layer 120; Then, refer to this photoresist layer 130 of Fig. 2 D patterning to form multiple opening 131, above-mentioned opening 131 is corresponding above-mentioned first districts 121; Afterwards, refer to Fig. 2 E, form multiple copper bump 140 in above-mentioned opening 131, respectively this copper bump 140 be cover this copper-containing metal layer 120 respectively this firstth district 121 and respectively this copper bump 140 be that there is one first end face 141; Then, refer to Fig. 2 F, form a conductive layer 150 in above-mentioned first end face 141 of above-mentioned copper bump 140, this conductive layer 150 has one second end face 151 and this conductive layer 150 includes nickel dam 152 and a knitting layer 153, and this nickel dam 152 is between this copper bump 140 and this knitting layer 153; Afterwards, refer to Fig. 2 G, remove this photoresist layer 130.
Then, refer to Fig. 2 H, remove above-mentioned second district 122 of this copper-containing metal layer 120, and make respectively this firstth district 121 of this copper-containing metal layer 120 form a Underbump metallization floor 123, wherein respectively this Underbump metallization layer 123 has one first periphery wall 123a, respectively this copper bump 140 has one second periphery wall 142, this conductive layer 150 has one the 3rd periphery wall 154, that there is one first space D 1 between 3rd periphery wall 154 and this second periphery wall 142, that there is one second space D 2 between 3rd periphery wall 154 and this first periphery wall 123a, in the present embodiment, this second space D 2 is not less than this first space D 1, this first periphery wall 123a has one first outer perimeter L1, this second periphery wall 142 has one second outer perimeter L2, 3rd periphery wall 154 has one the 3rd outer perimeter L3, 3rd outer perimeter L3 is greater than this second outer perimeter L2, this second outer perimeter L2 is not less than this first outer perimeter L1, afterwards, refer to Fig. 2 I, form an anti-ionized layers 160 in this second end face 151 of this conductive layer 150, the above-mentioned first periphery wall 123a of above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140, 3rd periphery wall 154 of this conductive layer 150 and this substrate 110, in the present embodiment, this anti-ionized layers 160 is this surface 111 and the above-mentioned weld pad 112 that cover this substrate 110, this anti-ionized layers 160 has one first overlay segment 161, one second overlay segment 162, one the 3rd overlay segment 163 and a section of removing 164, this first overlay segment 161 covers this substrate 110, this second overlay segment 162 is the above-mentioned first periphery wall 123a covering above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140 and the 3rd periphery wall 154 of this conductive layer 150, 3rd overlay segment 163 and this section of removing 164 are these second end faces 151 covering this conductive layer 150, in the present embodiment, this first overlay segment 161 covers this ring wall 112b of this weld pad 112 and this surface 111 of this substrate 110, this anti-ionized layers 160 be selected from oxide or nitride one of them, this nitride can be silicon nitride, silicon oxynitride or its mixture one of them, this oxide can be silicon dioxide, silicon oxynitride or its mixture one of them.
Then, refer to Fig. 2 J, form a dielectric layer 170 in this anti-ionized layers 160, the material of this dielectric layer 170 can be selected from polyimides (Pl, Polyimides) or benzocyclobutene (BCB, Benzocyclobutane), afterwards, refer to Fig. 2 K, this dielectric layer 170 of patterning multiplely appears opening 171 to be formed, and the above-mentioned opening 171 that appears is these sections of removing 164 appearing this anti-ionized layers 160, finally, refer to Fig. 2 L, remove this section of removing 164 of this anti-ionized layers 160 to appear this second end face 151 of this conductive layer 150, to form a kind of projection cube structure 100, this projection cube structure 100 at least comprises a substrate 110, multiple Underbump metallization layer 123, multiple copper bump 140, one conductive layer 150, one anti-ionized layers 160 and a dielectric layer 170, this substrate 110 has surface 111 and the multiple weld pad 112 being arranged at this surface 111, respectively this weld pad 112 has one to appear a face 112a and ring wall 112b, above-mentioned Underbump metallization layer 123 is formed on above-mentioned weld pad 112, respectively this Underbump metallization layer 123 has one first periphery wall 123a, above-mentioned copper bump 140 is formed on above-mentioned Underbump metallization layer 123, respectively this copper bump 140 has one first end face 141 and one second periphery wall 142, this conductive layer 150 is above-mentioned first end faces 141 being formed at above-mentioned copper bump 140, this conductive layer 150 has one second end face 151 and one the 3rd periphery wall 154, and this conductive layer 150 includes nickel dam 152 and a knitting layer 153, this nickel dam 152 is between this copper bump 140 and this knitting layer 153, in the present embodiment, 3rd periphery wall 154 has one the 3rd outer perimeter L3, this second periphery wall 142 has one second outer perimeter L2, this first periphery wall 123a has one first outer perimeter L1, 3rd outer perimeter L3 is greater than this second outer perimeter L2, this second outer perimeter L2 is not less than this first outer perimeter L1, wherein that there is one first space D 1 between the 3rd periphery wall 154 and this second periphery wall 142, that there is one second space D 2 between 3rd periphery wall 154 and this first periphery wall 123a, this anti-ionized layers 160 is the above-mentioned first periphery wall 123a being formed at above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140, 3rd periphery wall 154 of this conductive layer 150 and this substrate 110, this anti-ionized layers 160 has one first overlay segment 161, one second overlay segment 162 and one the 3rd overlay segment 163, this first overlay segment 161 covers this substrate 110, this second overlay segment 162 is the above-mentioned first periphery wall 123a covering above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140 and the 3rd periphery wall 154 of this conductive layer 150, 3rd overlay segment 163 is these second end faces 151 covering this conductive layer 150, this dielectric layer 170 is formed at this anti-ionized layers 160, and this dielectric layer 170 has multiple opening 171 that appears to appear this second end face 151 of this conductive layer 150.Because this projection cube structure 100 has this anti-ionized layers 160, above-mentioned second periphery wall 142 of the above-mentioned first periphery wall 123a of above-mentioned Underbump metallization layer 123 and above-mentioned copper bump 140 can be avoided exposed and cause copper ion to dissociate to cause the situation of short circuit, in addition, because this projection cube structure 100 has more this dielectric layer 170, therefore the thickness of this ionized layers does not need too thick and this dielectric layer 170 to be structural strengths after can increasing encapsulation and reduces the consumption of filling glue, more effectively can block aqueous vapor.
Or, refer to Fig. 3, it is the second embodiment of the present invention, and the difference of itself and the first embodiment is that the 3rd overlay segment 163 also simultaneously removing this anti-ionized layers 160 in the step of this section of removing 164 removing this anti-ionized layers 160 is to appear this second end face 151 more.
Or, refer to Fig. 4, it is the third embodiment of the present invention, the difference of itself and the first embodiment is that this substrate 110 separately has a protective layer 113, this protective layer 113 is formed at this surface 111 and covers above-mentioned weld pad 112, therefore this anti-ionized layers 160 is these second end faces 151 covering this conductive layer 150, the above-mentioned first periphery wall 123a of above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140, 3rd periphery wall 154 of this conductive layer 150 and this protective layer 113, in the present embodiment, this first overlay segment 161 of this anti-ionized layers 160 is these protective layers 113 covering this substrate 110, this second overlay segment 162 is the above-mentioned first periphery wall 123a covering above-mentioned Underbump metallization layer 123, above-mentioned second periphery wall 142 of above-mentioned copper bump 140 and the 3rd periphery wall 154 of this conductive layer 150, 3rd overlay segment 163 is these second end faces 151 covering this conductive layer 150.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art are not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (12)
1. a bumping manufacturing process, is characterized in that at least comprising:
There is provided substrate, this substrate has surface and multiple weld pad being arranged at this surface, and respectively this weld pad has and appears face and ring wall;
Form copper-containing metal layer and cover above-mentioned weld pad in this substrate, this copper-containing metal layer has multiple firstth district and multiple secondth district;
Form photoresist layer in this copper-containing metal layer;
This photoresist layer of patterning to form multiple opening, corresponding above-mentioned firstth district of above-mentioned opening;
Form multiple copper bump in above-mentioned opening, respectively this copper bump cover this copper-containing metal layer respectively this firstth district and respectively this copper bump there is the first end face;
Form conductive layer in above-mentioned first end face of above-mentioned copper bump, this conductive layer has the second end face and this conductive layer includes nickel dam and knitting layer, and this nickel dam is between this copper bump and this knitting layer;
Remove this photoresist layer;
Remove above-mentioned secondth district of this copper-containing metal layer, and make respectively this firstth district of this copper-containing metal layer be formed as Underbump metallization floor, wherein respectively this Underbump metallization layer has the first periphery wall, respectively this copper bump has the second periphery wall, this conductive layer has the 3rd periphery wall, being have the first spacing between 3rd periphery wall and this second periphery wall, is have the second spacing between the 3rd periphery wall and this first periphery wall;
Form anti-ionized layers in this second end face of this conductive layer, above-mentioned first periphery wall of above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump, 3rd periphery wall of this conductive layer and this substrate, this anti-ionized layers has the first overlay segment, second overlay segment, 3rd overlay segment and the section of removing, this first overlay segment covers this substrate, this second overlay segment is above-mentioned first periphery wall covering above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump and the 3rd periphery wall of this conductive layer, 3rd overlay segment and this section of removing are this second end faces covering this conductive layer, this anti-ionized layers be selected from oxide or nitride one of them,
Form dielectric layer in this anti-ionized layers;
This dielectric layer of patterning multiplely appears opening to be formed, and the above-mentioned opening that appears is this section of removing appearing this anti-ionized layers; And
Remove this section of removing of this anti-ionized layers to appear this second end face of this conductive layer.
2. bumping manufacturing process as claimed in claim 1, it is characterized in that wherein this substrate separately has protective layer, this protective layer is formed at this surface and covers above-mentioned weld pad.
3. bumping manufacturing process as claimed in claim 2, is characterized in that wherein this first overlay segment is this protective layer covering this substrate.
4. bumping manufacturing process as claimed in claim 1, is characterized in that wherein this first overlay segment covers this ring wall of this weld pad and this surface of this substrate.
5. bumping manufacturing process as claimed in claim 1, is characterized in that wherein this second spacing is not less than this first spacing.
6. bumping manufacturing process as claimed in claim 1, it is characterized in that wherein this nitride be can be silicon nitride, silicon oxynitride or its mixture one of them, this oxide be can be silicon dioxide, silicon oxynitride or its mixture one of them.
7. bumping manufacturing process as claimed in claim 1, is characterized in that the material of wherein this dielectric layer is selected from polyimides PI or benzocyclobutene BCB.
8. a projection cube structure, is characterized in that at least comprising:
Substrate, it has surface and multiple weld pad being arranged at this surface, and respectively this weld pad has and appears face and ring wall;
Multiple Underbump metallization layer, it is formed on above-mentioned weld pad, and respectively this Underbump metallization layer has the first periphery wall;
Multiple copper bump, it is formed on above-mentioned Underbump metallization layer, and respectively this copper bump has the first end face and the second periphery wall;
Conductive layer, it is above-mentioned first end face being formed at above-mentioned copper bump, this conductive layer has the second end face and the 3rd periphery wall, and this conductive layer includes nickel dam and knitting layer, this nickel dam is between this copper bump and this knitting layer, being wherein have the first spacing between the 3rd periphery wall and this second periphery wall, is have the second spacing between the 3rd periphery wall and this first periphery wall;
Anti-ionized layers, it is above-mentioned first periphery wall being formed at above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump, 3rd periphery wall of this conductive layer and this substrate, this anti-ionized layers has the first overlay segment, second overlay segment and the 3rd overlay segment, this first overlay segment covers this substrate, this second overlay segment is above-mentioned first periphery wall covering above-mentioned Underbump metallization layer, above-mentioned second periphery wall of above-mentioned copper bump and the 3rd periphery wall of this conductive layer, 3rd overlay segment is this second end face covering this conductive layer, this anti-ionized layers be selected from oxide or nitride one of them, and
Dielectric layer, it is formed at this anti-ionized layers, and this dielectric layer has multiple opening that appears to appear this second end face of this conductive layer.
9. projection cube structure as claimed in claim 8, it is characterized in that wherein the 3rd periphery wall has the 3rd outer perimeter, this second periphery wall has the second outer perimeter, this first periphery wall has the first outer perimeter, 3rd outer perimeter is greater than this second outer perimeter, and this second outer perimeter is not less than this first outer perimeter.
10. projection cube structure as claimed in claim 8, it is characterized in that wherein this substrate separately has protective layer, this protective layer is formed at this surface and covers above-mentioned weld pad.
11. projection cube structures as claimed in claim 8, is characterized in that wherein this first overlay segment covers this ring wall of this weld pad and this surface of this substrate.
12. projection cube structures as claimed in claim 10, is characterized in that wherein this first overlay segment is this protective layer covering this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110194648.3A CN102867758B (en) | 2011-07-08 | 2011-07-08 | Bumping manufacturing process and structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110194648.3A CN102867758B (en) | 2011-07-08 | 2011-07-08 | Bumping manufacturing process and structure thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102867758A CN102867758A (en) | 2013-01-09 |
| CN102867758B true CN102867758B (en) | 2015-12-02 |
Family
ID=47446537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110194648.3A Active CN102867758B (en) | 2011-07-08 | 2011-07-08 | Bumping manufacturing process and structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102867758B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9780052B2 (en) * | 2015-09-14 | 2017-10-03 | Micron Technology, Inc. | Collars for under-bump metal structures and associated systems and methods |
| CN105448755B (en) * | 2016-01-15 | 2019-02-15 | 中芯长电半导体（江阴）有限公司 | A kind of encapsulating method and structure of copper pillar bump |
| CN111128755B (en) * | 2019-12-30 | 2022-07-22 | 颀中科技（苏州）有限公司 | Packaging structure and forming method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101589467A (en) * | 2007-01-25 | 2009-11-25 | 卡西欧计算机株式会社 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6506671B1 (en) * | 2000-06-08 | 2003-01-14 | Micron Technology, Inc. | Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad |
| US6569753B1 (en) * | 2000-06-08 | 2003-05-27 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
| CN1176487C (en) * | 2000-09-18 | 2004-11-17 | 友达光电股份有限公司 | Structure with several convex and blocks having insulating side walls and its making method |
| JP2002270689A (en) * | 2001-03-13 | 2002-09-20 | Hitachi Ltd | Manufacturing method for semiconductor device |
| JP3829325B2 (en) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
| TWI252546B (en) * | 2004-11-03 | 2006-04-01 | Advanced Semiconductor Eng | Bumping process and structure thereof |
| US7919406B2 (en) * | 2009-07-08 | 2011-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming pillar bump structure having sidewall protection |
| US8324738B2 (en) * | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
| US9024431B2 (en) * | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US8659155B2 (en) * | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
-
2011
- 2011-07-08 CN CN201110194648.3A patent/CN102867758B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101589467A (en) * | 2007-01-25 | 2009-11-25 | 卡西欧计算机株式会社 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102867758A (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103165481B (en) | Bump manufacture technology and structure thereof | |
| CN102867758B (en) | Bumping manufacturing process and structure thereof | |
| WO2011066324A3 (en) | Magnetic tunnel junction device and fabrication | |
| WO2009142982A3 (en) | Metal gate structure and method of manufacturing same | |
| JP2018538697A5 (en) | ||
| JP2013520844A5 (en) | ||
| JP2015505643A5 (en) | ||
| JP2011187863A5 (en) | ||
| JP2011192973A5 (en) | Method of manufacturing transistor | |
| JP2011029491A (en) | Semiconductor device and method of fabricating the same | |
| US8841767B2 (en) | Bumping process and structure thereof | |
| US20130193570A1 (en) | Bumping process and structure thereof | |
| US8237288B1 (en) | Enhanced electromigration resistance in TSV structure and design | |
| CN104952822A (en) | Welding pad structure | |
| FI3561955T3 (en) | Antenna substrate | |
| CN102800599B (en) | Projection process and structure thereof | |
| CN102034740B (en) | Semiconductor device and method for fabricating same | |
| CN104183609B (en) | Semiconductor devices and preparation method thereof | |
| CN103137544A (en) | Semi-conductor chip structure and manufacture method of metal fuse in chip | |
| US20140065380A1 (en) | Overlay mark and method of forming the same | |
| US20120231624A1 (en) | Process for Producing Vertical Interconnections Through Structured Layers | |
| CN202758870U (en) | Semiconductor structure | |
| KR20150079934A (en) | Coil element production method | |
| TWI440150B (en) | Bumping process and structure thereof | |
| CN103367298A (en) | Semiconductor packaging structure and packaging method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |