CN102832250B - Irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET)for partitioning ring grating - Google Patents
Irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET)for partitioning ring grating Download PDFInfo
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- CN102832250B CN102832250B CN201210341406.7A CN201210341406A CN102832250B CN 102832250 B CN102832250 B CN 102832250B CN 201210341406 A CN201210341406 A CN 201210341406A CN 102832250 B CN102832250 B CN 102832250B
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Abstract
The invention relates to the field of semiconductor devices, in particular to a method for partitioning a ring grating irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET). The ring grating MOSFET is partitioned, the problem that a ring grating structure difficultly realizes smaller width to length ratio W/L is solved, so the channel leakage current and the device area are reduced. Three structures are provided according to different partition areas, the partition area of a structure 1 is realized through field oxygen, so the ring grating width W is reduced, and a certain irradiation resistant characteristic is obtained. The partition area of a structure 2 is introduced with a polysilicon gate (metal gate), a parasitic electric leakage channel between a source electrode and a drain electrode is inhibited, and strong irradiation resistance is obtained. The partition source/drain electrode of a structure 3 form a current mirror with the irradiation resistant characteristic, and the current mirror can also be used in an irradiation-free environment. The partitioned structure can inhibit the parasitic electric leakage channel between the source electrode and the drain electrode, the irradiation resistant characteristic is obtained, and moreover, the MOSFET is easily compatible with the conventional MOSFET technology.
Description
Technical field
The invention belongs to field of semiconductor devices, particularly relate to the method that ring gate metal oxide semiconductor field effect transistor (using MOSFET symbol in following file) is split.
Background technology
Semiconductor integrated circuit is widely used in the fields such as food irradiation preservation, Radiation Sterilization of Medical Products sterilization, radiation chemical engineering, space flight and aviation and nuclear industry.These radiation environments can cause damage to semiconductor device, the parameters such as the threshold voltage of device, mutual conductance, drive current and leakage current are degenerated, finally causes circuit malfunction.
For ensureing that semiconductor integrated circuit still reliably can complete predetermined function in radiation environment, various technical measures must be taked to reduce the impact of irradiation on semiconductor device.These measures comprise: use silicon-on-insulator (SOI), GaAs (GaAs), gallium nitride (GaN) etc. to have the new material of stronger anti-radiation performance; Adopt on high-quality radioresistance gate dielectric film, improvement gate oxidation method and Optimizing Technical, minimizing gate oxide thickness, shell and apply radioresistance coating, employing Vacuum Package carries out radiation hardened to device; Also can consider from the angle of circuit design, optimized circuit structure, adopt ring grid domain, add guard ring, strengthen the anti-radiation performance of integrated circuit.Wherein, current mirror, as one of the most basic element circuit of analog integrated circuit, requires during its layout design that each mirror device concentrates in together, and overall structure is as far as possible symmetrical, to improve the matching performance of circuit.During radiation environment application, each device of current mirror will carry out Flouride-resistani acid phesphatase design equally.Segmentation ring grid method of the present invention can meet the requirement to domain when current mirror Flouride-resistani acid phesphatase designs.
Gate-all-around structure is one of effective Flouride-resistani acid phesphatase measure that layout design can be taked.Fig. 1 is the domain schematic diagram of a surrounding-gate MOSFET, and it comprises drain/source 1, grid 2 and source/drain 3.Can see, the grid 2 of surrounding-gate MOSFET is loop configuration, there is not the edge in grid width direction, eliminates the edge parasitic leak channel between source and drain, the degeneration of the leakage current performance that can effectively suppress irradiation to cause.But the girth due to ring-shaped gate in figure below is device grid width W, and the grid in the radial direction of ring are of a size of the long L of device gate, therefore ring gate device is difficult to realize less breadth length ratio W/L.In fact, MOSFET leakage current also comprises the electric leakage in raceway groove between source and drain between two PN junctions, and this leakage current is directly proportional to device W/L.Therefore, ring gate device structure is unfavorable for that the PN junction reduced between source and drain leaks electricity.In addition, gate-all-around structure area is comparatively large, is unfavorable for integrated chip.
Summary of the invention
The object of the invention is to be difficult to do little problem to solve ring grid W/L, surrounding-gate MOSFET is split, to reducing ring grid grid width W, reducing channel leak current, saving area simultaneously, be conducive to integrated chip.
The gate shapes of surrounding-gate MOSFET can be polygon ring or annulus etc., and in practical application, conventional have straight-flanked ring, hexagon ring, annulus etc.
As Fig. 2, the present invention is introduced for straight-flanked ring gate MOSFET, and after segmentation, this surrounding-gate MOSFET comprises drain/source 1, grid 2, source/drain 3 and cut section 4, and the segmentation content of the following stated is applicable equally to other gate shapes.
Namely the present invention is split with cut section 4 pairs of surrounding-gate MOSFET transistors according to the thought of segmentation ring grid, is divided into two and above mosfet transistor, is common source/leakage or altogether grid common source/grid drain structure altogether altogether altogether between each MOSFET after segmentation.
An independent MOSFET element larger for script W/L can be divided into the MOSFET element that several W/L are less to the segmentation of ring grid.Below surrounding-gate MOSFET is divided into two MOSFET to introduce the present invention.As shown in Figure 2, surrounding-gate MOSFET is divided into two MOSFET by two cut sections 4.The drain/source 1 of these two MOSFET, grid 2 and source/drain 3 are a part for former surrounding-gate MOSFET.Its channel length L is identical with former surrounding-gate MOSFET, but channel width W reduces.The present invention proposes three kinds of different structures with regard to the different implementations of cut section 4.
The domain schematic diagram of structure one, as Fig. 3, its whole cut section 4 use oxygen 5 realizes, and is used for isolating two MOSFET.While segmentation surrounding-gate MOSFET, the segmentation portion of ring grid grid creates grid width border, i.e. the contact interface of grid 2 and cut section 4 in Fig. 2.The existence on these borders can induce edge parasitic leak channel between source and drain.In order to suppress these parasitic leakage passages, in cut section 4, from the contact interface of grid 2 and cut section 4, grow one section of polysilicon gate (or metal gate) 7, as Fig. 5 and Fig. 8.The work function of P+ polysilicon gate and metal gate (as aluminium, copper) is larger than N+ polysilicon gate, therefore large than N+ polysilicon gate MOSFET of the threshold voltage of P+ polysilicon gate and metal gate (as aluminium, copper) MOSFET under the same terms, thus play the effect of Flouride-resistani acid phesphatase.In addition, the position of cut section and size can determine the breadth length ratio W/L of two MOSFET.Increase the quantity of cut section 4, several common sources/drain MOSFET altogether can be formed, due to little W/L, there is certain Flouride-resistani acid phesphatase effect.Fig. 4 is the generalized section at AA' place in Fig. 3.
The domain schematic diagram of structure two is as Fig. 5, and cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8.In cut section 4, polysilicon gate (or metal gate) 7 is from the grid width boundary of two MOSFET to active area extension, and remainder is field oxygen 5.The work function of P+ polysilicon gate and metal gate (as aluminium, copper) is larger than N+ polysilicon gate, therefore large than N+ polysilicon gate MOSFET of the threshold voltage of P+ polysilicon gate and metal gate (as aluminium, copper) MOSFET under the same terms.Therefore, in order to suppress parasitic leakage passage, for PMOS transistor, cut section adopts N+ polysilicon gate (or metal gate); For nmos pass transistor, cut section adopts P+ polysilicon gate (or metal gate).Meanwhile, the grid oxygen under polysilicon gate (or metal gate) 7 is thin, and growth quality is high, the Fixed oxide charge that irradiation produces and silicon and silicon dioxide (Si-SiO
2) interfacial state is few.And field oxygen does not directly contact with the grid oxygen of MOSFET after segmentation, reduces the impact of interface on device of this two oxides, can the anti-radiation performance of enhance device further.According to aforementioned principles, adopt N+, P+ polysilicon gate at cut section respectively, the segmentation of P type ring grid, N-type ring grid can be realized.Pair pmos transistor of the present invention and nmos pass transistor have all carried out radiation hardened thus, can be applied in the cmos circuit of Flouride-resistani acid phesphatase.Fig. 6 is the generalized section at BB' place in Fig. 5.Fig. 7 is the generalized section at CC' place in Fig. 5.The position of cut section and size can determine the breadth length ratio W/L of two MOSFET.Increase the quantity of cut section 4, several common sources/drain MOSFET altogether can be formed.
Figure 11,12 simulation results are structure one, two Ids-Vgs curve charts after predose.Can find out, two kinds of structures all have certain Radiation hardness.Structure two leakage current is less, has stronger anti-radiation performance.
The feature of structure three only splits source/drain, do not split grid, and the grid common source altogether of the MOSFET therefore after segmentation/being total to grid leaks altogether.And this symmetrical configuration, compact, meet the layout design requirement of current mirror, can use as current mirror, meanwhile, because each pipe be partitioned into has radiation-resisting performance, the current mirror of formation also just has certain anti-radiation performance.
The domain schematic diagram of structure three is as 8, and cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7, grid oxygen 8 and medium 9.Wherein polysilicon gate (or metal gate) 7 connects with grid 2.Fig. 9 is the generalized section at DD' place in Fig. 8.Figure 10 is the generalized section at EE' place in Fig. 8.As can be seen from Fig. 9 and Figure 10, the lower zone of the grid oxygen 8 of polysilicon gate (or metal gate) 7 correspondence has medium 9, and this medium 9 can use silicon dioxide (SiO
2) fill.This structure two drain/source current, respectively as input current and image current, by changing position and the size of cut section 4, can change the ratio of input current and image current, forming the current mirror of various ratio.
Accompanying drawing explanation
Fig. 1 is the domain schematic diagram of surrounding-gate MOSFET.
Fig. 2 is the domain schematic diagram with cut section 4, surrounding-gate MOSFET being divided into two MOSFET.
Fig. 3 is the domain schematic diagram of the structure one that cut section 4 use oxygen realizes.
Fig. 4 is the generalized section at AA' place in Fig. 3.
Fig. 5 is the domain schematic diagram of the structure two that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8.
Fig. 6 is the generalized section at BB' place in Fig. 5.
Fig. 7 is the generalized section at CC' place in Fig. 5.
Fig. 8 is the domain schematic diagram of the structure three that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8, medium 9.
Fig. 9 is the generalized section at DD' place in Fig. 8.
Figure 10 is the generalized section at EE' place in Fig. 8.
Figure 11 is NMOS tube Ids-Vgs curve chart after predose of structure one and structure two, and field oxygen 5 adopts LOCOS technique.
Figure 12 is NMOS tube Ids-Vgs curve chart after predose of structure one and structure two, and field oxygen 5 adopts STI technique.
In figure, each serial number name sees the following form:
| 1 | Ring grid drain/source | 6 | Substrate |
| 2 | Ring grid grid | 7 | Polysilicon gate (metal gate) |
| 3 | Ring grid source/drain | 8 | Grid oxygen |
| 4 | Cut section | 9 | Medium |
| 5 | Field oxygen |
Embodiment:
By reference to the accompanying drawings, the technological process making each structure of the present invention is provided, further illustrates the present invention.
One. cut section 4 adopts the technological process of the structure one of field oxygen 5:
Step one: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3n
4) film;
Step 2: etch silicon nitride, exposes an oxygen 5 region, adopts LOCOS technique or STI technique or groove isolation technology to field oxygen 5 region, forms field oxygen 5 as shown in Fig. 3,4;
Step 3: remove silicon nitride film and silicon oxide film, expose active area silicon face;
Step 4: silicon chip surface grows one deck grid oxygen silica, forms grid oxygen 8;
Step 5: depositing polysilicon on grid oxygen, etches ring grid grid 2, forms ring grid grid 2 as shown in Figure 3;
Step 6: carry out source and drain injection in source/drain 1 and drain/source 3;
Step 7: make passivation layer and complete element manufacturing.
Two. the technological process of the structure two that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8:
Step one: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3n
4) film;
Step 2: etch silicon nitride, exposes an oxygen 5 region, adopts LOCOS technique or STI technique or groove isolation technology to field oxygen 5 region, forms field oxygen 5 as shown in Fig. 5,7;
Step 3: remove silicon nitride film and silicon oxide film, expose active area silicon face;
Step 4: silicon chip surface grows one deck grid oxygen silica, forms grid oxygen 8 as shown in Fig. 6,7;
Step 5: depositing polysilicon on grid oxygen, etches ring grid grid 2, forms ring grid grid 2 as shown in Fig. 5,7;
Step 6: depositing polysilicon (or aluminium, copper) on grid oxygen: NMOS deposit P+ polysilicon (or aluminium, copper), etch polysilicon P+ polysilicon (or aluminium, copper), forms polysilicon gate (or metal gate) 7 as shown in Fig. 5,6,7; PMOS deposit N+ polysilicon (or aluminium, copper), etch polysilicon N+ polysilicon (or aluminium, copper), forms polysilicon gate (or metal gate) 7 as shown in Fig. 5,6,7;
Step 7: carry out source and drain injection in source/drain 1 and drain/source 3;
Step 8: make passivation layer and complete element manufacturing.
Three. the technological process of the structure three that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8, medium 9:
Step one: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3n
4) film;
Step 2: etch silicon nitride, exposes an oxygen 5 region, adopts LOCOS technique or STI technique or groove isolation technology to field oxygen 5 region, forms field oxygen 5 as shown in Fig. 8,9;
Step 3: remove silicon nitride film and silicon oxide film, expose active area silicon face;
Step 4: polysilicon gate (or metal gate) 7 region cutting in fig. 8, filled media, forms medium 9 as shown in Fig. 9,10;
Step 5: silicon chip surface grows one deck grid oxygen silica, forms grid oxygen 8 as shown in Fig. 9,10;
Step 6: depositing polysilicon on grid oxygen, etches ring grid grid 2, forms ring grid grid 2 as shown in Fig. 8,10;
Step 7: depositing polysilicon (or aluminium, copper) on grid oxygen, NMOS deposit P+ polysilicon (or aluminium, copper), etch polysilicon P+ polysilicon (or aluminium, copper), forms polysilicon gate (or metal gate) 7 as shown in Fig. 8,9,10; PMOS deposit N+ polysilicon (or aluminium, copper), etch polysilicon N+ polysilicon (or aluminium, copper), forms polysilicon gate (or metal gate) 7 as shown in Fig. 8,9,10;
Step 8: carry out source and drain injection in source/drain 1 and drain/source 3;
Step 9: make passivation layer and complete element manufacturing.
Claims (9)
1. split the Flouride-resistani acid phesphatase N-type MOSFET of ring grid for one kind, containing drain/source (1), grid (2) and source/drain (3), cut section (4), is characterized in that: cut section (4) is made up of field oxygen (5), polysilicon gate/metal gate (7) and grid oxygen (8); Or cut section (4) is made up of field oxygen (5), polysilicon gate/metal gate (7), grid oxygen (8) and medium (9), the former, when cut section (4) is made up of field oxygen (5), polysilicon gate/metal gate (7) and grid oxygen (8), cut section (4) is polysilicon gate/metal gate (7)-field oxygen (5)-polysilicon gate/metal gate (7) structure in grid width direction, is polysilicon gate/metal gate (7)-grid oxygen (8)-substrat structure in vertical-channel in-plane polysilicon gate/metal gate (7) section; The latter, when cut section (4) is made up of field oxygen (5), polysilicon gate/metal gate (7), grid oxygen (8) and medium (9), cut section (4) is grid oxygen (8)-polysilicon gate/metal gate (7) structure in orientation, be polysilicon gate/metal gate (7)-grid oxygen (8)-medium (9) structure in vertical-channel in-plane polysilicon gate/metal gate (7) section, wherein in cut section (4), the work function of polysilicon gate/metal gate (7) is larger than the work function of ring grid before segmentation.
2. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 1, is characterized in that:
Ring grid nmos pass transistor, the polysilicon gate introduced in cut section (4) or the grid material of metal gate (7) adopt P+ polysilicon or aluminium or copper, and the MOSFET that segmentation ring grid NMOS produces has the performance of Flouride-resistani acid phesphatase.
3. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 1, is characterized in that:
The ring grid (2) of cut section (4) to surrounding-gate MOSFET are split, source/drain (3) and leakage/source (1) of surrounding-gate MOSFET remain unchanged, the MOSFET that segmentation produces is common source/drain structure altogether, and all MOSFET share a leakage/source (1);
Cut section (4) is split the source/drain (3) of surrounding-gate MOSFET and ring grid (2), leakage/the source (1) of surrounding-gate MOSFET remains unchanged, the MOSFET that segmentation produces is common grid common source/grid drain structure altogether altogether, and all MOSFET share a leakage/source (1) and grid.
4. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 3, is characterized in that:
Cut section (4) is split ring grid (2), and polysilicon gate or metal gate (7) in cut section (4), cover from the MOSFET grid width be partitioned into the subregion outside active area;
Cut section (4) is split source/drain (3) and ring grid (2), cut section (4) interior polysilicon gate or metal gate (7), cover from the MOSFET grid width be partitioned into the Zone Full outside active area.
5. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 1, it is characterized in that: cut section (4) is split surrounding-gate MOSFET, multiple MOSFET is created after segmentation, the grid width W of the MOSFET that segmentation produces is less than the grid width W of former ring grid, and the W/L of surrounding-gate MOSFET is reduced.
6. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 2, it is characterized in that: cut section (4) is split the source/drain (3) of surrounding-gate MOSFET and ring grid (2), it is common grid common source/grid drain structure altogether altogether between each MOSFET after segmentation, symmetrical configuration after this segmentation, compact, for the layout design of Flouride-resistani acid phesphatase current mirror or electric current sink structure.
7. the Flouride-resistani acid phesphatase N-type MOSFET of the segmentation ring grid according to claim 5,6, it is characterized in that: the position and the size that change cut section (4), the ratio of input current and image current can be changed, the current mirror of the Flouride-resistani acid phesphatase of various ratio can be formed.
8. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 1, is characterized in that: cut section (4) internal field oxygen (5) can adopt LOCOS technique or STI technique or groove isolation process to produce.
9. the Flouride-resistani acid phesphatase N-type MOSFET of segmentation ring grid according to claim 1, is characterized in that: to segmentation its gate shapes of surrounding-gate MOSFET be polygon ring or annulus.
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| CN113889537B (en) * | 2021-12-07 | 2022-03-04 | 北京芯可鉴科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN116153926B (en) * | 2023-01-10 | 2023-10-17 | 中国电子科技集团公司第五十八研究所 | Small-channel-width NMOS (N-channel metal oxide semiconductor) tube layout reinforcing structure resistant to total dose radiation |
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| CN102412303A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Layout reinforcement structure of large-head strip-shaped grid MOS (metal oxide semiconductor) tube with total-dose radiation effect resistance |
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