CN102832250A - Method for partitioning ring grating irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET) - Google Patents
Method for partitioning ring grating irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET) Download PDFInfo
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- CN102832250A CN102832250A CN2012103414067A CN201210341406A CN102832250A CN 102832250 A CN102832250 A CN 102832250A CN 2012103414067 A CN2012103414067 A CN 2012103414067A CN 201210341406 A CN201210341406 A CN 201210341406A CN 102832250 A CN102832250 A CN 102832250A
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Abstract
The invention relates to the field of semiconductor devices, in particular to a method for partitioning a ring grating irradiation-resistant metal-oxide-semiconductor field-effect transistor (MOSFET). The ring grating MOSFET is partitioned, the problem that a ring grating structure difficultly realizes smaller width to length ratio W/L is solved, so the channel leakage current and the device area are reduced. Three structures are provided according to different partition areas, the partition area of a structure 1 is realized through field oxygen, so the ring grating width W is reduced, and a certain irradiation resistant characteristic is obtained. The partition area of a structure 2 is introduced with a polysilicon gate (metal gate), a parasitic electric leakage channel between a source electrode and a drain electrode is inhibited, and strong irradiation resistance is obtained. The partition source/drain electrode of a structure 3 form a current mirror with the irradiation resistant characteristic, and the current mirror can also be used in an irradiation-free environment. The partitioned structure can inhibit the parasitic electric leakage channel between the source electrode and the drain electrode, the irradiation resistant characteristic is obtained, and moreover, the MOSFET is easily compatible with the conventional MOSFET technology.
Description
Technical field
The invention belongs to field of semiconductor devices, relate in particular to the method that ring gate metal oxide semiconductor field effect transistor (using the MOSFET symbol in the following file) is cut apart.
Background technology
Semiconductor integrated circuit is widely used in the fields such as food irradiation preservation, medical supplies radiation sterilization sterilization, radiation chemical engineering, space flight and aviation and nuclear industry.These radiation environments can cause damage to semiconductor device, and the parameters such as threshold voltage, mutual conductance, drive current and leakage current of device are degenerated, and finally cause circuit malfunction.
In radiation environment, still can accomplish predetermined function reliably for the assurance semiconductor integrated circuit, must take various technical measures to reduce the influence of irradiation semiconductor device.These measures comprise: use silicon-on-insulator (SOI), GaAs (GaAs), gallium nitride (GaN) etc. that the new material of strong anti-radiation performance is arranged; Adopt high-quality radioresistance gate dielectric film, improvement gate oxidation method and optimization process conditions, reduce coating radioresistance coating on gate oxide thickness, the shell, adopt Vacuum Package that device is carried out anti-irradiation reinforcing; Also can consider, optimize circuit structure, adopt ring grid domain, add guard ring, strengthen the anti-radiation performance of integrated circuit from the angle of circuit design.Wherein, current mirror requires each mirror device to concentrate in together as one of the most basic element circuit of analog integrated circuit during its layout design, and overall structure is symmetry as far as possible, to improve the matching performance of circuit.When radiation environment was used, each device of current mirror will carry out anti-irradiation design equally.Of the present invention when cutting apart ring grid method and can satisfy the anti-irradiation design of current mirror to the requirement of domain.
Gate-all-around structure is one of the effective anti-irradiation measure that can take on the layout design.Fig. 1 is the domain sketch map of a surrounding-gate MOSFET, and it comprises leakage/source electrode 1, grid 2 and source/drain electrode 3.Can see that the grid 2 of surrounding-gate MOSFET is a loop configuration, does not have the edge of grid width direction, the edge parasitic leakage passage between leak in the source of having eliminated can suppress the degeneration of the leakage current performance that irradiation causes effectively.But because the girth of ring-shaped gate is device grid width W in figure below, and the grid that the footpath of ring makes progress are of a size of the long L of device grid, and therefore encircling gate device is difficult to realize less breadth length ratio W/L.In fact, the MOSFET leakage current also comprise source in the raceway groove leak between electric leakage between two PN junctions, and this leakage current is directly proportional with device W/L.Therefore, ring gate device structure is unfavorable for the PN junction electric leakage between the leakage of reduction source.In addition, the gate-all-around structure area is bigger, is unfavorable for that chip is integrated.
Summary of the invention
The objective of the invention is to be difficult to do little problem, surrounding-gate MOSFET is cut apart,, reduce channel leak current in the hope of reducing to encircle grid grid width W in order to solve ring grid W/L, the while save area, it is integrated to help chip.
The gate shapes of surrounding-gate MOSFET can be polygon ring or annulus etc., and in the practical application, using always has straight-flanked ring, hexagon ring, annulus etc.
Like Fig. 2, the present invention is that example is introduced with the straight-flanked ring gate MOSFET, and this surrounding-gate MOSFET comprises leakage/source electrode 1, grid 2, source/drain electrode 3 and cut section 4 after cutting apart, the following stated to cut apart content suitable equally to other gate shapes.
The present invention is promptly cut apart with 4 pairs of surrounding-gate MOSFET transistors of cut section according to cutting apart the thought of encircling grid, is divided into two and above mosfet transistor, is common source/leak altogether or the grid of grid common source/altogether drain structure altogether altogether between each MOSFET after cutting apart.
To can the bigger independent MOSFET device of script W/L being divided into the less MOSFET device of several W/L cutting apart of ring grid.Be that example is introduced the present invention surrounding-gate MOSFET is divided into two MOSFET below.As shown in Figure 2, two cut sections 4 are divided into two MOSFET with surrounding-gate MOSFET.Leakage/source electrode 1 of these two MOSFET, grid 2 and source/drain electrode 3 is the part of former surrounding-gate MOSFET.Its channel length L is identical with former surrounding-gate MOSFET, but channel width W reduces.The present invention has proposed three kinds of various structure with regard to the different implementations of cut section 4.
The domain sketch map of structure one, like Fig. 2, its whole cut section 4 use oxygen 5 realize, are used for isolating two MOSFET.The position of cut section and size can determine the breadth length ratio W/L of two MOSFET.Increase the quantity of cut section 4, can form several common sources/common drain MOSFET, because little W/L has certain anti-irradiation effect.Fig. 4 is the generalized section at AA' place among Fig. 3.
When cutting apart surrounding-gate MOSFET, the place of cutting apart of ring grid grid has produced the grid width border, i.e. the contact interface of grid 2 and cut section 4 among Fig. 2.The existence on these borders can induce edge parasitic leakage passage between the leakage of source.In order to suppress these parasitic leakage passages, in cut section 4, from the contact interface of grid 2 and the cut section 4 one section polysilicon gate (or metal gate) 7 that begins to grow, like Fig. 5 and Fig. 8.The work function of P+ polysilicon gate and metal gate (like aluminium, copper) is bigger than N+ polysilicon gate, so big than N+ polysilicon gate MOSFET of the threshold voltage of P+ polysilicon gate and metal gate (like aluminium, copper) MOSFET under the same terms.Therefore, in order to suppress the parasitic leakage passage, for the PMOS transistor, cut section adopts N+ polysilicon gate (or metal gate); For nmos pass transistor, cut section adopts P+ polysilicon gate (or metal gate).Simultaneously, the grid oxygen under the polysilicon gate (or metal gate) 7 is thin, and growth quality is high, oxide layer fixed charge and silicon and silicon dioxide (Si-SiO that irradiation produces
2) interfacial state is few.And oxygen not with cut apart after the grid oxygen of MOSFET directly contact, weakened of the influence of the interface of these two kinds of oxides, further the anti-radiation performance of enhance device to device.
According to aforementioned principles, adopt N+, P+ polysilicon gate at cut section respectively, can realize cutting apart of P type ring grid, N type ring grid.Pair pmos transistor of the present invention thus and nmos pass transistor have all carried out anti-irradiation to be reinforced, and can be applied in the cmos circuit of anti-irradiation.
Domain sketch map such as Fig. 5 of structure two, cut section 4 is made up of with grid oxygen 8 field oxygen 5, polysilicon gate (or metal gate) 7.In the cut section 4, polysilicon gate (or metal gate) 7 extends outside active area from the grid width boundary of two MOSFET, and remainder is an oxygen 5.Fig. 6 is the generalized section at BB' place among Fig. 5.Fig. 7 is the generalized section at CC' place among Fig. 5.The position of cut section and size can determine the breadth length ratio W/L of two MOSFET.Increase the quantity of cut section 4, can form several common sources/common drain MOSFET.
Figure 11,12 simulation results are structure one, two Ids-Vgs curve charts behind predose.Can find out that two kinds of structures all have certain anti-irradiation ability.Structure two leakage currents are littler, and stronger anti-radiation performance is arranged.
The characteristics of structure three are segmented source/drain electrodes, do not cut apart grid, and the grid common source/grid leak the MOSFET after therefore cutting apart altogether altogether altogether.And this symmetrical configuration, compactness, satisfy the layout design requirement of current mirror, can be used as current mirror and use, simultaneously, because each pipe that is partitioned into has radiation-resisting performance, the current mirror of formation also just has certain anti-radiation performance.
The domain sketch map of structure three is as 8, and cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7, grid oxygen 8 and medium 9.Wherein polysilicon gate (or metal gate) 7 joins with grid 2.Fig. 9 is the generalized section at DD' place among Fig. 8.Figure 10 is the generalized section at EE' place among Fig. 8.Can find out that from Fig. 9 and Figure 10 the lower zone of the grid oxygen 8 of polysilicon gate (or metal gate) 7 correspondences has medium 9, this medium 9 can be used silicon dioxide (SiO
2) fill.Two drain/source current of this structure through changing the position and the size of cut section 4, can change the ratio of input current and image current respectively as input current and image current, form the current mirror of various ratios.
Description of drawings
Fig. 1 is the domain sketch map of surrounding-gate MOSFET.
Fig. 2 is the domain sketch map that surrounding-gate MOSFET is divided into two MOSFET with cut section 4.
Fig. 3 is the domain sketch map of the structure one of cut section 4 use oxygen realization.
Fig. 4 is the generalized section at AA' place among Fig. 3.
The domain sketch map of Fig. 5 structure two that to be cut section 4 be made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8.
Fig. 6 is the generalized section at BB' place among Fig. 5.
Fig. 7 is the generalized section at CC' place among Fig. 5.
The domain sketch map of Fig. 8 structure three that to be cut section 4 be made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8, medium 9.
Fig. 9 is the generalized section at DD' place among Fig. 8.
Figure 10 is the generalized section at EE' place among Fig. 8.
Figure 11 is NMOS pipe Ids-Vgs curve chart behind predose of structure one and structure two, and an oxygen 5 adopts LOCOS technology.
Figure 12 is NMOS pipe Ids-Vgs curve chart behind predose of structure one and structure two, and an oxygen 5 adopts STI technology.
Each serial number name sees the following form among the figure:
| 1 | Ring grid leak/ |
6 | |
| 2 | |
7 | Polysilicon gate (metal gate) |
| 3 | Ring grid source/ |
8 | |
| 4 | |
9 | Medium |
| 5 | Field oxygen |
Embodiment:
In conjunction with accompanying drawing, the technological process of making each structure of the present invention is provided, further specify the present invention.
One. cut section 4 adopts the technological process of the structure one of an oxygen 5:
Step 1: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3N
4) film;
Step 2: etch silicon nitride, expose an oxygen 5 zones, LOCOS technology or STI technology or groove isolation technology are adopted in oxygen 5 zones in field, form like Fig. 3, an oxygen 5 shown in 4;
Step 3: remove silicon nitride film and silicon oxide film, expose the active area silicon face;
Step 4: silicon chip surface growth one deck grid oxygen silica forms grid oxygen 8;
Step 5: deposit polysilicon on grid oxygen, etch ring grid grid 2, form and encircle grid grid 2 as shown in Figure 3;
Step 6: in the source/drain electrode 1 and leakage/source electrode 3 carry out the source and leak and inject;
Step 7: make passivation layer and accomplish element manufacturing.
Two. the technological process of the structure two that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8:
Step 1: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3N
4) film;
Step 2: etch silicon nitride, expose an oxygen 5 zones, LOCOS technology or STI technology or groove isolation technology are adopted in oxygen 5 zones in field, form like Fig. 5, an oxygen 5 shown in 7;
Step 3: remove silicon nitride film and silicon oxide film, expose the active area silicon face;
Step 4: silicon chip surface growth one deck grid oxygen silica forms like Fig. 6, the oxygen of grid shown in 78;
Step 5: deposit polysilicon on grid oxygen, etch ring grid grid 2, form like Fig. 5, the grid of ring shown in 7 grid 2;
Step 6: deposit polysilicon on grid oxygen (or aluminium, copper): NMOS deposit P+ polysilicon (or aluminium, copper), etch polysilicon P+ polysilicon (or aluminium, copper) forms like Fig. 5,6, polysilicon gate shown in 7 (or metal gate) 7; PMOS deposit N+ polysilicon (or aluminium, copper), etch polysilicon N+ polysilicon (or aluminium, copper) forms like Fig. 5,6, polysilicon gate shown in 7 (or metal gate) 7;
Step 7: in the source/drain electrode 1 and leakage/source electrode 3 carry out the source and leak and inject;
Step 8: make passivation layer and accomplish element manufacturing.
Three. the technological process of the structure three that cut section 4 is made up of field oxygen 5, polysilicon gate (or metal gate) 7 and grid oxygen 8, medium 9:
Step 1: silicon chip surface deposit layer of silicon dioxide (SiO
2) film does pad oxygen, deposit one deck silicon nitride (Si on silicon oxide film
3N
4) film;
Step 2: etch silicon nitride, expose an oxygen 5 zones, LOCOS technology or STI technology or groove isolation technology are adopted in oxygen 5 zones in field, form like Fig. 8, an oxygen 5 shown in 9;
Step 3: remove silicon nitride film and silicon oxide film, expose the active area silicon face;
Step 4: the polysilicon gate in Fig. 8 (or metal gate) 7 regional cuttings, fill medium, form like Fig. 9, medium shown in 10 9;
Step 5: silicon chip surface growth one deck grid oxygen silica forms like Fig. 9, the oxygen of grid shown in 10 8;
Step 6: deposit polysilicon on grid oxygen, etch ring grid grid 2, form like Fig. 8, the grid of ring shown in 10 grid 2;
Step 7: deposit polysilicon on grid oxygen (or aluminium, copper), NMOS deposit P+ polysilicon (or aluminium, copper), etch polysilicon P+ polysilicon (or aluminium, copper) forms like Fig. 8,9, polysilicon gate shown in 10 (or metal gate) 7; PMOS deposit N+ polysilicon (or aluminium, copper), etch polysilicon N+ polysilicon (or aluminium, copper) forms like Fig. 8,9, polysilicon gate shown in 10 (or metal gate) 7;
Step 8: in the source/drain electrode 1 and leakage/source electrode 3 carry out the source and leak and inject;
Step 9: make passivation layer and accomplish element manufacturing.
Claims (9)
1. cut apart the anti-irradiation MOSFET that encircles grid for one kind; Contain leakage/source electrode (1), grid (2) and source/drain electrode (3); It is characterized in that: surrounding-gate MOSFET is cut apart with cut section (4); Being divided into two above MOSFET, is common source/leak altogether or the grid of grid common source/altogether drain structure altogether altogether between each MOSFET that is partitioned into.
2. the MOSFET that encircles grid of cutting apart according to claim 1 is characterized in that: cut section (4) only adopts an oxygen to isolate, and is the drain structure of common source/altogether between each MOSFET that is partitioned into, and has reduced the grid width W of ring grid after cutting apart, and W/L is reduced.
3. the anti-irradiation MOSFET that encircles grid of cutting apart according to claim 1; It is characterized in that: cut section (4) is made up of field oxygen (5), polysilicon gate or metal gate (7) and grid oxygen (8); Polysilicon gate or metal gate (7) extend outside active area from the MOSFET grid width that is partitioned in cut section (4), and remainder is an oxygen (5); Between each MOSFET that is partitioned into common source/common drain structure, parasitic leakage passage between leak in ability inhibition source.
4. the anti-irradiation MOSFET that encircles grid of cutting apart according to claim 1; It is characterized in that: cut section (4) is made up of field oxygen (5), polysilicon gate or metal gate (7), grid oxygen (8) and medium (9); Polysilicon gate or metal gate (7) link together the MOSFET grid that separates; Be that common grid common source/grid are total to drain structure altogether between each MOSFET after promptly cutting apart, the symmetrical configuration after this is cut apart, compactness are in order to realize the layout design of current mirror or electric current sink structure; And be used for anti-irradiation current mirror or the heavy design of electric current, and has the performance of anti-irradiation.
5. the anti-irradiation MOSFET that encircles grid of cutting apart according to claim 1, it is characterized in that: its gate shapes of surrounding-gate MOSFET to cutting apart is polygon ring or annulus.
6. according to claim 2,3, the 4 described anti-irradiation MOSFET that encircle grid of cutting apart, it is characterized in that: an oxygen (5) can adopt LOCOS technology or STI technology or groove isolation process.
7. according to claim 3, the 4 described anti-irradiation MOSFET that encircle grid of cutting apart, it is characterized in that: for ring grid PMOS transistor, the polysilicon gate of introducing in the cut section or the grid material of metal gate (7) adopt N+ polysilicon or aluminium or copper; For ring grid nmos pass transistor, the grid material of interior polysilicon gate of introducing of cut section or metal gate (7) adopts P+ polysilicon or aluminium or copper, cuts apart ring grid PMOS simultaneously and encircles the cmos device that grid NMOS can realize anti-irradiation.
8. the anti-irradiation MOSFET that encircles grid of cutting apart according to claim 1; It is characterized in that: the breadth length ratio W/L of the position of cut section (4) and size decision MOSFET; Increase the quantity of cut section (4), can increase and cut apart drain MOSFET of back common source/altogether or the grid of the grid common source/altogether quantity of drain MOSFET altogether altogether.
9. the anti-irradiation MOSFET that encircles grid of cutting apart according to claim 4 is characterized in that: change the position and the size of cut section (4), can change the ratio of input current and image current, can form the current mirror of various ratios.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687716A (en) * | 2020-12-28 | 2021-04-20 | 中国电子科技集团公司第四十四研究所 | CCD amplifier structure for improving ionization effect irradiation resistance |
| CN113889537A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN116153926B (en) * | 2023-01-10 | 2023-10-17 | 中国电子科技集团公司第五十八研究所 | Small-channel-width NMOS (N-channel metal oxide semiconductor) tube layout reinforcing structure resistant to total dose radiation |
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|---|---|---|---|---|
| US20060197108A1 (en) * | 2005-03-03 | 2006-09-07 | Gardner Harry N | Total ionizing dose suppression transistor architecture |
| US20090212854A1 (en) * | 2008-02-25 | 2009-08-27 | Peter Baumgartner | Asymmetric Segmented Channel Transistors |
| CN102412303A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Layout reinforcement structure of large-head strip-shaped grid MOS (metal oxide semiconductor) tube with total-dose radiation effect resistance |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197108A1 (en) * | 2005-03-03 | 2006-09-07 | Gardner Harry N | Total ionizing dose suppression transistor architecture |
| US20090212854A1 (en) * | 2008-02-25 | 2009-08-27 | Peter Baumgartner | Asymmetric Segmented Channel Transistors |
| CN102412303A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Layout reinforcement structure of large-head strip-shaped grid MOS (metal oxide semiconductor) tube with total-dose radiation effect resistance |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687716A (en) * | 2020-12-28 | 2021-04-20 | 中国电子科技集团公司第四十四研究所 | CCD amplifier structure for improving ionization effect irradiation resistance |
| CN112687716B (en) * | 2020-12-28 | 2022-06-24 | 中国电子科技集团公司第四十四研究所 | CCD amplifier structure for improving ionization effect irradiation resistance |
| CN113889537A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN116153926B (en) * | 2023-01-10 | 2023-10-17 | 中国电子科技集团公司第五十八研究所 | Small-channel-width NMOS (N-channel metal oxide semiconductor) tube layout reinforcing structure resistant to total dose radiation |
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