CN102832174A - Method for improving static random access memory reading redundancy - Google Patents
Method for improving static random access memory reading redundancy Download PDFInfo
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- CN102832174A CN102832174A CN2012101587146A CN201210158714A CN102832174A CN 102832174 A CN102832174 A CN 102832174A CN 2012101587146 A CN2012101587146 A CN 2012101587146A CN 201210158714 A CN201210158714 A CN 201210158714A CN 102832174 A CN102832174 A CN 102832174A
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Abstract
The invention discloses a method for improving static random access memory reading redundancy. The method comprises the following process: through a polycrystalline silicon pre-injection process for removing a control tube; the polycrystalline silicon doping concentration of the control tube is reduced, an equivalent resistance of the control tube is increased, and the random memory reading redundancy is increased. With the adoption of the method for improving static random access memory reading redundancy provided by the invention, the doping concentration of a polysilicon gate of the control tube is reduced effectively without carrying out pre-injection on a control tube area any longer, thereby a parasitic resistance of the polysilicon gate and the polysilicon gate use-up phenomenon are increased, a threshold voltage of the control tube is increased, a starting current is reduced, and at the same time the equivalent resistance of the control tube is increased; and during a reading process, the potential of a node 8 is reduced, thereby increasing the reading redundancy of the random access memory.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate in particular to a kind of method that the static random holder is read redundancy that improves.
Background technology
Static random access memory (Static Random Access Memory is called for short SRAM) has obtained using widely in high-speed data exchange systems such as computer, communication, multimedia as one type of staple product in the semiconductor memory.As shown in Figure 1 is the domain structure of one the 90 common sram cell below the nanometer, includes these three levels of source region, polysilicon gate and contact hole.What zone 21 was marked among the figure is control valve (Pass Gate); This zone is a nmos area territory; What zone 22 was marked is following trombone slide (Pull Down MOS); This zone is similarly a nmos area territory, and what zone 23 was marked is last trombone slide (Pull Up MOS), and this zone is PMOS zone.
Reading redundancy is to weigh sram cell to read an important parameter of performance, as shown in Figure 2, is the work sketch map of a SRAM zone when reading; 4 is control valve among the figure, and 5 are following trombone slide, and 6 is last trombone slide; Suppose that node 7 storage data are high potential (promptly store data and be " 1 "), and corresponding, node 8 storage data are electronegative potential (promptly store data and be " 0 "); Before reading action, bit line 9 can be precharged to high potential with bit line 10, when reading the action beginning; Word line 11 is opened, because the data of node 7 storages are high potential, so the voltage on the bit line 9 remains unchanged; And because the data of node 8 storages are electronegative potential, the voltage meeting quilt on the bit line 10 is accomplished the action of reading of sram cell to drop-down through perception bit line 9 and the voltage difference on the bit line 10.A condition that must guarantee is arranged in readout, can not change the data of original storage in the sram cell exactly.After word line 11 is opened; Voltage on the bit line 10 is by drop-down the time; The current potential of node 8 also can be pulled up to an intermediate potential simultaneously; Promptly no longer keep " 0 ", the size of intermediate potential is to be determined by the ratio of trombone slide and control valve down, promptly can be regarded as drop-down pipe and control valve equivalent resistance ratio determined.In order not change in the sram cell data of original storage, the intermediate potential of node 8 is asked to must be less than certain numerical value, promptly descends the ratio of the equivalent resistance of trombone slide and control valve must be less than certain value.Here it is, and SRAM reads the requirement of reading redundancy when moving.Increase the equivalent resistance of control valve, can reduce the intermediate potential of node 8, thereby increase the redundancy of reading of sram cell.
Progress along with technology generations; Particularly in the following technology generations of 45 nanometers, can adopt the preparatory injection technology of polysilicon gate, before the polysilicon gate etching processing step; The grid in nmos area territory is carried out the preparatory injection of group-v element, and the grid in PMOS zone is carried out the preparatory injection of group iii elements.Purpose is to reduce gate resistance and reduce the polysilicon gate tcam-exhaustion.To reach the purpose of regulating CMOS region threshold voltage (Vt) and firing current (Ion).For sram cell; Usually can carry out the preparatory injection of group-v element to control valve and these two nmos area territories of following trombone slide in the technology; The preparatory injection of group-v element is carried out with zone 22 in zone 21 in as shown in Figure 1, and the last trombone slide (PMOS zone) in zone 23 is carried out the preparatory injection of group iii elements.Like this; Usually in the technology, the polysilicon gate doping content of control valve raises, thereby the dead resistance and the polysilicon gate that have reduced polysilicon gate exhaust phenomenon; Make the control valve threshold voltage reduce; Firing current increases, thereby has reduced the equivalent resistance of control valve, and the not high problem of performance of reading of random asccess memory takes place.
Summary of the invention
Disclosure of the Invention a kind ofly improve the method that the static random holder is read redundancy.In order to solve in the prior art; In the domain structure technology of the sram cell below 45 nanometers; The grid in nmos area territory is carried out the preparatory injection of group-v element, and the grid in PMOS zone is carried out the preparatory injection of group iii elements, thereby the not high problem of performance of reading of random asccess memory takes place.
For realizing above-mentioned purpose, the technical scheme that invention is adopted is:
A kind ofly improve the method that the static random holder is read redundancy, wherein, comprise following processing step:
Step 1 generates the NMOS polysilicon gate and injects photolithography plate in advance on domain, make common nmos area territory be opened, and makes that the control valve zone is capped in the SRAM domain, and territory, drop-down area under control is opened;
Step 2 generates the PMOS polysilicon gate and injects photolithography plate in advance on domain, make in common PMOS zone and the SRAM domain on trombone slide be opened;
Step 3 is utilized the NMOS polysilicon gate to inject photolithography plate in advance and is carried out the preparatory injection technology of polysilicon gate, and the injection of pentels is carried out in territory, drop-down area under control in common nmos area territory and the SRAM domain;
Above-mentioned raising static random holder is read the method for redundancy, and wherein, said triels is B, Ga and IN.
Above-mentioned raising static random holder is read the method for redundancy, and wherein, said pentels is P, As and Sb.
Above-mentioned raising static random holder is read the method for redundancy, wherein, has reduced the current potential of node (8).
A kind ofly among the present invention improve the method that the static random holder is read redundancy, having adopted as above, scheme has following effect:
1, can be through no longer the control valve zone being injected in advance; The doping content of control valve polysilicon gate is reduced; Thereby the dead resistance and the polysilicon gate that have increased polysilicon gate exhaust phenomenon, cause the threshold voltage of control valve to increase, and firing current reduces;
2, increase the equivalent resistance of control valve simultaneously, in reading process, reduced the current potential of node 8, thereby improved the redundancy of reading of random asccess memory.
Description of drawings
Through the detailed description that reading is done non-limiting example with reference to following accompanying drawing, the further feature of invention, it is more obvious that purpose and advantage will become.
Fig. 1 improves the sketch map of SRAM domain that the static random holder is read the method for redundancy for a kind of;
Fig. 2 reads the sketch map that the method SRAM of redundancy reads work for a kind of static random holder that improves;
Fig. 3 is a kind of processing step sketch map that the static random holder is read the method for redundancy that improves.
Embodiment
For technological means that invention is realized, create characteristic, reach purpose and effect and be easy to understand and understand that following combinations specifically illustrates, and further sets forth the present invention.
Like Fig. 1,2, shown in 3, a kind ofly improve the method that the static random holder is read redundancy, wherein, comprise following processing step:
Step 1 generates the NMOS polysilicon gate and injects photolithography plate in advance on domain, make common nmos area territory (not shown) be opened, and makes that control valve zone 21 is capped in the SRAM domain, and territory, drop-down area under control 22 is opened;
Step 2 generates the PMOS polysilicon gate and injects photolithography plate in advance on domain, make in common PMOS zone (not shown) and the SRAM domain on trombone slide 23 be opened;
Step 3 is utilized the NMOS polysilicon gate to inject photolithography plate in advance and is carried out the preparatory injection technology of polysilicon gate, and the injection of pentels is carried out in territory, drop-down area under control 22 in common nmos area territory and the SRAM domain;
In specific embodiment of the present invention, triels is B, Ga, IN.
In specific embodiment of the present invention, pentels is P, As, Sb.
In specific embodiment of the present invention, reduced the current potential of node (8), further can in reading process, improve the redundancy of random access memory.
In specific embodiment of the present invention, reduced the current potential of node (8), make node 8 storage data in reading process, can better remain electronegative potential (promptly store data and be " 0 "), increased the redundancy of reading of sram cell.Before reading action, bit line 9 can be precharged to high potential with bit line 10, when reading the action beginning; Word line 11 is opened; Because the data of node 7 storage are high potential, thus the voltage on the bit line 9 remain unchanged, and because the data of node 8 storages are electronegative potential; Voltage meeting quilt on the bit line 10 is accomplished the action of reading of sram cell to drop-down through perception bit line 9 and the voltage difference on the bit line 10.A condition that must guarantee is arranged in readout, can not change the data of original storage in the sram cell exactly.After word line 11 is opened; Voltage on the bit line 10 is by drop-down the time; The current potential of node 8 also can be pulled up to an intermediate potential simultaneously, promptly no longer keeps " 0 ", further; The size of intermediate potential is to be determined by the following ratio of trombone slide and control valve, promptly can be regarded as drop-down pipe and control valve equivalent resistance ratio determined.Because the intermediate potential of node 8 is asked to and must the data of original storage in the sram cell is not changed less than certain numerical value, promptly descend the ratio of the equivalent resistance of trombone slide and control valve must be less than certain value.Here it is, and SRAM reads the requirement of reading redundancy when moving.Wherein, increase the equivalent resistance of control valve, can reduce the intermediate potential of node 8, thereby increase the redundancy of reading of sram cell.
In sum, invent a kind of method that the static random holder is read redundancy that improves, can be through no longer the control valve zone being injected in advance; The doping content of control valve polysilicon gate is reduced; Thereby the dead resistance and the polysilicon gate that have increased polysilicon gate exhaust phenomenon, cause the threshold voltage of control valve to increase, and firing current reduces; Increased the equivalent resistance of control valve simultaneously; In reading process, reduced the current potential of node 8, thereby improved the redundancy of reading of random asccess memory.
More than to the invention specific embodiment be described.It will be appreciated that invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence the essence of an invention content.
Claims (4)
1. one kind is improved the method that the static random holder is read redundancy, it is characterized in that, comprises following processing step:
Step 1 generates the NMOS polysilicon gate and injects photolithography plate in advance on domain, make common nmos area territory be opened, and makes that the control valve zone is capped in the SRAM domain, and territory, drop-down area under control is opened;
Step 2 generates the PMOS polysilicon gate and injects photolithography plate in advance on domain, make in common PMOS zone and the SRAM domain on trombone slide be opened;
Step 3 is utilized the NMOS polysilicon gate to inject photolithography plate in advance and is carried out the preparatory injection technology of polysilicon gate, and the injection of pentels is carried out in territory, drop-down area under control in common nmos area territory and the SRAM domain;
Step 4 is utilized the PMOS polysilicon gate to inject reticle in advance and is carried out the preparatory injection technology of polysilicon gate, carries out the injection of triels to going up the trombone slide zone in common PMOS zone and the SRAM domain, to accomplish last injection technology.
2. raising static random holder according to claim 1 is read the method for redundancy, it is characterized in that, said triels is B, Ga and IN.
3. raising static random holder according to claim 1 is read the method for redundancy, it is characterized in that, said pentels is P, As and Sb.
4. raising static random holder according to claim 1 is read the method for redundancy, it is characterized in that, has reduced the current potential of node (8).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107017873A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Digital circuit structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174412A (en) * | 1996-05-13 | 1998-02-25 | 现代电子产业株式会社 | High load resistance type static random access memory cell and method for forming the same |
| US20070257308A1 (en) * | 2006-05-03 | 2007-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modifying work function in PMOS devices by counter-doping |
| CN101640187A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Four layer transistor SRAM unit manufacturing method |
| JP4477197B2 (en) * | 2000-05-18 | 2010-06-09 | Ｎｅｃエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174412A (en) * | 1996-05-13 | 1998-02-25 | 现代电子产业株式会社 | High load resistance type static random access memory cell and method for forming the same |
| JP4477197B2 (en) * | 2000-05-18 | 2010-06-09 | Ｎｅｃエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US20070257308A1 (en) * | 2006-05-03 | 2007-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modifying work function in PMOS devices by counter-doping |
| CN101640187A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Four layer transistor SRAM unit manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017873A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Digital circuit structure |
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